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RISC-V: implement low-level interrupt handling
Add support for a routine that dispatches exceptions with the interrupt flags set to either the IPI or irqdomain code (and the clock source in the future). Loosely based on the irq-riscv-int.c irqchip driver from the RISC-V tree. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2 changed files with 45 additions and 11 deletions
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@ -168,8 +168,8 @@ ENTRY(handle_exception)
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/* Handle interrupts */
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move a0, sp /* pt_regs */
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REG_L a1, handle_arch_irq
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jr a1
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move a1, s4 /* scause */
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tail do_IRQ
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1:
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/* Exceptions run with interrupts enabled */
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csrs sstatus, SR_SIE
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@ -1,21 +1,55 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* Copyright (C) 2018 Christoph Hellwig
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*/
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#include <linux/interrupt.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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/*
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* Possible interrupt causes:
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*/
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#define INTERRUPT_CAUSE_SOFTWARE 1
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#define INTERRUPT_CAUSE_TIMER 5
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#define INTERRUPT_CAUSE_EXTERNAL 9
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/*
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* The high order bit of the trap cause register is always set for
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* interrupts, which allows us to differentiate them from exceptions
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* quickly. The INTERRUPT_CAUSE_* macros don't contain that bit, so we
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* need to mask it off.
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*/
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#define INTERRUPT_CAUSE_FLAG (1UL << (__riscv_xlen - 1))
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asmlinkage void __irq_entry do_IRQ(struct pt_regs *regs, unsigned long cause)
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{
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struct pt_regs *old_regs = set_irq_regs(regs);
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irq_enter();
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switch (cause & ~INTERRUPT_CAUSE_FLAG) {
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#ifdef CONFIG_SMP
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case INTERRUPT_CAUSE_SOFTWARE:
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/*
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* We only use software interrupts to pass IPIs, so if a non-SMP
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* system gets one, then we don't know what to do.
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*/
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riscv_software_interrupt();
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break;
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#endif
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case INTERRUPT_CAUSE_EXTERNAL:
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handle_arch_irq(regs);
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break;
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default:
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panic("unexpected interrupt cause");
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}
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irq_exit();
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set_irq_regs(old_regs);
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}
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void __init init_IRQ(void)
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{
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irqchip_init();
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