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mtd: denali.h: fixed checkpatch errors
Fix all checkpatch.pl complaints. Artem: tweaked a little and fix tab indentations, so now this is not only about checkpatch, but also about making indentations look sane. Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
parent
1c3275b656
commit
6ea9ad2418
1 changed files with 78 additions and 82 deletions
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@ -17,7 +17,7 @@
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*
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*/
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand.h>
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#define DEVICE_RESET 0x0
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#define DEVICE_RESET__BANK0 0x0001
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@ -29,7 +29,7 @@
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#define TRANSFER_SPARE_REG__FLAG 0x0001
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#define LOAD_WAIT_CNT 0x20
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#define LOAD_WAIT_CNT__VALUE 0xffff
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#define LOAD_WAIT_CNT__VALUE 0xffff
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#define PROGRAM_WAIT_CNT 0x30
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#define PROGRAM_WAIT_CNT__VALUE 0xffff
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@ -83,7 +83,7 @@
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#define RE_2_WE 0x120
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#define RE_2_WE__VALUE 0x003f
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#define ACC_CLKS 0x130
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#define ACC_CLKS 0x130
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#define ACC_CLKS__VALUE 0x000f
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#define NUMBER_OF_PLANES 0x140
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@ -140,7 +140,7 @@
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#define DEVICES_CONNECTED 0x250
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#define DEVICES_CONNECTED__VALUE 0x0007
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#define DIE_MASK 0x260
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#define DIE_MASK 0x260
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#define DIE_MASK__VALUE 0x00ff
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#define FIRST_BLOCK_OF_NEXT_PLANE 0x270
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@ -152,7 +152,7 @@
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#define RE_2_RE 0x290
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#define RE_2_RE__VALUE 0x003f
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#define MANUFACTURER_ID 0x300
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#define MANUFACTURER_ID 0x300
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#define MANUFACTURER_ID__VALUE 0x00ff
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#define DEVICE_ID 0x310
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@ -173,13 +173,13 @@
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#define LOGICAL_PAGE_SPARE_SIZE 0x360
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#define LOGICAL_PAGE_SPARE_SIZE__VALUE 0xffff
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#define REVISION 0x370
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#define REVISION 0x370
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#define REVISION__VALUE 0xffff
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#define ONFI_DEVICE_FEATURES 0x380
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#define ONFI_DEVICE_FEATURES__VALUE 0x003f
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#define ONFI_OPTIONAL_COMMANDS 0x390
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#define ONFI_OPTIONAL_COMMANDS 0x390
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#define ONFI_OPTIONAL_COMMANDS__VALUE 0x003f
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#define ONFI_TIMING_MODE 0x3a0
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@ -201,12 +201,12 @@
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#define FEATURES 0x3f0
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#define FEATURES__N_BANKS 0x0003
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#define FEATURES__ECC_MAX_ERR 0x003c
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#define FEATURES__DMA 0x0040
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#define FEATURES__DMA 0x0040
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#define FEATURES__CMD_DMA 0x0080
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#define FEATURES__PARTITION 0x0100
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#define FEATURES__XDMA_SIDEBAND 0x0200
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#define FEATURES__GPREG 0x0400
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#define FEATURES__INDEX_ADDR 0x0800
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#define FEATURES__INDEX_ADDR 0x0800
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#define TRANSFER_MODE 0x400
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#define TRANSFER_MODE__VALUE 0x0003
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@ -235,12 +235,12 @@
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#define INTR_EN0__DMA_CMD_COMP 0x0004
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#define INTR_EN0__TIME_OUT 0x0008
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#define INTR_EN0__PROGRAM_FAIL 0x0010
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#define INTR_EN0__ERASE_FAIL 0x0020
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#define INTR_EN0__ERASE_FAIL 0x0020
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#define INTR_EN0__LOAD_COMP 0x0040
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#define INTR_EN0__PROGRAM_COMP 0x0080
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#define INTR_EN0__ERASE_COMP 0x0100
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#define INTR_EN0__ERASE_COMP 0x0100
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#define INTR_EN0__PIPE_CPYBCK_CMD_COMP 0x0200
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#define INTR_EN0__LOCKED_BLK 0x0400
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#define INTR_EN0__LOCKED_BLK 0x0400
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#define INTR_EN0__UNSUP_CMD 0x0800
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#define INTR_EN0__INT_ACT 0x1000
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#define INTR_EN0__RST_COMP 0x2000
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@ -253,7 +253,7 @@
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#define ERR_PAGE_ADDR0 0x440
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#define ERR_PAGE_ADDR0__VALUE 0xffff
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#define ERR_BLOCK_ADDR0 0x450
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#define ERR_BLOCK_ADDR0 0x450
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#define ERR_BLOCK_ADDR0__VALUE 0xffff
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#define INTR_STATUS1 0x460
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@ -280,12 +280,12 @@
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#define INTR_EN1__DMA_CMD_COMP 0x0004
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#define INTR_EN1__TIME_OUT 0x0008
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#define INTR_EN1__PROGRAM_FAIL 0x0010
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#define INTR_EN1__ERASE_FAIL 0x0020
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#define INTR_EN1__ERASE_FAIL 0x0020
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#define INTR_EN1__LOAD_COMP 0x0040
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#define INTR_EN1__PROGRAM_COMP 0x0080
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#define INTR_EN1__ERASE_COMP 0x0100
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#define INTR_EN1__ERASE_COMP 0x0100
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#define INTR_EN1__PIPE_CPYBCK_CMD_COMP 0x0200
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#define INTR_EN1__LOCKED_BLK 0x0400
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#define INTR_EN1__LOCKED_BLK 0x0400
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#define INTR_EN1__UNSUP_CMD 0x0800
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#define INTR_EN1__INT_ACT 0x1000
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#define INTR_EN1__RST_COMP 0x2000
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@ -298,7 +298,7 @@
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#define ERR_PAGE_ADDR1 0x490
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#define ERR_PAGE_ADDR1__VALUE 0xffff
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#define ERR_BLOCK_ADDR1 0x4a0
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#define ERR_BLOCK_ADDR1 0x4a0
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#define ERR_BLOCK_ADDR1__VALUE 0xffff
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#define INTR_STATUS2 0x4b0
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@ -325,12 +325,12 @@
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#define INTR_EN2__DMA_CMD_COMP 0x0004
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#define INTR_EN2__TIME_OUT 0x0008
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#define INTR_EN2__PROGRAM_FAIL 0x0010
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#define INTR_EN2__ERASE_FAIL 0x0020
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#define INTR_EN2__ERASE_FAIL 0x0020
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#define INTR_EN2__LOAD_COMP 0x0040
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#define INTR_EN2__PROGRAM_COMP 0x0080
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#define INTR_EN2__ERASE_COMP 0x0100
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#define INTR_EN2__ERASE_COMP 0x0100
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#define INTR_EN2__PIPE_CPYBCK_CMD_COMP 0x0200
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#define INTR_EN2__LOCKED_BLK 0x0400
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#define INTR_EN2__LOCKED_BLK 0x0400
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#define INTR_EN2__UNSUP_CMD 0x0800
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#define INTR_EN2__INT_ACT 0x1000
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#define INTR_EN2__RST_COMP 0x2000
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@ -343,7 +343,7 @@
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#define ERR_PAGE_ADDR2 0x4e0
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#define ERR_PAGE_ADDR2__VALUE 0xffff
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#define ERR_BLOCK_ADDR2 0x4f0
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#define ERR_BLOCK_ADDR2 0x4f0
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#define ERR_BLOCK_ADDR2__VALUE 0xffff
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#define INTR_STATUS3 0x500
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@ -370,12 +370,12 @@
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#define INTR_EN3__DMA_CMD_COMP 0x0004
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#define INTR_EN3__TIME_OUT 0x0008
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#define INTR_EN3__PROGRAM_FAIL 0x0010
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#define INTR_EN3__ERASE_FAIL 0x0020
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#define INTR_EN3__ERASE_FAIL 0x0020
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#define INTR_EN3__LOAD_COMP 0x0040
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#define INTR_EN3__PROGRAM_COMP 0x0080
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#define INTR_EN3__ERASE_COMP 0x0100
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#define INTR_EN3__ERASE_COMP 0x0100
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#define INTR_EN3__PIPE_CPYBCK_CMD_COMP 0x0200
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#define INTR_EN3__LOCKED_BLK 0x0400
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#define INTR_EN3__LOCKED_BLK 0x0400
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#define INTR_EN3__UNSUP_CMD 0x0800
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#define INTR_EN3__INT_ACT 0x1000
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#define INTR_EN3__RST_COMP 0x2000
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@ -388,7 +388,7 @@
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#define ERR_PAGE_ADDR3 0x530
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#define ERR_PAGE_ADDR3__VALUE 0xffff
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#define ERR_BLOCK_ADDR3 0x540
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#define ERR_BLOCK_ADDR3 0x540
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#define ERR_BLOCK_ADDR3__VALUE 0xffff
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#define DATA_INTR 0x550
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@ -412,9 +412,9 @@
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#define GPREG_3__VALUE 0xffff
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#define ECC_THRESHOLD 0x600
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#define ECC_THRESHOLD__VALUE 0x03ff
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#define ECC_THRESHOLD__VALUE 0x03ff
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#define ECC_ERROR_BLOCK_ADDRESS 0x610
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#define ECC_ERROR_BLOCK_ADDRESS 0x610
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#define ECC_ERROR_BLOCK_ADDRESS__VALUE 0xffff
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#define ECC_ERROR_PAGE_ADDRESS 0x620
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@ -466,7 +466,7 @@
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#define CHNL_ACTIVE__CHANNEL3 0x0008
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#define ACTIVE_SRC_ID 0x800
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#define ACTIVE_SRC_ID__VALUE 0x00ff
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#define ACTIVE_SRC_ID__VALUE 0x00ff
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#define PTN_INTR 0x810
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#define PTN_INTR__CONFIG_ERROR 0x0001
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@ -485,7 +485,7 @@
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#define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020
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#define PERM_SRC_ID_0 0x830
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#define PERM_SRC_ID_0__SRCID 0x00ff
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#define PERM_SRC_ID_0__SRCID 0x00ff
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#define PERM_SRC_ID_0__DIRECT_ACCESS_ACTIVE 0x0800
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#define PERM_SRC_ID_0__WRITE_ACTIVE 0x2000
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#define PERM_SRC_ID_0__READ_ACTIVE 0x4000
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@ -502,7 +502,7 @@
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#define MIN_MAX_BANK_0__MAX_VALUE 0x000c
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#define PERM_SRC_ID_1 0x870
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#define PERM_SRC_ID_1__SRCID 0x00ff
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#define PERM_SRC_ID_1__SRCID 0x00ff
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#define PERM_SRC_ID_1__DIRECT_ACCESS_ACTIVE 0x0800
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#define PERM_SRC_ID_1__WRITE_ACTIVE 0x2000
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#define PERM_SRC_ID_1__READ_ACTIVE 0x4000
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#define MIN_MAX_BANK_1__MAX_VALUE 0x000c
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#define PERM_SRC_ID_2 0x8b0
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#define PERM_SRC_ID_2__SRCID 0x00ff
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#define PERM_SRC_ID_2__SRCID 0x00ff
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#define PERM_SRC_ID_2__DIRECT_ACCESS_ACTIVE 0x0800
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#define PERM_SRC_ID_2__WRITE_ACTIVE 0x2000
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#define PERM_SRC_ID_2__READ_ACTIVE 0x4000
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#define MIN_MAX_BANK_2__MAX_VALUE 0x000c
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#define PERM_SRC_ID_3 0x8f0
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#define PERM_SRC_ID_3__SRCID 0x00ff
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#define PERM_SRC_ID_3__SRCID 0x00ff
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#define PERM_SRC_ID_3__DIRECT_ACCESS_ACTIVE 0x0800
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#define PERM_SRC_ID_3__WRITE_ACTIVE 0x2000
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#define PERM_SRC_ID_3__READ_ACTIVE 0x4000
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#define MIN_MAX_BANK_3__MAX_VALUE 0x000c
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#define PERM_SRC_ID_4 0x930
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#define PERM_SRC_ID_4__SRCID 0x00ff
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#define PERM_SRC_ID_4__SRCID 0x00ff
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#define PERM_SRC_ID_4__DIRECT_ACCESS_ACTIVE 0x0800
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#define PERM_SRC_ID_4__WRITE_ACTIVE 0x2000
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#define PERM_SRC_ID_4__READ_ACTIVE 0x4000
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#define MIN_MAX_BANK_4__MAX_VALUE 0x000c
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#define PERM_SRC_ID_5 0x970
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#define PERM_SRC_ID_5__SRCID 0x00ff
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#define PERM_SRC_ID_5__SRCID 0x00ff
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#define PERM_SRC_ID_5__DIRECT_ACCESS_ACTIVE 0x0800
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#define PERM_SRC_ID_5__WRITE_ACTIVE 0x2000
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#define PERM_SRC_ID_5__READ_ACTIVE 0x4000
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#define MIN_MAX_BANK_5__MAX_VALUE 0x000c
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#define PERM_SRC_ID_6 0x9b0
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#define PERM_SRC_ID_6__SRCID 0x00ff
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#define PERM_SRC_ID_6__SRCID 0x00ff
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#define PERM_SRC_ID_6__DIRECT_ACCESS_ACTIVE 0x0800
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#define PERM_SRC_ID_6__WRITE_ACTIVE 0x2000
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#define PERM_SRC_ID_6__READ_ACTIVE 0x4000
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#define MIN_MAX_BANK_6__MAX_VALUE 0x000c
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#define PERM_SRC_ID_7 0x9f0
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#define PERM_SRC_ID_7__SRCID 0x00ff
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#define PERM_SRC_ID_7__SRCID 0x00ff
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#define PERM_SRC_ID_7__DIRECT_ACCESS_ACTIVE 0x0800
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#define PERM_SRC_ID_7__WRITE_ACTIVE 0x2000
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#define PERM_SRC_ID_7__READ_ACTIVE 0x4000
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/* flash.h */
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struct device_info_tag {
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uint16_t wDeviceMaker;
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uint16_t wDeviceID;
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uint16_t wDeviceMaker;
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uint16_t wDeviceID;
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uint8_t bDeviceParam0;
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uint8_t bDeviceParam1;
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uint8_t bDeviceParam2;
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uint32_t wDeviceType;
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uint32_t wSpectraStartBlock;
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uint32_t wSpectraEndBlock;
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uint32_t wTotalBlocks;
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uint16_t wPagesPerBlock;
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uint16_t wPageSize;
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uint16_t wPageDataSize;
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uint16_t wPageSpareSize;
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uint16_t wNumPageSpareFlag;
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uint16_t wECCBytesPerSector;
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uint32_t wBlockSize;
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uint32_t wBlockDataSize;
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uint32_t wDataBlockNum;
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uint8_t bPlaneNum;
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uint16_t wDeviceMainAreaSize;
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uint16_t wDeviceSpareAreaSize;
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uint16_t wDevicesConnected;
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uint16_t wDeviceWidth;
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uint16_t wHWRevision;
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uint16_t wHWFeatures;
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uint16_t wONFIDevFeatures;
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uint16_t wONFIOptCommands;
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uint16_t wONFITimingMode;
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uint16_t wONFIPgmCacheTimingMode;
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uint16_t MLCDevice;
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uint16_t wSpareSkipBytes;
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uint8_t nBitsInPageNumber;
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uint8_t nBitsInPageDataSize;
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uint8_t nBitsInBlockDataSize;
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uint32_t wDeviceType;
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uint32_t wSpectraStartBlock;
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uint32_t wSpectraEndBlock;
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uint32_t wTotalBlocks;
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uint16_t wPagesPerBlock;
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uint16_t wPageSize;
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uint16_t wPageDataSize;
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uint16_t wPageSpareSize;
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uint16_t wNumPageSpareFlag;
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uint16_t wECCBytesPerSector;
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uint32_t wBlockSize;
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uint32_t wBlockDataSize;
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uint32_t wDataBlockNum;
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uint8_t bPlaneNum;
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uint16_t wDeviceMainAreaSize;
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uint16_t wDeviceSpareAreaSize;
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uint16_t wDevicesConnected;
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uint16_t wDeviceWidth;
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uint16_t wHWRevision;
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uint16_t wHWFeatures;
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uint16_t wONFIDevFeatures;
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uint16_t wONFIOptCommands;
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uint16_t wONFITimingMode;
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uint16_t wONFIPgmCacheTimingMode;
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uint16_t MLCDevice;
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uint16_t wSpareSkipBytes;
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uint8_t nBitsInPageNumber;
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uint8_t nBitsInPageDataSize;
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uint8_t nBitsInBlockDataSize;
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};
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/* ffsdefs.h */
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#define NAND_DBG_TRACE 3
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#ifdef VERBOSE
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#define nand_dbg_print(level, args...) \
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do { \
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if (level <= nand_debug_level) \
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printk(KERN_ALERT args); \
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} while (0)
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#define nand_dbg_print(level, args...) \
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do { \
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if (level <= nand_debug_level) \
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printk(KERN_ALERT args); \
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} while (0)
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#else
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#define nand_dbg_print(level, args...)
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#endif
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#define ECC_SECTOR_SIZE 512
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#define LLD_MAX_FLASH_BANKS 4
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#define DENALI_BUF_SIZE NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE
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#define DENALI_BUF_SIZE (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE)
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struct nand_buf
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{
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struct nand_buf {
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int head;
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int tail;
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uint8_t buf[DENALI_BUF_SIZE];
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int idx;
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};
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static uint16_t NAND_Flash_Reset(struct denali_nand_info *denali);
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static uint16_t NAND_Read_Device_ID(struct denali_nand_info *denali);
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static void NAND_LLD_Enable_Disable_Interrupts(struct denali_nand_info *denali, uint16_t INT_ENABLE);
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static uint16_t NAND_Flash_Reset(struct denali_nand_info *denali);
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static uint16_t NAND_Read_Device_ID(struct denali_nand_info *denali);
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static void NAND_LLD_Enable_Disable_Interrupts(struct denali_nand_info *denali,
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uint16_t INT_ENABLE);
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#endif /*_LLD_NAND_*/
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