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pci: mvebu: fix the emulation of the status register
The status register of the PCI configuration space of PCI-to-PCI bridges contain some read-only bits, and so write-1-to-clear bits. So, the Linux PCI core sometimes writes 0xffff to this status register, and in the current PCI-to-PCI bridge emulation code of the Marvell driver, we do take all those 1s being written. Even the read-only bits are being overwritten. For now, all the read-only bits should be emulated to have the zero value. The other bits, that are write-1-to-clear bits are used to report various kind of errors, and are never set by the emulated bridge, so there is no need to support this write-1-to-clear bits mechanism. As a conclusion, the easiest solution is to simply emulate this status register by returning zero when read, and ignore the writes to it. This has two visible effects: * The devsel is no longer 'unknown' in, i.e Flags: bus master, 66MHz, user-definable features, ?? devsel, latency 0 becomes: Flags: bus master, 66MHz, user-definable features, fast devsel, latency 0 in lspci -v. This was caused by a value of 11b being read for devsel, which is an invalid value. This 11b value being read was due to a previous write of 0xffff into the status register. * The capability list is no longer broken, because we indicate to the Linux PCI core that we don't have a Capabilities Pointer in the PCI configuration space of this bridge. The following message is therefore no longer visible in lspci -v: Capabilities: [fc] <chain broken> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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parent
197fc226d9
commit
6eb237c41a
1 changed files with 1 additions and 4 deletions
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@ -69,7 +69,6 @@ struct mvebu_sw_pci_bridge {
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u16 vendor;
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u16 device;
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u16 command;
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u16 status;
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u16 class;
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u8 interface;
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u8 revision;
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@ -359,7 +358,6 @@ static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
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memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
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bridge->status = PCI_STATUS_CAP_LIST;
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bridge->class = PCI_CLASS_BRIDGE_PCI;
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bridge->vendor = PCI_VENDOR_ID_MARVELL;
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bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
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@ -386,7 +384,7 @@ static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
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break;
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case PCI_COMMAND:
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*value = bridge->status << 16 | bridge->command;
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*value = bridge->command;
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break;
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case PCI_CLASS_REVISION:
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@ -479,7 +477,6 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
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switch (where & ~3) {
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case PCI_COMMAND:
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bridge->command = value & 0xffff;
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bridge->status = value >> 16;
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break;
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case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
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