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irqchip/gic-v3: Ensure GICR_CTLR.EnableLPI=0 is observed before enabling
Booting with GICR_CTLR.EnableLPI=1 is usually a bad idea, and may result in subtle memory corruption. Detecting this is thus pretty important. On detecting that LPIs are still enabled, we taint the kernel (because we're not sure of anything anymore), and try to disable LPIs. This can fail, as implementations are allowed to implement GICR_CTLR.EnableLPI as a one-way enable, meaning the redistributors cannot be reprogrammed with new tables. Should this happen, we fail probing the redistributor and warn the user that things are pretty dire. Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org> [maz: reworded changelog, minor comment and message changes] Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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19d9916448
commit
6eb486b66a
2 changed files with 61 additions and 14 deletions
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@ -1879,16 +1879,6 @@ static void its_cpu_init_lpis(void)
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gic_data_rdist()->pend_page = pend_page;
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}
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/* Disable LPIs */
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val = readl_relaxed(rbase + GICR_CTLR);
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val &= ~GICR_CTLR_ENABLE_LPIS;
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writel_relaxed(val, rbase + GICR_CTLR);
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/*
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* Make sure any change to the table is observable by the GIC.
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*/
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dsb(sy);
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/* set PROPBASE */
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val = (page_to_phys(gic_rdists->prop_page) |
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GICR_PROPBASER_InnerShareable |
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@ -3403,13 +3393,69 @@ static bool gic_rdists_supports_plpis(void)
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return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
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}
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static int redist_disable_lpis(void)
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{
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void __iomem *rbase = gic_data_rdist_rd_base();
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u64 timeout = USEC_PER_SEC;
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u64 val;
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if (!gic_rdists_supports_plpis()) {
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pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
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return -ENXIO;
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}
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val = readl_relaxed(rbase + GICR_CTLR);
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if (!(val & GICR_CTLR_ENABLE_LPIS))
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return 0;
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pr_warn("CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
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smp_processor_id());
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add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
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/* Disable LPIs */
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val &= ~GICR_CTLR_ENABLE_LPIS;
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writel_relaxed(val, rbase + GICR_CTLR);
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/* Make sure any change to GICR_CTLR is observable by the GIC */
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dsb(sy);
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/*
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* Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
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* from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
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* Error out if we time out waiting for RWP to clear.
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*/
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while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
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if (!timeout) {
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pr_err("CPU%d: Timeout while disabling LPIs\n",
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smp_processor_id());
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return -ETIMEDOUT;
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}
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udelay(1);
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timeout--;
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}
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/*
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* After it has been written to 1, it is IMPLEMENTATION
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* DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
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* cleared to 0. Error out if clearing the bit failed.
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*/
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if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
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pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
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return -EBUSY;
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}
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return 0;
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}
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int its_cpu_init(void)
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{
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if (!list_empty(&its_nodes)) {
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if (!gic_rdists_supports_plpis()) {
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pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
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return -ENXIO;
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}
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int ret;
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ret = redist_disable_lpis();
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if (ret)
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return ret;
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its_cpu_init_lpis();
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its_cpu_init_collections();
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}
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@ -106,6 +106,7 @@
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#define GICR_PIDR2 GICD_PIDR2
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#define GICR_CTLR_ENABLE_LPIS (1UL << 0)
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#define GICR_CTLR_RWP (1UL << 3)
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#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)
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