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IB/hfi1: Ensure full Gen3 speed in a Gen4 system
commita9c3c4c597
upstream. If an hfi1 card is inserted in a Gen4 systems, the driver will avoid the gen3 speed bump and the card will operate at half speed. This is because the driver avoids the gen3 speed bump when the parent bus speed isn't identical to gen3, 8.0GT/s. This is not compatible with gen4 and newer speeds. Fix by relaxing the test to explicitly look for the lower capability speeds which inherently allows for gen4 and all future speeds. Fixes:7724105686
("IB/hfi1: add driver files") Link: https://lore.kernel.org/r/20191101192059.106248.1699.stgit@awfm-01.aw.intel.com Cc: <stable@vger.kernel.org> Reviewed-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Reviewed-by: Kaike Wan <kaike.wan@intel.com> Signed-off-by: James Erwin <james.erwin@intel.com> Signed-off-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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1 changed files with 3 additions and 1 deletions
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@ -331,7 +331,9 @@ int pcie_speeds(struct hfi1_devdata *dd)
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/*
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* bus->max_bus_speed is set from the bridge's linkcap Max Link Speed
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*/
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if (parent && dd->pcidev->bus->max_bus_speed != PCIE_SPEED_8_0GT) {
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if (parent &&
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(dd->pcidev->bus->max_bus_speed == PCIE_SPEED_2_5GT ||
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dd->pcidev->bus->max_bus_speed == PCIE_SPEED_5_0GT)) {
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dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n");
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dd->link_gen3_capable = 0;
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}
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