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drm/i915/gen9: Add WaOCLCoherentLineFlush
This is mainly required for future enabling of pre-emptive command execution. v2: explain purpose of change (Chris) Reviewed-by: Nick Hoath <nicholas.hoath@intel.com> Cc: Dave Gordon <david.s.gordon@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1453412634-29238-9-git-send-email-arun.siluvery@linux.intel.com Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -981,6 +981,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
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/* WaDisableSTUnitPowerOptimization:skl,bxt */
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WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
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/* WaOCLCoherentLineFlush:skl,bxt */
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I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
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GEN8_LQSC_FLUSH_COHERENT_LINES));
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/* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
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ret= wa_ring_whitelist_reg(ring, GEN8_CS_CHICKEN1);
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if (ret)
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