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drm/i915: Unset reset pch handshake when PCH is not present in one place
Right now RESET_PCH_HANDSHAKE_ENABLE is enabled all the times inside of intel_power_domains_init_hw() and if PCH is NOP it is unsed in i915_gem_init_hw(). So making skl_pch_reset_handshake() handle both cases and calling it for the missing gens in intel_power_domains_init_hw(). Ivybridge have a different register and bits but with the same objective so moving it too. v2(Rodrigo): - handling IVYBRIDGE case inside intel_pch_reset_handshake() v4(Rodrigo and Ville): - moving the enable/disable decision to callers Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180918204714.27306-2-jose.souza@intel.com
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parent
7c86828d56
commit
6edafc4eb3
2 changed files with 20 additions and 20 deletions
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@ -5301,18 +5301,6 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
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I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
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LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
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if (HAS_PCH_NOP(dev_priv)) {
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if (IS_IVYBRIDGE(dev_priv)) {
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u32 temp = I915_READ(GEN7_MSG_CTL);
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temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
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I915_WRITE(GEN7_MSG_CTL, temp);
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} else if (INTEL_GEN(dev_priv) >= 7) {
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u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
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temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
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I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
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}
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}
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intel_gt_workarounds_apply(dev_priv);
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i915_gem_init_swizzling(dev_priv);
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@ -3243,14 +3243,25 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
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static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
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bool enable)
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{
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u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);
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i915_reg_t reg;
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u32 reset_bits, val;
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if (IS_IVYBRIDGE(dev_priv)) {
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reg = GEN7_MSG_CTL;
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reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK;
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} else {
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reg = HSW_NDE_RSTWRN_OPT;
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reset_bits = RESET_PCH_HANDSHAKE_ENABLE;
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}
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val = I915_READ(reg);
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if (enable)
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val |= RESET_PCH_HANDSHAKE_ENABLE;
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val |= reset_bits;
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else
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val &= ~RESET_PCH_HANDSHAKE_ENABLE;
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val &= ~reset_bits;
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I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
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I915_WRITE(reg, val);
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}
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static void skl_display_core_init(struct drm_i915_private *dev_priv,
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@ -3262,7 +3273,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
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gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
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/* enable PCH reset handshake */
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intel_pch_reset_handshake(dev_priv, true);
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intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
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/* enable PG1 and Misc I/O */
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mutex_lock(&power_domains->lock);
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@ -3448,7 +3459,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
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gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
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/* 1. Enable PCH Reset Handshake */
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intel_pch_reset_handshake(dev_priv, true);
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intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
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/* 2. Enable Comp */
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val = I915_READ(CHICKEN_MISC_2);
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@ -3531,7 +3542,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
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gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
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/* 1. Enable PCH reset handshake. */
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intel_pch_reset_handshake(dev_priv, true);
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intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
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for (port = PORT_A; port <= PORT_B; port++) {
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/* 2. Enable DDI combo PHY comp. */
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@ -3763,7 +3774,8 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
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mutex_lock(&power_domains->lock);
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vlv_cmnlane_wa(dev_priv);
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mutex_unlock(&power_domains->lock);
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}
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} else if (IS_IVYBRIDGE(dev_priv) || INTEL_GEN(dev_priv) >= 7)
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intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
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/*
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* Keep all power wells enabled for any dependent HW access during
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