mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-05 10:29:37 +00:00
Merge branch 'drm-fixes-4.10' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
Fixes for 4.10: - Polaris 12 support - Add new amd-gfx mailing list to MAINTAINERS file - UVD clockgating fix - SI dpm fixes * 'drm-fixes-4.10' of git://people.freedesktop.org/~agd5f/linux: drm/amdgpu: drop verde dpm quirks drm/radeon: drop verde dpm quirks drm/radeon: update smc firmware selection for SI drm/amdgpu: update si kicker smc firmware drm/amd/powerplay: extend smu's response timeout time. drm/amdgpu: remove static integer for uvd pp state drm/amd/amdgpu: add Polaris12 PCI ID drm/amdgpu/powerplay: add Polaris12 support drm/amd/amdgpu: add Polaris12 support (v3) MAINTAINERS: Update mailing list for radeon and amdgpu
This commit is contained in:
commit
6edd870bca
21 changed files with 146 additions and 106 deletions
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@ -4117,7 +4117,7 @@ F: drivers/gpu/drm/cirrus/
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RADEON and AMDGPU DRM DRIVERS
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RADEON and AMDGPU DRM DRIVERS
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M: Alex Deucher <alexander.deucher@amd.com>
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M: Alex Deucher <alexander.deucher@amd.com>
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M: Christian König <christian.koenig@amd.com>
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M: Christian König <christian.koenig@amd.com>
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L: dri-devel@lists.freedesktop.org
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L: amd-gfx@lists.freedesktop.org
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T: git git://people.freedesktop.org/~agd5f/linux
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T: git git://people.freedesktop.org/~agd5f/linux
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S: Supported
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S: Supported
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F: drivers/gpu/drm/radeon/
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F: drivers/gpu/drm/radeon/
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|
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@ -840,6 +840,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
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else if (type == CGS_UCODE_ID_SMU_SK)
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else if (type == CGS_UCODE_ID_SMU_SK)
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strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
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strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
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break;
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break;
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case CHIP_POLARIS12:
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strcpy(fw_name, "amdgpu/polaris12_smc.bin");
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break;
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default:
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default:
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DRM_ERROR("SMC firmware not supported\n");
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DRM_ERROR("SMC firmware not supported\n");
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return -EINVAL;
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return -EINVAL;
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@ -73,6 +73,7 @@ static const char *amdgpu_asic_name[] = {
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"STONEY",
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"STONEY",
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"POLARIS10",
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"POLARIS10",
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"POLARIS11",
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"POLARIS11",
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"POLARIS12",
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"LAST",
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"LAST",
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};
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};
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@ -1277,6 +1278,7 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
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case CHIP_FIJI:
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case CHIP_FIJI:
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case CHIP_POLARIS11:
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case CHIP_POLARIS11:
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case CHIP_POLARIS10:
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case CHIP_POLARIS10:
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case CHIP_POLARIS12:
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case CHIP_CARRIZO:
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case CHIP_CARRIZO:
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case CHIP_STONEY:
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case CHIP_STONEY:
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if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
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if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
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@ -418,6 +418,13 @@ static const struct pci_device_id pciidlist[] = {
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{0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
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{0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
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{0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
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{0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
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{0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
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{0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
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/* Polaris12 */
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{0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
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{0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
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{0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
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{0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
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{0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
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{0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
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{0, 0, 0}
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{0, 0, 0}
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};
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};
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@ -98,6 +98,7 @@ static int amdgpu_pp_early_init(void *handle)
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switch (adev->asic_type) {
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switch (adev->asic_type) {
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case CHIP_POLARIS11:
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case CHIP_POLARIS11:
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case CHIP_POLARIS10:
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case CHIP_POLARIS10:
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case CHIP_POLARIS12:
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case CHIP_TONGA:
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case CHIP_TONGA:
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case CHIP_FIJI:
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case CHIP_FIJI:
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case CHIP_TOPAZ:
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case CHIP_TOPAZ:
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|
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@ -65,6 +65,7 @@
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#define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin"
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#define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin"
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#define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin"
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#define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin"
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#define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin"
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#define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin"
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#define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin"
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/**
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/**
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* amdgpu_uvd_cs_ctx - Command submission parser context
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* amdgpu_uvd_cs_ctx - Command submission parser context
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@ -98,6 +99,7 @@ MODULE_FIRMWARE(FIRMWARE_FIJI);
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MODULE_FIRMWARE(FIRMWARE_STONEY);
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MODULE_FIRMWARE(FIRMWARE_STONEY);
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MODULE_FIRMWARE(FIRMWARE_POLARIS10);
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MODULE_FIRMWARE(FIRMWARE_POLARIS10);
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MODULE_FIRMWARE(FIRMWARE_POLARIS11);
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MODULE_FIRMWARE(FIRMWARE_POLARIS11);
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MODULE_FIRMWARE(FIRMWARE_POLARIS12);
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static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
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static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
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@ -149,6 +151,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
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case CHIP_POLARIS11:
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case CHIP_POLARIS11:
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fw_name = FIRMWARE_POLARIS11;
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fw_name = FIRMWARE_POLARIS11;
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break;
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break;
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case CHIP_POLARIS12:
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fw_name = FIRMWARE_POLARIS12;
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break;
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default:
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default:
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return -EINVAL;
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return -EINVAL;
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}
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}
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|
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@ -52,6 +52,7 @@
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#define FIRMWARE_STONEY "amdgpu/stoney_vce.bin"
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#define FIRMWARE_STONEY "amdgpu/stoney_vce.bin"
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#define FIRMWARE_POLARIS10 "amdgpu/polaris10_vce.bin"
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#define FIRMWARE_POLARIS10 "amdgpu/polaris10_vce.bin"
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#define FIRMWARE_POLARIS11 "amdgpu/polaris11_vce.bin"
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#define FIRMWARE_POLARIS11 "amdgpu/polaris11_vce.bin"
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#define FIRMWARE_POLARIS12 "amdgpu/polaris12_vce.bin"
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#ifdef CONFIG_DRM_AMDGPU_CIK
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#ifdef CONFIG_DRM_AMDGPU_CIK
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MODULE_FIRMWARE(FIRMWARE_BONAIRE);
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MODULE_FIRMWARE(FIRMWARE_BONAIRE);
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@ -66,6 +67,7 @@ MODULE_FIRMWARE(FIRMWARE_FIJI);
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MODULE_FIRMWARE(FIRMWARE_STONEY);
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MODULE_FIRMWARE(FIRMWARE_STONEY);
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MODULE_FIRMWARE(FIRMWARE_POLARIS10);
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MODULE_FIRMWARE(FIRMWARE_POLARIS10);
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MODULE_FIRMWARE(FIRMWARE_POLARIS11);
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MODULE_FIRMWARE(FIRMWARE_POLARIS11);
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MODULE_FIRMWARE(FIRMWARE_POLARIS12);
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|
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static void amdgpu_vce_idle_work_handler(struct work_struct *work);
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static void amdgpu_vce_idle_work_handler(struct work_struct *work);
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|
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@ -121,6 +123,9 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
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case CHIP_POLARIS11:
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case CHIP_POLARIS11:
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fw_name = FIRMWARE_POLARIS11;
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fw_name = FIRMWARE_POLARIS11;
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break;
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break;
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case CHIP_POLARIS12:
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fw_name = FIRMWARE_POLARIS12;
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break;
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|
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default:
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default:
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return -EINVAL;
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return -EINVAL;
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||||||
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|
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@ -167,6 +167,7 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
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(const u32)ARRAY_SIZE(stoney_golden_settings_a11));
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(const u32)ARRAY_SIZE(stoney_golden_settings_a11));
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break;
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break;
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case CHIP_POLARIS11:
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case CHIP_POLARIS11:
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case CHIP_POLARIS12:
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amdgpu_program_register_sequence(adev,
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amdgpu_program_register_sequence(adev,
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polaris11_golden_settings_a11,
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polaris11_golden_settings_a11,
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(const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
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(const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
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@ -608,6 +609,7 @@ static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
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num_crtc = 6;
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num_crtc = 6;
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break;
|
break;
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case CHIP_POLARIS11:
|
case CHIP_POLARIS11:
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case CHIP_POLARIS12:
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num_crtc = 5;
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num_crtc = 5;
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break;
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break;
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default:
|
default:
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@ -1589,6 +1591,7 @@ static int dce_v11_0_audio_init(struct amdgpu_device *adev)
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adev->mode_info.audio.num_pins = 8;
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adev->mode_info.audio.num_pins = 8;
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break;
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break;
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case CHIP_POLARIS11:
|
case CHIP_POLARIS11:
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case CHIP_POLARIS12:
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adev->mode_info.audio.num_pins = 6;
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adev->mode_info.audio.num_pins = 6;
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break;
|
break;
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default:
|
default:
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||||||
|
@ -2388,7 +2391,8 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
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int pll;
|
int pll;
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|
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||||||
if ((adev->asic_type == CHIP_POLARIS10) ||
|
if ((adev->asic_type == CHIP_POLARIS10) ||
|
||||||
(adev->asic_type == CHIP_POLARIS11)) {
|
(adev->asic_type == CHIP_POLARIS11) ||
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|
(adev->asic_type == CHIP_POLARIS12)) {
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struct amdgpu_encoder *amdgpu_encoder =
|
struct amdgpu_encoder *amdgpu_encoder =
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to_amdgpu_encoder(amdgpu_crtc->encoder);
|
to_amdgpu_encoder(amdgpu_crtc->encoder);
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struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
|
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
|
||||||
|
@ -2822,7 +2826,8 @@ static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
if ((adev->asic_type == CHIP_POLARIS10) ||
|
if ((adev->asic_type == CHIP_POLARIS10) ||
|
||||||
(adev->asic_type == CHIP_POLARIS11)) {
|
(adev->asic_type == CHIP_POLARIS11) ||
|
||||||
|
(adev->asic_type == CHIP_POLARIS12)) {
|
||||||
struct amdgpu_encoder *amdgpu_encoder =
|
struct amdgpu_encoder *amdgpu_encoder =
|
||||||
to_amdgpu_encoder(amdgpu_crtc->encoder);
|
to_amdgpu_encoder(amdgpu_crtc->encoder);
|
||||||
int encoder_mode =
|
int encoder_mode =
|
||||||
|
@ -2992,6 +2997,7 @@ static int dce_v11_0_early_init(void *handle)
|
||||||
adev->mode_info.num_dig = 6;
|
adev->mode_info.num_dig = 6;
|
||||||
break;
|
break;
|
||||||
case CHIP_POLARIS11:
|
case CHIP_POLARIS11:
|
||||||
|
case CHIP_POLARIS12:
|
||||||
adev->mode_info.num_hpd = 5;
|
adev->mode_info.num_hpd = 5;
|
||||||
adev->mode_info.num_dig = 5;
|
adev->mode_info.num_dig = 5;
|
||||||
break;
|
break;
|
||||||
|
@ -3101,7 +3107,8 @@ static int dce_v11_0_hw_init(void *handle)
|
||||||
amdgpu_atombios_crtc_powergate_init(adev);
|
amdgpu_atombios_crtc_powergate_init(adev);
|
||||||
amdgpu_atombios_encoder_init_dig(adev);
|
amdgpu_atombios_encoder_init_dig(adev);
|
||||||
if ((adev->asic_type == CHIP_POLARIS10) ||
|
if ((adev->asic_type == CHIP_POLARIS10) ||
|
||||||
(adev->asic_type == CHIP_POLARIS11)) {
|
(adev->asic_type == CHIP_POLARIS11) ||
|
||||||
|
(adev->asic_type == CHIP_POLARIS12)) {
|
||||||
amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
|
amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
|
||||||
DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
|
DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
|
||||||
amdgpu_atombios_crtc_set_dce_clock(adev, 0,
|
amdgpu_atombios_crtc_set_dce_clock(adev, 0,
|
||||||
|
|
|
@ -139,6 +139,13 @@ MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
|
||||||
MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
|
MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
|
||||||
MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
|
MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
|
||||||
|
|
||||||
|
MODULE_FIRMWARE("amdgpu/polaris12_ce.bin");
|
||||||
|
MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin");
|
||||||
|
MODULE_FIRMWARE("amdgpu/polaris12_me.bin");
|
||||||
|
MODULE_FIRMWARE("amdgpu/polaris12_mec.bin");
|
||||||
|
MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin");
|
||||||
|
MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin");
|
||||||
|
|
||||||
static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
|
static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
|
||||||
{
|
{
|
||||||
{mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
|
{mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
|
||||||
|
@ -689,6 +696,7 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
|
||||||
(const u32)ARRAY_SIZE(tonga_golden_common_all));
|
(const u32)ARRAY_SIZE(tonga_golden_common_all));
|
||||||
break;
|
break;
|
||||||
case CHIP_POLARIS11:
|
case CHIP_POLARIS11:
|
||||||
|
case CHIP_POLARIS12:
|
||||||
amdgpu_program_register_sequence(adev,
|
amdgpu_program_register_sequence(adev,
|
||||||
golden_settings_polaris11_a11,
|
golden_settings_polaris11_a11,
|
||||||
(const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
|
(const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
|
||||||
|
@ -903,6 +911,9 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
|
||||||
case CHIP_POLARIS10:
|
case CHIP_POLARIS10:
|
||||||
chip_name = "polaris10";
|
chip_name = "polaris10";
|
||||||
break;
|
break;
|
||||||
|
case CHIP_POLARIS12:
|
||||||
|
chip_name = "polaris12";
|
||||||
|
break;
|
||||||
case CHIP_STONEY:
|
case CHIP_STONEY:
|
||||||
chip_name = "stoney";
|
chip_name = "stoney";
|
||||||
break;
|
break;
|
||||||
|
@ -1768,6 +1779,7 @@ static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
|
||||||
gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
|
gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
|
||||||
break;
|
break;
|
||||||
case CHIP_POLARIS11:
|
case CHIP_POLARIS11:
|
||||||
|
case CHIP_POLARIS12:
|
||||||
ret = amdgpu_atombios_get_gfx_info(adev);
|
ret = amdgpu_atombios_get_gfx_info(adev);
|
||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
|
@ -2682,6 +2694,7 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
|
||||||
|
|
||||||
break;
|
break;
|
||||||
case CHIP_POLARIS11:
|
case CHIP_POLARIS11:
|
||||||
|
case CHIP_POLARIS12:
|
||||||
modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
|
modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
|
||||||
PIPE_CONFIG(ADDR_SURF_P4_16x16) |
|
PIPE_CONFIG(ADDR_SURF_P4_16x16) |
|
||||||
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
|
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
|
||||||
|
@ -3503,6 +3516,7 @@ gfx_v8_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
|
||||||
*rconf1 |= 0x0;
|
*rconf1 |= 0x0;
|
||||||
break;
|
break;
|
||||||
case CHIP_POLARIS11:
|
case CHIP_POLARIS11:
|
||||||
|
case CHIP_POLARIS12:
|
||||||
*rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
|
*rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
|
||||||
SE_XSEL(1) | SE_YSEL(1);
|
SE_XSEL(1) | SE_YSEL(1);
|
||||||
*rconf1 |= 0x0;
|
*rconf1 |= 0x0;
|
||||||
|
@ -4021,7 +4035,8 @@ static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
|
||||||
cz_enable_cp_power_gating(adev, true);
|
cz_enable_cp_power_gating(adev, true);
|
||||||
else
|
else
|
||||||
cz_enable_cp_power_gating(adev, false);
|
cz_enable_cp_power_gating(adev, false);
|
||||||
} else if (adev->asic_type == CHIP_POLARIS11) {
|
} else if ((adev->asic_type == CHIP_POLARIS11) ||
|
||||||
|
(adev->asic_type == CHIP_POLARIS12)) {
|
||||||
gfx_v8_0_init_csb(adev);
|
gfx_v8_0_init_csb(adev);
|
||||||
gfx_v8_0_init_save_restore_list(adev);
|
gfx_v8_0_init_save_restore_list(adev);
|
||||||
gfx_v8_0_enable_save_restore_machine(adev);
|
gfx_v8_0_enable_save_restore_machine(adev);
|
||||||
|
@ -4095,7 +4110,8 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
|
||||||
RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
|
RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
|
||||||
WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
|
WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
|
||||||
if (adev->asic_type == CHIP_POLARIS11 ||
|
if (adev->asic_type == CHIP_POLARIS11 ||
|
||||||
adev->asic_type == CHIP_POLARIS10) {
|
adev->asic_type == CHIP_POLARIS10 ||
|
||||||
|
adev->asic_type == CHIP_POLARIS12) {
|
||||||
tmp = RREG32(mmRLC_CGCG_CGLS_CTRL_3D);
|
tmp = RREG32(mmRLC_CGCG_CGLS_CTRL_3D);
|
||||||
tmp &= ~0x3;
|
tmp &= ~0x3;
|
||||||
WREG32(mmRLC_CGCG_CGLS_CTRL_3D, tmp);
|
WREG32(mmRLC_CGCG_CGLS_CTRL_3D, tmp);
|
||||||
|
@ -4283,6 +4299,7 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
|
||||||
amdgpu_ring_write(ring, 0x0000002A);
|
amdgpu_ring_write(ring, 0x0000002A);
|
||||||
break;
|
break;
|
||||||
case CHIP_POLARIS11:
|
case CHIP_POLARIS11:
|
||||||
|
case CHIP_POLARIS12:
|
||||||
amdgpu_ring_write(ring, 0x16000012);
|
amdgpu_ring_write(ring, 0x16000012);
|
||||||
amdgpu_ring_write(ring, 0x00000000);
|
amdgpu_ring_write(ring, 0x00000000);
|
||||||
break;
|
break;
|
||||||
|
@ -4664,7 +4681,8 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
|
||||||
(adev->asic_type == CHIP_FIJI) ||
|
(adev->asic_type == CHIP_FIJI) ||
|
||||||
(adev->asic_type == CHIP_STONEY) ||
|
(adev->asic_type == CHIP_STONEY) ||
|
||||||
(adev->asic_type == CHIP_POLARIS11) ||
|
(adev->asic_type == CHIP_POLARIS11) ||
|
||||||
(adev->asic_type == CHIP_POLARIS10)) {
|
(adev->asic_type == CHIP_POLARIS10) ||
|
||||||
|
(adev->asic_type == CHIP_POLARIS12)) {
|
||||||
WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
|
WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
|
||||||
AMDGPU_DOORBELL_KIQ << 2);
|
AMDGPU_DOORBELL_KIQ << 2);
|
||||||
WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
|
WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
|
||||||
|
@ -4700,7 +4718,8 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
|
||||||
mqd->cp_hqd_persistent_state = tmp;
|
mqd->cp_hqd_persistent_state = tmp;
|
||||||
if (adev->asic_type == CHIP_STONEY ||
|
if (adev->asic_type == CHIP_STONEY ||
|
||||||
adev->asic_type == CHIP_POLARIS11 ||
|
adev->asic_type == CHIP_POLARIS11 ||
|
||||||
adev->asic_type == CHIP_POLARIS10) {
|
adev->asic_type == CHIP_POLARIS10 ||
|
||||||
|
adev->asic_type == CHIP_POLARIS12) {
|
||||||
tmp = RREG32(mmCP_ME1_PIPE3_INT_CNTL);
|
tmp = RREG32(mmCP_ME1_PIPE3_INT_CNTL);
|
||||||
tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE3_INT_CNTL, GENERIC2_INT_ENABLE, 1);
|
tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE3_INT_CNTL, GENERIC2_INT_ENABLE, 1);
|
||||||
WREG32(mmCP_ME1_PIPE3_INT_CNTL, tmp);
|
WREG32(mmCP_ME1_PIPE3_INT_CNTL, tmp);
|
||||||
|
@ -5279,7 +5298,8 @@ static int gfx_v8_0_late_init(void *handle)
|
||||||
static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
|
static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
|
||||||
bool enable)
|
bool enable)
|
||||||
{
|
{
|
||||||
if (adev->asic_type == CHIP_POLARIS11)
|
if ((adev->asic_type == CHIP_POLARIS11) ||
|
||||||
|
(adev->asic_type == CHIP_POLARIS12))
|
||||||
/* Send msg to SMU via Powerplay */
|
/* Send msg to SMU via Powerplay */
|
||||||
amdgpu_set_powergating_state(adev,
|
amdgpu_set_powergating_state(adev,
|
||||||
AMD_IP_BLOCK_TYPE_SMC,
|
AMD_IP_BLOCK_TYPE_SMC,
|
||||||
|
@ -5353,6 +5373,7 @@ static int gfx_v8_0_set_powergating_state(void *handle,
|
||||||
gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
|
gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
|
||||||
break;
|
break;
|
||||||
case CHIP_POLARIS11:
|
case CHIP_POLARIS11:
|
||||||
|
case CHIP_POLARIS12:
|
||||||
if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
|
if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
|
||||||
gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
|
gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
|
||||||
else
|
else
|
||||||
|
|
|
@ -46,6 +46,7 @@ static int gmc_v8_0_wait_for_idle(void *handle);
|
||||||
MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
|
MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
|
||||||
MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
|
MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
|
||||||
MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
|
MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
|
||||||
|
MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
|
||||||
|
|
||||||
static const u32 golden_settings_tonga_a11[] =
|
static const u32 golden_settings_tonga_a11[] =
|
||||||
{
|
{
|
||||||
|
@ -130,6 +131,7 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
|
||||||
(const u32)ARRAY_SIZE(golden_settings_tonga_a11));
|
(const u32)ARRAY_SIZE(golden_settings_tonga_a11));
|
||||||
break;
|
break;
|
||||||
case CHIP_POLARIS11:
|
case CHIP_POLARIS11:
|
||||||
|
case CHIP_POLARIS12:
|
||||||
amdgpu_program_register_sequence(adev,
|
amdgpu_program_register_sequence(adev,
|
||||||
golden_settings_polaris11_a11,
|
golden_settings_polaris11_a11,
|
||||||
(const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
|
(const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
|
||||||
|
@ -225,6 +227,9 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
|
||||||
case CHIP_POLARIS10:
|
case CHIP_POLARIS10:
|
||||||
chip_name = "polaris10";
|
chip_name = "polaris10";
|
||||||
break;
|
break;
|
||||||
|
case CHIP_POLARIS12:
|
||||||
|
chip_name = "polaris12";
|
||||||
|
break;
|
||||||
case CHIP_FIJI:
|
case CHIP_FIJI:
|
||||||
case CHIP_CARRIZO:
|
case CHIP_CARRIZO:
|
||||||
case CHIP_STONEY:
|
case CHIP_STONEY:
|
||||||
|
|
|
@ -60,6 +60,8 @@ MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
|
||||||
MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
|
MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
|
||||||
MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
|
MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
|
||||||
MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
|
MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
|
||||||
|
MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin");
|
||||||
|
MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin");
|
||||||
|
|
||||||
|
|
||||||
static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
|
static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
|
||||||
|
@ -206,6 +208,7 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
|
||||||
(const u32)ARRAY_SIZE(golden_settings_tonga_a11));
|
(const u32)ARRAY_SIZE(golden_settings_tonga_a11));
|
||||||
break;
|
break;
|
||||||
case CHIP_POLARIS11:
|
case CHIP_POLARIS11:
|
||||||
|
case CHIP_POLARIS12:
|
||||||
amdgpu_program_register_sequence(adev,
|
amdgpu_program_register_sequence(adev,
|
||||||
golden_settings_polaris11_a11,
|
golden_settings_polaris11_a11,
|
||||||
(const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
|
(const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
|
||||||
|
@ -278,6 +281,9 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
|
||||||
case CHIP_POLARIS10:
|
case CHIP_POLARIS10:
|
||||||
chip_name = "polaris10";
|
chip_name = "polaris10";
|
||||||
break;
|
break;
|
||||||
|
case CHIP_POLARIS12:
|
||||||
|
chip_name = "polaris12";
|
||||||
|
break;
|
||||||
case CHIP_CARRIZO:
|
case CHIP_CARRIZO:
|
||||||
chip_name = "carrizo";
|
chip_name = "carrizo";
|
||||||
break;
|
break;
|
||||||
|
|
|
@ -56,7 +56,6 @@
|
||||||
#define BIOS_SCRATCH_4 0x5cd
|
#define BIOS_SCRATCH_4 0x5cd
|
||||||
|
|
||||||
MODULE_FIRMWARE("radeon/tahiti_smc.bin");
|
MODULE_FIRMWARE("radeon/tahiti_smc.bin");
|
||||||
MODULE_FIRMWARE("radeon/tahiti_k_smc.bin");
|
|
||||||
MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
|
MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
|
||||||
MODULE_FIRMWARE("radeon/pitcairn_k_smc.bin");
|
MODULE_FIRMWARE("radeon/pitcairn_k_smc.bin");
|
||||||
MODULE_FIRMWARE("radeon/verde_smc.bin");
|
MODULE_FIRMWARE("radeon/verde_smc.bin");
|
||||||
|
@ -3488,19 +3487,6 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
|
||||||
(adev->pdev->device == 0x6817) ||
|
(adev->pdev->device == 0x6817) ||
|
||||||
(adev->pdev->device == 0x6806))
|
(adev->pdev->device == 0x6806))
|
||||||
max_mclk = 120000;
|
max_mclk = 120000;
|
||||||
} else if (adev->asic_type == CHIP_VERDE) {
|
|
||||||
if ((adev->pdev->revision == 0x81) ||
|
|
||||||
(adev->pdev->revision == 0x83) ||
|
|
||||||
(adev->pdev->revision == 0x87) ||
|
|
||||||
(adev->pdev->device == 0x6820) ||
|
|
||||||
(adev->pdev->device == 0x6821) ||
|
|
||||||
(adev->pdev->device == 0x6822) ||
|
|
||||||
(adev->pdev->device == 0x6823) ||
|
|
||||||
(adev->pdev->device == 0x682A) ||
|
|
||||||
(adev->pdev->device == 0x682B)) {
|
|
||||||
max_sclk = 75000;
|
|
||||||
max_mclk = 80000;
|
|
||||||
}
|
|
||||||
} else if (adev->asic_type == CHIP_OLAND) {
|
} else if (adev->asic_type == CHIP_OLAND) {
|
||||||
if ((adev->pdev->revision == 0xC7) ||
|
if ((adev->pdev->revision == 0xC7) ||
|
||||||
(adev->pdev->revision == 0x80) ||
|
(adev->pdev->revision == 0x80) ||
|
||||||
|
@ -7687,49 +7673,49 @@ static int si_dpm_init_microcode(struct amdgpu_device *adev)
|
||||||
chip_name = "tahiti";
|
chip_name = "tahiti";
|
||||||
break;
|
break;
|
||||||
case CHIP_PITCAIRN:
|
case CHIP_PITCAIRN:
|
||||||
if ((adev->pdev->revision == 0x81) ||
|
if ((adev->pdev->revision == 0x81) &&
|
||||||
(adev->pdev->device == 0x6810) ||
|
((adev->pdev->device == 0x6810) ||
|
||||||
(adev->pdev->device == 0x6811) ||
|
(adev->pdev->device == 0x6811)))
|
||||||
(adev->pdev->device == 0x6816) ||
|
|
||||||
(adev->pdev->device == 0x6817) ||
|
|
||||||
(adev->pdev->device == 0x6806))
|
|
||||||
chip_name = "pitcairn_k";
|
chip_name = "pitcairn_k";
|
||||||
else
|
else
|
||||||
chip_name = "pitcairn";
|
chip_name = "pitcairn";
|
||||||
break;
|
break;
|
||||||
case CHIP_VERDE:
|
case CHIP_VERDE:
|
||||||
if ((adev->pdev->revision == 0x81) ||
|
if (((adev->pdev->device == 0x6820) &&
|
||||||
(adev->pdev->revision == 0x83) ||
|
((adev->pdev->revision == 0x81) ||
|
||||||
(adev->pdev->revision == 0x87) ||
|
(adev->pdev->revision == 0x83))) ||
|
||||||
(adev->pdev->device == 0x6820) ||
|
((adev->pdev->device == 0x6821) &&
|
||||||
(adev->pdev->device == 0x6821) ||
|
((adev->pdev->revision == 0x83) ||
|
||||||
(adev->pdev->device == 0x6822) ||
|
(adev->pdev->revision == 0x87))) ||
|
||||||
(adev->pdev->device == 0x6823) ||
|
((adev->pdev->revision == 0x87) &&
|
||||||
(adev->pdev->device == 0x682A) ||
|
((adev->pdev->device == 0x6823) ||
|
||||||
(adev->pdev->device == 0x682B))
|
(adev->pdev->device == 0x682b))))
|
||||||
chip_name = "verde_k";
|
chip_name = "verde_k";
|
||||||
else
|
else
|
||||||
chip_name = "verde";
|
chip_name = "verde";
|
||||||
break;
|
break;
|
||||||
case CHIP_OLAND:
|
case CHIP_OLAND:
|
||||||
if ((adev->pdev->revision == 0xC7) ||
|
if (((adev->pdev->revision == 0x81) &&
|
||||||
(adev->pdev->revision == 0x80) ||
|
((adev->pdev->device == 0x6600) ||
|
||||||
(adev->pdev->revision == 0x81) ||
|
(adev->pdev->device == 0x6604) ||
|
||||||
(adev->pdev->revision == 0x83) ||
|
(adev->pdev->device == 0x6605) ||
|
||||||
(adev->pdev->revision == 0x87) ||
|
(adev->pdev->device == 0x6610))) ||
|
||||||
(adev->pdev->device == 0x6604) ||
|
((adev->pdev->revision == 0x83) &&
|
||||||
(adev->pdev->device == 0x6605))
|
(adev->pdev->device == 0x6610)))
|
||||||
chip_name = "oland_k";
|
chip_name = "oland_k";
|
||||||
else
|
else
|
||||||
chip_name = "oland";
|
chip_name = "oland";
|
||||||
break;
|
break;
|
||||||
case CHIP_HAINAN:
|
case CHIP_HAINAN:
|
||||||
if ((adev->pdev->revision == 0x81) ||
|
if (((adev->pdev->revision == 0x81) &&
|
||||||
(adev->pdev->revision == 0x83) ||
|
(adev->pdev->device == 0x6660)) ||
|
||||||
(adev->pdev->revision == 0xC3) ||
|
((adev->pdev->revision == 0x83) &&
|
||||||
(adev->pdev->device == 0x6664) ||
|
((adev->pdev->device == 0x6660) ||
|
||||||
(adev->pdev->device == 0x6665) ||
|
(adev->pdev->device == 0x6663) ||
|
||||||
(adev->pdev->device == 0x6667))
|
(adev->pdev->device == 0x6665) ||
|
||||||
|
(adev->pdev->device == 0x6667))) ||
|
||||||
|
((adev->pdev->revision == 0xc3) &&
|
||||||
|
(adev->pdev->device == 0x6665)))
|
||||||
chip_name = "hainan_k";
|
chip_name = "hainan_k";
|
||||||
else
|
else
|
||||||
chip_name = "hainan";
|
chip_name = "hainan";
|
||||||
|
|
|
@ -791,15 +791,10 @@ static int uvd_v5_0_set_clockgating_state(void *handle,
|
||||||
{
|
{
|
||||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||||
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
|
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
|
||||||
static int curstate = -1;
|
|
||||||
|
|
||||||
if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
|
if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
if (curstate == state)
|
|
||||||
return 0;
|
|
||||||
|
|
||||||
curstate = state;
|
|
||||||
if (enable) {
|
if (enable) {
|
||||||
/* wait for STATUS to clear */
|
/* wait for STATUS to clear */
|
||||||
if (uvd_v5_0_wait_for_idle(handle))
|
if (uvd_v5_0_wait_for_idle(handle))
|
||||||
|
|
|
@ -320,11 +320,12 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
|
||||||
{
|
{
|
||||||
u32 tmp;
|
u32 tmp;
|
||||||
|
|
||||||
/* Fiji, Stoney, Polaris10, Polaris11 are single pipe */
|
/* Fiji, Stoney, Polaris10, Polaris11, Polaris12 are single pipe */
|
||||||
if ((adev->asic_type == CHIP_FIJI) ||
|
if ((adev->asic_type == CHIP_FIJI) ||
|
||||||
(adev->asic_type == CHIP_STONEY) ||
|
(adev->asic_type == CHIP_STONEY) ||
|
||||||
(adev->asic_type == CHIP_POLARIS10) ||
|
(adev->asic_type == CHIP_POLARIS10) ||
|
||||||
(adev->asic_type == CHIP_POLARIS11))
|
(adev->asic_type == CHIP_POLARIS11) ||
|
||||||
|
(adev->asic_type == CHIP_POLARIS12))
|
||||||
return AMDGPU_VCE_HARVEST_VCE1;
|
return AMDGPU_VCE_HARVEST_VCE1;
|
||||||
|
|
||||||
/* Tonga and CZ are dual or single pipe */
|
/* Tonga and CZ are dual or single pipe */
|
||||||
|
|
|
@ -88,6 +88,7 @@ MODULE_FIRMWARE("amdgpu/polaris10_smc.bin");
|
||||||
MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin");
|
MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin");
|
||||||
MODULE_FIRMWARE("amdgpu/polaris11_smc.bin");
|
MODULE_FIRMWARE("amdgpu/polaris11_smc.bin");
|
||||||
MODULE_FIRMWARE("amdgpu/polaris11_smc_sk.bin");
|
MODULE_FIRMWARE("amdgpu/polaris11_smc_sk.bin");
|
||||||
|
MODULE_FIRMWARE("amdgpu/polaris12_smc.bin");
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Indirect registers accessor
|
* Indirect registers accessor
|
||||||
|
@ -312,6 +313,7 @@ static void vi_init_golden_registers(struct amdgpu_device *adev)
|
||||||
break;
|
break;
|
||||||
case CHIP_POLARIS11:
|
case CHIP_POLARIS11:
|
||||||
case CHIP_POLARIS10:
|
case CHIP_POLARIS10:
|
||||||
|
case CHIP_POLARIS12:
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -671,6 +673,7 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
|
||||||
case CHIP_TONGA:
|
case CHIP_TONGA:
|
||||||
case CHIP_POLARIS11:
|
case CHIP_POLARIS11:
|
||||||
case CHIP_POLARIS10:
|
case CHIP_POLARIS10:
|
||||||
|
case CHIP_POLARIS12:
|
||||||
case CHIP_CARRIZO:
|
case CHIP_CARRIZO:
|
||||||
case CHIP_STONEY:
|
case CHIP_STONEY:
|
||||||
asic_register_table = cz_allowed_read_registers;
|
asic_register_table = cz_allowed_read_registers;
|
||||||
|
@ -994,6 +997,11 @@ static int vi_common_early_init(void *handle)
|
||||||
adev->pg_flags = 0;
|
adev->pg_flags = 0;
|
||||||
adev->external_rev_id = adev->rev_id + 0x50;
|
adev->external_rev_id = adev->rev_id + 0x50;
|
||||||
break;
|
break;
|
||||||
|
case CHIP_POLARIS12:
|
||||||
|
adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
|
||||||
|
adev->pg_flags = 0;
|
||||||
|
adev->external_rev_id = adev->rev_id + 0x64;
|
||||||
|
break;
|
||||||
case CHIP_CARRIZO:
|
case CHIP_CARRIZO:
|
||||||
adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
|
adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
|
||||||
AMD_CG_SUPPORT_GFX_MGCG |
|
AMD_CG_SUPPORT_GFX_MGCG |
|
||||||
|
@ -1346,6 +1354,7 @@ static int vi_common_set_clockgating_state(void *handle,
|
||||||
case CHIP_TONGA:
|
case CHIP_TONGA:
|
||||||
case CHIP_POLARIS10:
|
case CHIP_POLARIS10:
|
||||||
case CHIP_POLARIS11:
|
case CHIP_POLARIS11:
|
||||||
|
case CHIP_POLARIS12:
|
||||||
vi_common_set_clockgating_state_by_smu(adev, state);
|
vi_common_set_clockgating_state_by_smu(adev, state);
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
|
@ -1429,6 +1438,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
|
||||||
break;
|
break;
|
||||||
case CHIP_POLARIS11:
|
case CHIP_POLARIS11:
|
||||||
case CHIP_POLARIS10:
|
case CHIP_POLARIS10:
|
||||||
|
case CHIP_POLARIS12:
|
||||||
amdgpu_ip_block_add(adev, &vi_common_ip_block);
|
amdgpu_ip_block_add(adev, &vi_common_ip_block);
|
||||||
amdgpu_ip_block_add(adev, &gmc_v8_1_ip_block);
|
amdgpu_ip_block_add(adev, &gmc_v8_1_ip_block);
|
||||||
amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
|
amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
|
||||||
|
|
|
@ -23,7 +23,7 @@
|
||||||
#ifndef __AMD_SHARED_H__
|
#ifndef __AMD_SHARED_H__
|
||||||
#define __AMD_SHARED_H__
|
#define __AMD_SHARED_H__
|
||||||
|
|
||||||
#define AMD_MAX_USEC_TIMEOUT 100000 /* 100 ms */
|
#define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Supported ASIC types
|
* Supported ASIC types
|
||||||
|
@ -46,6 +46,7 @@ enum amd_asic_type {
|
||||||
CHIP_STONEY,
|
CHIP_STONEY,
|
||||||
CHIP_POLARIS10,
|
CHIP_POLARIS10,
|
||||||
CHIP_POLARIS11,
|
CHIP_POLARIS11,
|
||||||
|
CHIP_POLARIS12,
|
||||||
CHIP_LAST,
|
CHIP_LAST,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -95,6 +95,7 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
|
||||||
break;
|
break;
|
||||||
case CHIP_POLARIS11:
|
case CHIP_POLARIS11:
|
||||||
case CHIP_POLARIS10:
|
case CHIP_POLARIS10:
|
||||||
|
case CHIP_POLARIS12:
|
||||||
polaris_set_asic_special_caps(hwmgr);
|
polaris_set_asic_special_caps(hwmgr);
|
||||||
hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
|
hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
|
||||||
break;
|
break;
|
||||||
|
@ -745,7 +746,7 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
|
||||||
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
||||||
PHM_PlatformCaps_TablelessHardwareInterface);
|
PHM_PlatformCaps_TablelessHardwareInterface);
|
||||||
|
|
||||||
if (hwmgr->chip_id == CHIP_POLARIS11)
|
if ((hwmgr->chip_id == CHIP_POLARIS11) || (hwmgr->chip_id == CHIP_POLARIS12))
|
||||||
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
||||||
PHM_PlatformCaps_SPLLShutdownSupport);
|
PHM_PlatformCaps_SPLLShutdownSupport);
|
||||||
return 0;
|
return 0;
|
||||||
|
|
|
@ -521,7 +521,7 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
|
||||||
PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
|
PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
|
||||||
result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris10);
|
result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris10);
|
||||||
PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
|
PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
|
||||||
} else if (hwmgr->chip_id == CHIP_POLARIS11) {
|
} else if ((hwmgr->chip_id == CHIP_POLARIS11) || (hwmgr->chip_id == CHIP_POLARIS12)) {
|
||||||
result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
|
result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
|
||||||
PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
|
PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
|
||||||
result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11);
|
result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11);
|
||||||
|
|
|
@ -65,6 +65,7 @@ int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
|
||||||
break;
|
break;
|
||||||
case CHIP_POLARIS11:
|
case CHIP_POLARIS11:
|
||||||
case CHIP_POLARIS10:
|
case CHIP_POLARIS10:
|
||||||
|
case CHIP_POLARIS12:
|
||||||
polaris10_smum_init(smumgr);
|
polaris10_smum_init(smumgr);
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
|
|
|
@ -50,7 +50,6 @@ MODULE_FIRMWARE("radeon/tahiti_ce.bin");
|
||||||
MODULE_FIRMWARE("radeon/tahiti_mc.bin");
|
MODULE_FIRMWARE("radeon/tahiti_mc.bin");
|
||||||
MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
|
MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
|
||||||
MODULE_FIRMWARE("radeon/tahiti_smc.bin");
|
MODULE_FIRMWARE("radeon/tahiti_smc.bin");
|
||||||
MODULE_FIRMWARE("radeon/tahiti_k_smc.bin");
|
|
||||||
|
|
||||||
MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
|
MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
|
||||||
MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
|
MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
|
||||||
|
@ -1657,9 +1656,6 @@ static int si_init_microcode(struct radeon_device *rdev)
|
||||||
switch (rdev->family) {
|
switch (rdev->family) {
|
||||||
case CHIP_TAHITI:
|
case CHIP_TAHITI:
|
||||||
chip_name = "TAHITI";
|
chip_name = "TAHITI";
|
||||||
/* XXX: figure out which Tahitis need the new ucode */
|
|
||||||
if (0)
|
|
||||||
new_smc = true;
|
|
||||||
new_chip_name = "tahiti";
|
new_chip_name = "tahiti";
|
||||||
pfp_req_size = SI_PFP_UCODE_SIZE * 4;
|
pfp_req_size = SI_PFP_UCODE_SIZE * 4;
|
||||||
me_req_size = SI_PM4_UCODE_SIZE * 4;
|
me_req_size = SI_PM4_UCODE_SIZE * 4;
|
||||||
|
@ -1671,12 +1667,9 @@ static int si_init_microcode(struct radeon_device *rdev)
|
||||||
break;
|
break;
|
||||||
case CHIP_PITCAIRN:
|
case CHIP_PITCAIRN:
|
||||||
chip_name = "PITCAIRN";
|
chip_name = "PITCAIRN";
|
||||||
if ((rdev->pdev->revision == 0x81) ||
|
if ((rdev->pdev->revision == 0x81) &&
|
||||||
(rdev->pdev->device == 0x6810) ||
|
((rdev->pdev->device == 0x6810) ||
|
||||||
(rdev->pdev->device == 0x6811) ||
|
(rdev->pdev->device == 0x6811)))
|
||||||
(rdev->pdev->device == 0x6816) ||
|
|
||||||
(rdev->pdev->device == 0x6817) ||
|
|
||||||
(rdev->pdev->device == 0x6806))
|
|
||||||
new_smc = true;
|
new_smc = true;
|
||||||
new_chip_name = "pitcairn";
|
new_chip_name = "pitcairn";
|
||||||
pfp_req_size = SI_PFP_UCODE_SIZE * 4;
|
pfp_req_size = SI_PFP_UCODE_SIZE * 4;
|
||||||
|
@ -1689,15 +1682,15 @@ static int si_init_microcode(struct radeon_device *rdev)
|
||||||
break;
|
break;
|
||||||
case CHIP_VERDE:
|
case CHIP_VERDE:
|
||||||
chip_name = "VERDE";
|
chip_name = "VERDE";
|
||||||
if ((rdev->pdev->revision == 0x81) ||
|
if (((rdev->pdev->device == 0x6820) &&
|
||||||
(rdev->pdev->revision == 0x83) ||
|
((rdev->pdev->revision == 0x81) ||
|
||||||
(rdev->pdev->revision == 0x87) ||
|
(rdev->pdev->revision == 0x83))) ||
|
||||||
(rdev->pdev->device == 0x6820) ||
|
((rdev->pdev->device == 0x6821) &&
|
||||||
(rdev->pdev->device == 0x6821) ||
|
((rdev->pdev->revision == 0x83) ||
|
||||||
(rdev->pdev->device == 0x6822) ||
|
(rdev->pdev->revision == 0x87))) ||
|
||||||
(rdev->pdev->device == 0x6823) ||
|
((rdev->pdev->revision == 0x87) &&
|
||||||
(rdev->pdev->device == 0x682A) ||
|
((rdev->pdev->device == 0x6823) ||
|
||||||
(rdev->pdev->device == 0x682B))
|
(rdev->pdev->device == 0x682b))))
|
||||||
new_smc = true;
|
new_smc = true;
|
||||||
new_chip_name = "verde";
|
new_chip_name = "verde";
|
||||||
pfp_req_size = SI_PFP_UCODE_SIZE * 4;
|
pfp_req_size = SI_PFP_UCODE_SIZE * 4;
|
||||||
|
@ -1710,13 +1703,13 @@ static int si_init_microcode(struct radeon_device *rdev)
|
||||||
break;
|
break;
|
||||||
case CHIP_OLAND:
|
case CHIP_OLAND:
|
||||||
chip_name = "OLAND";
|
chip_name = "OLAND";
|
||||||
if ((rdev->pdev->revision == 0xC7) ||
|
if (((rdev->pdev->revision == 0x81) &&
|
||||||
(rdev->pdev->revision == 0x80) ||
|
((rdev->pdev->device == 0x6600) ||
|
||||||
(rdev->pdev->revision == 0x81) ||
|
(rdev->pdev->device == 0x6604) ||
|
||||||
(rdev->pdev->revision == 0x83) ||
|
(rdev->pdev->device == 0x6605) ||
|
||||||
(rdev->pdev->revision == 0x87) ||
|
(rdev->pdev->device == 0x6610))) ||
|
||||||
(rdev->pdev->device == 0x6604) ||
|
((rdev->pdev->revision == 0x83) &&
|
||||||
(rdev->pdev->device == 0x6605))
|
(rdev->pdev->device == 0x6610)))
|
||||||
new_smc = true;
|
new_smc = true;
|
||||||
new_chip_name = "oland";
|
new_chip_name = "oland";
|
||||||
pfp_req_size = SI_PFP_UCODE_SIZE * 4;
|
pfp_req_size = SI_PFP_UCODE_SIZE * 4;
|
||||||
|
@ -1728,12 +1721,15 @@ static int si_init_microcode(struct radeon_device *rdev)
|
||||||
break;
|
break;
|
||||||
case CHIP_HAINAN:
|
case CHIP_HAINAN:
|
||||||
chip_name = "HAINAN";
|
chip_name = "HAINAN";
|
||||||
if ((rdev->pdev->revision == 0x81) ||
|
if (((rdev->pdev->revision == 0x81) &&
|
||||||
(rdev->pdev->revision == 0x83) ||
|
(rdev->pdev->device == 0x6660)) ||
|
||||||
(rdev->pdev->revision == 0xC3) ||
|
((rdev->pdev->revision == 0x83) &&
|
||||||
(rdev->pdev->device == 0x6664) ||
|
((rdev->pdev->device == 0x6660) ||
|
||||||
(rdev->pdev->device == 0x6665) ||
|
(rdev->pdev->device == 0x6663) ||
|
||||||
(rdev->pdev->device == 0x6667))
|
(rdev->pdev->device == 0x6665) ||
|
||||||
|
(rdev->pdev->device == 0x6667))) ||
|
||||||
|
((rdev->pdev->revision == 0xc3) &&
|
||||||
|
(rdev->pdev->device == 0x6665)))
|
||||||
new_smc = true;
|
new_smc = true;
|
||||||
new_chip_name = "hainan";
|
new_chip_name = "hainan";
|
||||||
pfp_req_size = SI_PFP_UCODE_SIZE * 4;
|
pfp_req_size = SI_PFP_UCODE_SIZE * 4;
|
||||||
|
|
|
@ -3008,19 +3008,6 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
|
||||||
(rdev->pdev->device == 0x6817) ||
|
(rdev->pdev->device == 0x6817) ||
|
||||||
(rdev->pdev->device == 0x6806))
|
(rdev->pdev->device == 0x6806))
|
||||||
max_mclk = 120000;
|
max_mclk = 120000;
|
||||||
} else if (rdev->family == CHIP_VERDE) {
|
|
||||||
if ((rdev->pdev->revision == 0x81) ||
|
|
||||||
(rdev->pdev->revision == 0x83) ||
|
|
||||||
(rdev->pdev->revision == 0x87) ||
|
|
||||||
(rdev->pdev->device == 0x6820) ||
|
|
||||||
(rdev->pdev->device == 0x6821) ||
|
|
||||||
(rdev->pdev->device == 0x6822) ||
|
|
||||||
(rdev->pdev->device == 0x6823) ||
|
|
||||||
(rdev->pdev->device == 0x682A) ||
|
|
||||||
(rdev->pdev->device == 0x682B)) {
|
|
||||||
max_sclk = 75000;
|
|
||||||
max_mclk = 80000;
|
|
||||||
}
|
|
||||||
} else if (rdev->family == CHIP_OLAND) {
|
} else if (rdev->family == CHIP_OLAND) {
|
||||||
if ((rdev->pdev->revision == 0xC7) ||
|
if ((rdev->pdev->revision == 0xC7) ||
|
||||||
(rdev->pdev->revision == 0x80) ||
|
(rdev->pdev->revision == 0x80) ||
|
||||||
|
|
Loading…
Reference in a new issue