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drm/amd/pm: correct Arcturus mmTHM_BACO_CNTL register address
Arcturus has a different register address from other SMU V11 ASICs. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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992ace410c
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6efda16713
1 changed files with 12 additions and 3 deletions
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@ -78,6 +78,9 @@ MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
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#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
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#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
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#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
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#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
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#define mmTHM_BACO_CNTL_ARCT 0xA7
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#define mmTHM_BACO_CNTL_ARCT_BASE_IDX 0
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static int link_width[] = {0, 1, 2, 4, 8, 12, 16};
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static int link_width[] = {0, 1, 2, 4, 8, 12, 16};
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static int link_speed[] = {25, 50, 80, 160};
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static int link_speed[] = {25, 50, 80, 160};
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@ -1532,9 +1535,15 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
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break;
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break;
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default:
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default:
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if (!ras || !ras->supported) {
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if (!ras || !ras->supported) {
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data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
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if (adev->asic_type == CHIP_ARCTURUS) {
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data |= 0x80000000;
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data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
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WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
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data |= 0x80000000;
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WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data);
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} else {
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data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
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data |= 0x80000000;
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WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
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}
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ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
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ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
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} else {
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} else {
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