mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-04 08:08:54 +00:00
ARM: arm-soc driver changes for 3.10
This is a rather large set of patches for device drivers that for one
reason or another the subsystem maintainer preferred to get merged
through the arm-soc tree. There are both new drivers as well as
existing drivers that are getting converted from platform-specific
code into standalone drivers using the appropriate subsystem
specific interfaces.
In particular, we can now have pinctrl, clk, clksource and irqchip
drivers in one file per driver, without the need to call into
platform specific interface, or to get called from platform specific
code, as long as all information about the hardware is provided
through a device tree.
Most of the drivers we touch this time are for clocksource. Since
now most of them are part of drivers/clocksource, I expect that we
won't have to touch these again from arm-soc and can let the
clocksource maintainers take care of these in the future.
Another larger part of this series is specific to the exynos platform,
which is seeing some significant effort in upstreaming and
modernization of its device drivers this time around, which
unfortunately is also the cause for the churn and a lot of the
merge conflicts.
There is one new subsystem that gets merged as part of this series:
the reset controller interface, which is a very simple interface
for taking devices on the SoC out of reset or back into reset.
Patches to use this interface on i.MX follow later in this merge
window, and we are going to have other platforms (at least tegra
and sirf) get converted in 3.11. This will let us get rid of
platform specific callbacks in a number of platform independent
device drivers.
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Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver changes from Olof Johansson:
"This is a rather large set of patches for device drivers that for one
reason or another the subsystem maintainer preferred to get merged
through the arm-soc tree. There are both new drivers as well as
existing drivers that are getting converted from platform-specific
code into standalone drivers using the appropriate subsystem specific
interfaces.
In particular, we can now have pinctrl, clk, clksource and irqchip
drivers in one file per driver, without the need to call into platform
specific interface, or to get called from platform specific code, as
long as all information about the hardware is provided through a
device tree.
Most of the drivers we touch this time are for clocksource. Since now
most of them are part of drivers/clocksource, I expect that we won't
have to touch these again from arm-soc and can let the clocksource
maintainers take care of these in the future.
Another larger part of this series is specific to the exynos platform,
which is seeing some significant effort in upstreaming and
modernization of its device drivers this time around, which
unfortunately is also the cause for the churn and a lot of the merge
conflicts.
There is one new subsystem that gets merged as part of this series:
the reset controller interface, which is a very simple interface for
taking devices on the SoC out of reset or back into reset. Patches to
use this interface on i.MX follow later in this merge window, and we
are going to have other platforms (at least tegra and sirf) get
converted in 3.11. This will let us get rid of platform specific
callbacks in a number of platform independent device drivers."
* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (256 commits)
irqchip: s3c24xx: add missing __init annotations
ARM: dts: Disable the RTC by default on exynos5
clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3}
ARM: exynos: restore mach/regs-clock.h for exynos5
clocksource: exynos_mct: fix build error on non-DT
pinctrl: vt8500: wmt: Fix checking return value of pinctrl_register()
irqchip: vt8500: Convert arch-vt8500 to new irqchip infrastructure
reset: NULL deref on allocation failure
reset: Add reset controller API
dt: describe base reset signal binding
ARM: EXYNOS: Add arm-pmu DT binding for exynos421x
ARM: EXYNOS: Add arm-pmu DT binding for exynos5250
ARM: EXYNOS: Enable PMUs for exynos4
irqchip: exynos-combiner: Correct combined IRQs for exynos4
irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq
ARM: EXYNOS: fix compilation error introduced due to common clock migration
clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
clk: exynos4: export clocks required for fimc-is
clk: samsung: Fix compilation error
clk: tegra: fix enum tegra114_clk to match binding
...
This commit is contained in:
Linus Torvalds
commit
6fa52ed33b
253 changed files with 16898 additions and 7299 deletions
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|
@ -35,36 +35,83 @@ Required properties:
|
|||
|
||||
Timing properties for child nodes. All are optional and default to 0.
|
||||
|
||||
- gpmc,sync-clk: Minimum clock period for synchronous mode, in picoseconds
|
||||
- gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds
|
||||
|
||||
Chip-select signal timings corresponding to GPMC_CONFIG2:
|
||||
- gpmc,cs-on: Assertion time
|
||||
- gpmc,cs-rd-off: Read deassertion time
|
||||
- gpmc,cs-wr-off: Write deassertion time
|
||||
Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:
|
||||
- gpmc,cs-on-ns: Assertion time
|
||||
- gpmc,cs-rd-off-ns: Read deassertion time
|
||||
- gpmc,cs-wr-off-ns: Write deassertion time
|
||||
|
||||
ADV signal timings corresponding to GPMC_CONFIG3:
|
||||
- gpmc,adv-on: Assertion time
|
||||
- gpmc,adv-rd-off: Read deassertion time
|
||||
- gpmc,adv-wr-off: Write deassertion time
|
||||
ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3:
|
||||
- gpmc,adv-on-ns: Assertion time
|
||||
- gpmc,adv-rd-off-ns: Read deassertion time
|
||||
- gpmc,adv-wr-off-ns: Write deassertion time
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||||
|
||||
WE signals timings corresponding to GPMC_CONFIG4:
|
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- gpmc,we-on: Assertion time
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- gpmc,we-off: Deassertion time
|
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WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
|
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- gpmc,we-on-ns Assertion time
|
||||
- gpmc,we-off-ns: Deassertion time
|
||||
|
||||
OE signals timings corresponding to GPMC_CONFIG4:
|
||||
- gpmc,oe-on: Assertion time
|
||||
- gpmc,oe-off: Deassertion time
|
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OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
|
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- gpmc,oe-on-ns: Assertion time
|
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- gpmc,oe-off-ns: Deassertion time
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Access time and cycle time timings corresponding to GPMC_CONFIG5:
|
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- gpmc,page-burst-access: Multiple access word delay
|
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- gpmc,access: Start-cycle to first data valid delay
|
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- gpmc,rd-cycle: Total read cycle time
|
||||
- gpmc,wr-cycle: Total write cycle time
|
||||
Access time and cycle time timings (in nanoseconds) corresponding to
|
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GPMC_CONFIG5:
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- gpmc,page-burst-access-ns: Multiple access word delay
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- gpmc,access-ns: Start-cycle to first data valid delay
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- gpmc,rd-cycle-ns: Total read cycle time
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- gpmc,wr-cycle-ns: Total write cycle time
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- gpmc,bus-turnaround-ns: Turn-around time between successive accesses
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- gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses
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- gpmc,clk-activation-ns: GPMC clock activation time
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- gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid
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data
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Boolean timing parameters. If property is present parameter enabled and
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disabled if omitted:
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- gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock
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- gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock
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- gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive
|
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accesses to a different CS
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- gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive
|
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accesses to the same CS
|
||||
- gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock
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- gpmc,we-extra-delay: WE signal is delayed by half GPMC clock
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- gpmc,time-para-granularity: Multiply all access times by 2
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The following are only applicable to OMAP3+ and AM335x:
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- gpmc,wr-access
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- gpmc,wr-data-mux-bus
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- gpmc,wr-access-ns: In synchronous write mode, for single or
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burst accesses, defines the number of
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GPMC_FCLK cycles from start access time
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to the GPMC_CLK rising edge used by the
|
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memory device for the first data capture.
|
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- gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies
|
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the time when the first data is driven on
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the address-data bus.
|
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|
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GPMC chip-select settings properties for child nodes. All are optional.
|
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|
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- gpmc,burst-length Page/burst length. Must be 4, 8 or 16.
|
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- gpmc,burst-wrap Enables wrap bursting
|
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- gpmc,burst-read Enables read page/burst mode
|
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- gpmc,burst-write Enables write page/burst mode
|
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- gpmc,device-nand Device is NAND
|
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- gpmc,device-width Total width of device(s) connected to a GPMC
|
||||
chip-select in bytes. The GPMC supports 8-bit
|
||||
and 16-bit devices and so this property must be
|
||||
1 or 2.
|
||||
- gpmc,mux-add-data Address and data multiplexing configuration.
|
||||
Valid values are 1 for address-address-data
|
||||
multiplexing mode and 2 for address-data
|
||||
multiplexing mode.
|
||||
- gpmc,sync-read Enables synchronous read. Defaults to asynchronous
|
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is this is not set.
|
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- gpmc,sync-write Enables synchronous writes. Defaults to asynchronous
|
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is this is not set.
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- gpmc,wait-pin Wait-pin used by client. Must be less than
|
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"gpmc,num-waitpins".
|
||||
- gpmc,wait-on-read Enables wait monitoring on reads.
|
||||
- gpmc,wait-on-write Enables wait monitoring on writes.
|
||||
|
||||
Example for an AM33xx board:
|
||||
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||||
|
|
|
|||
288
Documentation/devicetree/bindings/clock/exynos4-clock.txt
Normal file
288
Documentation/devicetree/bindings/clock/exynos4-clock.txt
Normal file
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|
@ -0,0 +1,288 @@
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* Samsung Exynos4 Clock Controller
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|
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The Exynos4 clock controller generates and supplies clock to various controllers
|
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within the Exynos4 SoC. The clock binding described here is applicable to all
|
||||
SoC's in the Exynos4 family.
|
||||
|
||||
Required Properties:
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||||
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||||
- comptible: should be one of the following.
|
||||
- "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
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- "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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The following is the list of clocks generated by the controller. Each clock is
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assigned an identifier and client nodes use this identifier to specify the
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clock which they consume. Some of the clocks are available only on a particular
|
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Exynos4 SoC and this is specified where applicable.
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[Core Clocks]
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Clock ID SoC (if specific)
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||||
-----------------------------------------------
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||||
xxti 1
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xusbxti 2
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fin_pll 3
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fout_apll 4
|
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fout_mpll 5
|
||||
fout_epll 6
|
||||
fout_vpll 7
|
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sclk_apll 8
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sclk_mpll 9
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sclk_epll 10
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sclk_vpll 11
|
||||
arm_clk 12
|
||||
aclk200 13
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||||
aclk100 14
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||||
aclk160 15
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aclk133 16
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mout_mpll_user_t 17 Exynos4x12
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||||
mout_mpll_user_c 18 Exynos4x12
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mout_core 19
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mout_apll 20
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[Clock Gate for Special Clocks]
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Clock ID SoC (if specific)
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||||
-----------------------------------------------
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sclk_fimc0 128
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sclk_fimc1 129
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sclk_fimc2 130
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sclk_fimc3 131
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sclk_cam0 132
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sclk_cam1 133
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sclk_csis0 134
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sclk_csis1 135
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sclk_hdmi 136
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sclk_mixer 137
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sclk_dac 138
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sclk_pixel 139
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sclk_fimd0 140
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sclk_mdnie0 141 Exynos4412
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sclk_mdnie_pwm0 12 142 Exynos4412
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sclk_mipi0 143
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sclk_audio0 144
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sclk_mmc0 145
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sclk_mmc1 146
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sclk_mmc2 147
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sclk_mmc3 148
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sclk_mmc4 149
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sclk_sata 150 Exynos4210
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sclk_uart0 151
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||||
sclk_uart1 152
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||||
sclk_uart2 153
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sclk_uart3 154
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||||
sclk_uart4 155
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sclk_audio1 156
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sclk_audio2 157
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sclk_spdif 158
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sclk_spi0 159
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sclk_spi1 160
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sclk_spi2 161
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sclk_slimbus 162
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sclk_fimd1 163 Exynos4210
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sclk_mipi1 164 Exynos4210
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||||
sclk_pcm1 165
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sclk_pcm2 166
|
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sclk_i2s1 167
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sclk_i2s2 168
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||||
sclk_mipihsi 169 Exynos4412
|
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sclk_mfc 170
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sclk_pcm0 171
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sclk_g3d 172
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||||
sclk_pwm_isp 173 Exynos4x12
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||||
sclk_spi0_isp 174 Exynos4x12
|
||||
sclk_spi1_isp 175 Exynos4x12
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||||
sclk_uart_isp 176 Exynos4x12
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||||
|
||||
[Peripheral Clock Gates]
|
||||
|
||||
Clock ID SoC (if specific)
|
||||
-----------------------------------------------
|
||||
|
||||
fimc0 256
|
||||
fimc1 257
|
||||
fimc2 258
|
||||
fimc3 259
|
||||
csis0 260
|
||||
csis1 261
|
||||
jpeg 262
|
||||
smmu_fimc0 263
|
||||
smmu_fimc1 264
|
||||
smmu_fimc2 265
|
||||
smmu_fimc3 266
|
||||
smmu_jpeg 267
|
||||
vp 268
|
||||
mixer 269
|
||||
tvenc 270 Exynos4210
|
||||
hdmi 271
|
||||
smmu_tv 272
|
||||
mfc 273
|
||||
smmu_mfcl 274
|
||||
smmu_mfcr 275
|
||||
g3d 276
|
||||
g2d 277 Exynos4210
|
||||
rotator 278 Exynos4210
|
||||
mdma 279 Exynos4210
|
||||
smmu_g2d 280 Exynos4210
|
||||
smmu_rotator 281 Exynos4210
|
||||
smmu_mdma 282 Exynos4210
|
||||
fimd0 283
|
||||
mie0 284
|
||||
mdnie0 285 Exynos4412
|
||||
dsim0 286
|
||||
smmu_fimd0 287
|
||||
fimd1 288 Exynos4210
|
||||
mie1 289 Exynos4210
|
||||
dsim1 290 Exynos4210
|
||||
smmu_fimd1 291 Exynos4210
|
||||
pdma0 292
|
||||
pdma1 293
|
||||
pcie_phy 294
|
||||
sata_phy 295 Exynos4210
|
||||
tsi 296
|
||||
sdmmc0 297
|
||||
sdmmc1 298
|
||||
sdmmc2 299
|
||||
sdmmc3 300
|
||||
sdmmc4 301
|
||||
sata 302 Exynos4210
|
||||
sromc 303
|
||||
usb_host 304
|
||||
usb_device 305
|
||||
pcie 306
|
||||
onenand 307
|
||||
nfcon 308
|
||||
smmu_pcie 309
|
||||
gps 310
|
||||
smmu_gps 311
|
||||
uart0 312
|
||||
uart1 313
|
||||
uart2 314
|
||||
uart3 315
|
||||
uart4 316
|
||||
i2c0 317
|
||||
i2c1 318
|
||||
i2c2 319
|
||||
i2c3 320
|
||||
i2c4 321
|
||||
i2c5 322
|
||||
i2c6 323
|
||||
i2c7 324
|
||||
i2c_hdmi 325
|
||||
tsadc 326
|
||||
spi0 327
|
||||
spi1 328
|
||||
spi2 329
|
||||
i2s1 330
|
||||
i2s2 331
|
||||
pcm0 332
|
||||
i2s0 333
|
||||
pcm1 334
|
||||
pcm2 335
|
||||
pwm 336
|
||||
slimbus 337
|
||||
spdif 338
|
||||
ac97 339
|
||||
modemif 340
|
||||
chipid 341
|
||||
sysreg 342
|
||||
hdmi_cec 343
|
||||
mct 344
|
||||
wdt 345
|
||||
rtc 346
|
||||
keyif 347
|
||||
audss 348
|
||||
mipi_hsi 349 Exynos4210
|
||||
mdma2 350 Exynos4210
|
||||
pixelasyncm0 351
|
||||
pixelasyncm1 352
|
||||
fimc_lite0 353 Exynos4x12
|
||||
fimc_lite1 354 Exynos4x12
|
||||
ppmuispx 355 Exynos4x12
|
||||
ppmuispmx 356 Exynos4x12
|
||||
fimc_isp 357 Exynos4x12
|
||||
fimc_drc 358 Exynos4x12
|
||||
fimc_fd 359 Exynos4x12
|
||||
mcuisp 360 Exynos4x12
|
||||
gicisp 361 Exynos4x12
|
||||
smmu_isp 362 Exynos4x12
|
||||
smmu_drc 363 Exynos4x12
|
||||
smmu_fd 364 Exynos4x12
|
||||
smmu_lite0 365 Exynos4x12
|
||||
smmu_lite1 366 Exynos4x12
|
||||
mcuctl_isp 367 Exynos4x12
|
||||
mpwm_isp 368 Exynos4x12
|
||||
i2c0_isp 369 Exynos4x12
|
||||
i2c1_isp 370 Exynos4x12
|
||||
mtcadc_isp 371 Exynos4x12
|
||||
pwm_isp 372 Exynos4x12
|
||||
wdt_isp 373 Exynos4x12
|
||||
uart_isp 374 Exynos4x12
|
||||
asyncaxim 375 Exynos4x12
|
||||
smmu_ispcx 376 Exynos4x12
|
||||
spi0_isp 377 Exynos4x12
|
||||
spi1_isp 378 Exynos4x12
|
||||
pwm_isp_sclk 379 Exynos4x12
|
||||
spi0_isp_sclk 380 Exynos4x12
|
||||
spi1_isp_sclk 381 Exynos4x12
|
||||
uart_isp_sclk 382 Exynos4x12
|
||||
|
||||
[Mux Clocks]
|
||||
|
||||
Clock ID SoC (if specific)
|
||||
-----------------------------------------------
|
||||
|
||||
mout_fimc0 384
|
||||
mout_fimc1 385
|
||||
mout_fimc2 386
|
||||
mout_fimc3 387
|
||||
mout_cam0 388
|
||||
mout_cam1 389
|
||||
mout_csis0 390
|
||||
mout_csis1 391
|
||||
mout_g3d0 392
|
||||
mout_g3d1 393
|
||||
mout_g3d 394
|
||||
aclk400_mcuisp 395 Exynos4x12
|
||||
|
||||
[Div Clocks]
|
||||
|
||||
Clock ID SoC (if specific)
|
||||
-----------------------------------------------
|
||||
|
||||
div_isp0 450 Exynos4x12
|
||||
div_isp1 451 Exynos4x12
|
||||
div_mcuisp0 452 Exynos4x12
|
||||
div_mcuisp1 453 Exynos4x12
|
||||
div_aclk200 454 Exynos4x12
|
||||
div_aclk400_mcuisp 455 Exynos4x12
|
||||
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
clock: clock-controller@0x10030000 {
|
||||
compatible = "samsung,exynos4210-clock";
|
||||
reg = <0x10030000 0x20000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example 2: UART controller node that consumes the clock generated by the clock
|
||||
controller. Refer to the standard clock bindings for information
|
||||
about 'clocks' and 'clock-names' property.
|
||||
|
||||
serial@13820000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13820000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
clocks = <&clock 314>, <&clock 153>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
177
Documentation/devicetree/bindings/clock/exynos5250-clock.txt
Normal file
177
Documentation/devicetree/bindings/clock/exynos5250-clock.txt
Normal file
|
|
@ -0,0 +1,177 @@
|
|||
* Samsung Exynos5250 Clock Controller
|
||||
|
||||
The Exynos5250 clock controller generates and supplies clock to various
|
||||
controllers within the Exynos5250 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- comptible: should be one of the following.
|
||||
- "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
The following is the list of clocks generated by the controller. Each clock is
|
||||
assigned an identifier and client nodes use this identifier to specify the
|
||||
clock which they consume.
|
||||
|
||||
|
||||
[Core Clocks]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
fin_pll 1
|
||||
|
||||
[Clock Gate for Special Clocks]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
sclk_cam_bayer 128
|
||||
sclk_cam0 129
|
||||
sclk_cam1 130
|
||||
sclk_gscl_wa 131
|
||||
sclk_gscl_wb 132
|
||||
sclk_fimd1 133
|
||||
sclk_mipi1 134
|
||||
sclk_dp 135
|
||||
sclk_hdmi 136
|
||||
sclk_pixel 137
|
||||
sclk_audio0 138
|
||||
sclk_mmc0 139
|
||||
sclk_mmc1 140
|
||||
sclk_mmc2 141
|
||||
sclk_mmc3 142
|
||||
sclk_sata 143
|
||||
sclk_usb3 144
|
||||
sclk_jpeg 145
|
||||
sclk_uart0 146
|
||||
sclk_uart1 147
|
||||
sclk_uart2 148
|
||||
sclk_uart3 149
|
||||
sclk_pwm 150
|
||||
sclk_audio1 151
|
||||
sclk_audio2 152
|
||||
sclk_spdif 153
|
||||
sclk_spi0 154
|
||||
sclk_spi1 155
|
||||
sclk_spi2 156
|
||||
|
||||
|
||||
[Peripheral Clock Gates]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
gscl0 256
|
||||
gscl1 257
|
||||
gscl2 258
|
||||
gscl3 259
|
||||
gscl_wa 260
|
||||
gscl_wb 261
|
||||
smmu_gscl0 262
|
||||
smmu_gscl1 263
|
||||
smmu_gscl2 264
|
||||
smmu_gscl3 265
|
||||
mfc 266
|
||||
smmu_mfcl 267
|
||||
smmu_mfcr 268
|
||||
rotator 269
|
||||
jpeg 270
|
||||
mdma1 271
|
||||
smmu_rotator 272
|
||||
smmu_jpeg 273
|
||||
smmu_mdma1 274
|
||||
pdma0 275
|
||||
pdma1 276
|
||||
sata 277
|
||||
usbotg 278
|
||||
mipi_hsi 279
|
||||
sdmmc0 280
|
||||
sdmmc1 281
|
||||
sdmmc2 282
|
||||
sdmmc3 283
|
||||
sromc 284
|
||||
usb2 285
|
||||
usb3 286
|
||||
sata_phyctrl 287
|
||||
sata_phyi2c 288
|
||||
uart0 289
|
||||
uart1 290
|
||||
uart2 291
|
||||
uart3 292
|
||||
uart4 293
|
||||
i2c0 294
|
||||
i2c1 295
|
||||
i2c2 296
|
||||
i2c3 297
|
||||
i2c4 298
|
||||
i2c5 299
|
||||
i2c6 300
|
||||
i2c7 301
|
||||
i2c_hdmi 302
|
||||
adc 303
|
||||
spi0 304
|
||||
spi1 305
|
||||
spi2 306
|
||||
i2s1 307
|
||||
i2s2 308
|
||||
pcm1 309
|
||||
pcm2 310
|
||||
pwm 311
|
||||
spdif 312
|
||||
ac97 313
|
||||
hsi2c0 314
|
||||
hsi2c1 315
|
||||
hs12c2 316
|
||||
hs12c3 317
|
||||
chipid 318
|
||||
sysreg 319
|
||||
pmu 320
|
||||
cmu_top 321
|
||||
cmu_core 322
|
||||
cmu_mem 323
|
||||
tzpc0 324
|
||||
tzpc1 325
|
||||
tzpc2 326
|
||||
tzpc3 327
|
||||
tzpc4 328
|
||||
tzpc5 329
|
||||
tzpc6 330
|
||||
tzpc7 331
|
||||
tzpc8 332
|
||||
tzpc9 333
|
||||
hdmi_cec 334
|
||||
mct 335
|
||||
wdt 336
|
||||
rtc 337
|
||||
tmu 338
|
||||
fimd1 339
|
||||
mie1 340
|
||||
dsim0 341
|
||||
dp 342
|
||||
mixer 343
|
||||
hdmi 345
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
clock: clock-controller@0x10010000 {
|
||||
compatible = "samsung,exynos5250-clock";
|
||||
reg = <0x10010000 0x30000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example 2: UART controller node that consumes the clock generated by the clock
|
||||
controller. Refer to the standard clock bindings for information
|
||||
about 'clocks' and 'clock-names' property.
|
||||
|
||||
serial@13820000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13820000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
clocks = <&clock 314>, <&clock 153>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
61
Documentation/devicetree/bindings/clock/exynos5440-clock.txt
Normal file
61
Documentation/devicetree/bindings/clock/exynos5440-clock.txt
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
* Samsung Exynos5440 Clock Controller
|
||||
|
||||
The Exynos5440 clock controller generates and supplies clock to various
|
||||
controllers within the Exynos5440 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- comptible: should be "samsung,exynos5440-clock".
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
The following is the list of clocks generated by the controller. Each clock is
|
||||
assigned an identifier and client nodes use this identifier to specify the
|
||||
clock which they consume.
|
||||
|
||||
|
||||
[Core Clocks]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
xtal 1
|
||||
arm_clk 2
|
||||
|
||||
[Peripheral Clock Gates]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
spi_baud 16
|
||||
pb0_250 17
|
||||
pr0_250 18
|
||||
pr1_250 19
|
||||
b_250 20
|
||||
b_125 21
|
||||
b_200 22
|
||||
sata 23
|
||||
usb 24
|
||||
gmac0 25
|
||||
cs250 26
|
||||
pb0_250_o 27
|
||||
pr0_250_o 28
|
||||
pr1_250_o 29
|
||||
b_250_o 30
|
||||
b_125_o 31
|
||||
b_200_o 32
|
||||
sata_o 33
|
||||
usb_o 34
|
||||
gmac0_o 35
|
||||
cs250_o 36
|
||||
|
||||
Example: An example of a clock controller node is listed below.
|
||||
|
||||
clock: clock-controller@0x10010000 {
|
||||
compatible = "samsung,exynos5440-clock";
|
||||
reg = <0x160000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
303
Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
Normal file
303
Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
Normal file
|
|
@ -0,0 +1,303 @@
|
|||
NVIDIA Tegra114 Clock And Reset Controller
|
||||
|
||||
This binding uses the common clock binding:
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
|
||||
for muxing and gating Tegra's clocks, and setting their rates.
|
||||
|
||||
Required properties :
|
||||
- compatible : Should be "nvidia,tegra114-car"
|
||||
- reg : Should contain CAR registers location and length
|
||||
- clocks : Should contain phandle and clock specifiers for two clocks:
|
||||
the 32 KHz "32k_in", and the board-specific oscillator "osc".
|
||||
- #clock-cells : Should be 1.
|
||||
In clock consumers, this cell represents the clock ID exposed by the CAR.
|
||||
|
||||
The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
|
||||
registers. These IDs often match those in the CAR's RST_DEVICES registers,
|
||||
but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
|
||||
this case, those clocks are assigned IDs above 160 in order to highlight
|
||||
this issue. Implementations that interpret these clock IDs as bit values
|
||||
within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
|
||||
explicitly handle these special cases.
|
||||
|
||||
The balance of the clocks controlled by the CAR are assigned IDs of 160 and
|
||||
above.
|
||||
|
||||
0 unassigned
|
||||
1 unassigned
|
||||
2 unassigned
|
||||
3 unassigned
|
||||
4 rtc
|
||||
5 timer
|
||||
6 uarta
|
||||
7 unassigned (register bit affects uartb and vfir)
|
||||
8 unassigned
|
||||
9 sdmmc2
|
||||
10 unassigned (register bit affects spdif_in and spdif_out)
|
||||
11 i2s1
|
||||
12 i2c1
|
||||
13 ndflash
|
||||
14 sdmmc1
|
||||
15 sdmmc4
|
||||
16 unassigned
|
||||
17 pwm
|
||||
18 i2s2
|
||||
19 epp
|
||||
20 unassigned (register bit affects vi and vi_sensor)
|
||||
21 2d
|
||||
22 usbd
|
||||
23 isp
|
||||
24 3d
|
||||
25 unassigned
|
||||
26 disp2
|
||||
27 disp1
|
||||
28 host1x
|
||||
29 vcp
|
||||
30 i2s0
|
||||
31 unassigned
|
||||
|
||||
32 unassigned
|
||||
33 unassigned
|
||||
34 apbdma
|
||||
35 unassigned
|
||||
36 kbc
|
||||
37 unassigned
|
||||
38 unassigned
|
||||
39 unassigned (register bit affects fuse and fuse_burn)
|
||||
40 kfuse
|
||||
41 sbc1
|
||||
42 nor
|
||||
43 unassigned
|
||||
44 sbc2
|
||||
45 unassigned
|
||||
46 sbc3
|
||||
47 i2c5
|
||||
48 dsia
|
||||
49 unassigned
|
||||
50 mipi
|
||||
51 hdmi
|
||||
52 csi
|
||||
53 unassigned
|
||||
54 i2c2
|
||||
55 uartc
|
||||
56 mipi-cal
|
||||
57 emc
|
||||
58 usb2
|
||||
59 usb3
|
||||
60 msenc
|
||||
61 vde
|
||||
62 bsea
|
||||
63 bsev
|
||||
|
||||
64 unassigned
|
||||
65 uartd
|
||||
66 unassigned
|
||||
67 i2c3
|
||||
68 sbc4
|
||||
69 sdmmc3
|
||||
70 unassigned
|
||||
71 owr
|
||||
72 afi
|
||||
73 csite
|
||||
74 unassigned
|
||||
75 unassigned
|
||||
76 la
|
||||
77 trace
|
||||
78 soc_therm
|
||||
79 dtv
|
||||
80 ndspeed
|
||||
81 i2cslow
|
||||
82 dsib
|
||||
83 tsec
|
||||
84 unassigned
|
||||
85 unassigned
|
||||
86 unassigned
|
||||
87 unassigned
|
||||
88 unassigned
|
||||
89 xusb_host
|
||||
90 unassigned
|
||||
91 msenc
|
||||
92 csus
|
||||
93 unassigned
|
||||
94 unassigned
|
||||
95 unassigned (bit affects xusb_dev and xusb_dev_src)
|
||||
|
||||
96 unassigned
|
||||
97 unassigned
|
||||
98 unassigned
|
||||
99 mselect
|
||||
100 tsensor
|
||||
101 i2s3
|
||||
102 i2s4
|
||||
103 i2c4
|
||||
104 sbc5
|
||||
105 sbc6
|
||||
106 d_audio
|
||||
107 apbif
|
||||
108 dam0
|
||||
109 dam1
|
||||
110 dam2
|
||||
111 hda2codec_2x
|
||||
112 unassigned
|
||||
113 audio0_2x
|
||||
114 audio1_2x
|
||||
115 audio2_2x
|
||||
116 audio3_2x
|
||||
117 audio4_2x
|
||||
118 spdif_2x
|
||||
119 actmon
|
||||
120 extern1
|
||||
121 extern2
|
||||
122 extern3
|
||||
123 unassigned
|
||||
124 unassigned
|
||||
125 hda
|
||||
126 unassigned
|
||||
127 se
|
||||
|
||||
128 hda2hdmi
|
||||
129 unassigned
|
||||
130 unassigned
|
||||
131 unassigned
|
||||
132 unassigned
|
||||
133 unassigned
|
||||
134 unassigned
|
||||
135 unassigned
|
||||
136 unassigned
|
||||
137 unassigned
|
||||
138 unassigned
|
||||
139 unassigned
|
||||
140 unassigned
|
||||
141 unassigned
|
||||
142 unassigned
|
||||
143 unassigned (bit affects xusb_falcon_src, xusb_fs_src,
|
||||
xusb_host_src and xusb_ss_src)
|
||||
144 cilab
|
||||
145 cilcd
|
||||
146 cile
|
||||
147 dsialp
|
||||
148 dsiblp
|
||||
149 unassigned
|
||||
150 dds
|
||||
151 unassigned
|
||||
152 dp2
|
||||
153 amx
|
||||
154 adx
|
||||
155 unassigned (bit affects dfll_ref and dfll_soc)
|
||||
156 xusb_ss
|
||||
|
||||
192 uartb
|
||||
193 vfir
|
||||
194 spdif_in
|
||||
195 spdif_out
|
||||
196 vi
|
||||
197 vi_sensor
|
||||
198 fuse
|
||||
199 fuse_burn
|
||||
200 clk_32k
|
||||
201 clk_m
|
||||
202 clk_m_div2
|
||||
203 clk_m_div4
|
||||
204 pll_ref
|
||||
205 pll_c
|
||||
206 pll_c_out1
|
||||
207 pll_c2
|
||||
208 pll_c3
|
||||
209 pll_m
|
||||
210 pll_m_out1
|
||||
211 pll_p
|
||||
212 pll_p_out1
|
||||
213 pll_p_out2
|
||||
214 pll_p_out3
|
||||
215 pll_p_out4
|
||||
216 pll_a
|
||||
217 pll_a_out0
|
||||
218 pll_d
|
||||
219 pll_d_out0
|
||||
220 pll_d2
|
||||
221 pll_d2_out0
|
||||
222 pll_u
|
||||
223 pll_u_480M
|
||||
224 pll_u_60M
|
||||
225 pll_u_48M
|
||||
226 pll_u_12M
|
||||
227 pll_x
|
||||
228 pll_x_out0
|
||||
229 pll_re_vco
|
||||
230 pll_re_out
|
||||
231 pll_e_out0
|
||||
232 spdif_in_sync
|
||||
233 i2s0_sync
|
||||
234 i2s1_sync
|
||||
235 i2s2_sync
|
||||
236 i2s3_sync
|
||||
237 i2s4_sync
|
||||
238 vimclk_sync
|
||||
239 audio0
|
||||
240 audio1
|
||||
241 audio2
|
||||
242 audio3
|
||||
243 audio4
|
||||
244 spdif
|
||||
245 clk_out_1
|
||||
246 clk_out_2
|
||||
247 clk_out_3
|
||||
248 blink
|
||||
252 xusb_host_src
|
||||
253 xusb_falcon_src
|
||||
254 xusb_fs_src
|
||||
255 xusb_ss_src
|
||||
256 xusb_dev_src
|
||||
257 xusb_dev
|
||||
258 xusb_hs_src
|
||||
259 sclk
|
||||
260 hclk
|
||||
261 pclk
|
||||
262 cclk_g
|
||||
263 cclk_lp
|
||||
264 dfll_ref
|
||||
265 dfll_soc
|
||||
|
||||
Example SoC include file:
|
||||
|
||||
/ {
|
||||
tegra_car: clock {
|
||||
compatible = "nvidia,tegra114-car";
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
usb@c5004000 {
|
||||
clocks = <&tegra_car 58>; /* usb2 */
|
||||
};
|
||||
};
|
||||
|
||||
Example board file:
|
||||
|
||||
/ {
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
osc: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
clk_32k: clock@1 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <1>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
&tegra_car {
|
||||
clocks = <&clk_32k> <&osc>;
|
||||
};
|
||||
};
|
||||
|
|
@ -120,8 +120,8 @@ Required properties :
|
|||
90 clk_d
|
||||
91 unassigned
|
||||
92 sus
|
||||
93 cdev1
|
||||
94 cdev2
|
||||
93 cdev2
|
||||
94 cdev1
|
||||
95 unassigned
|
||||
|
||||
96 uart2
|
||||
|
|
|
|||
|
|
@ -1,24 +0,0 @@
|
|||
VIA/Wondermedia VT8500 GPIO Controller
|
||||
-----------------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible : "via,vt8500-gpio", "wm,wm8505-gpio"
|
||||
or "wm,wm8650-gpio" depending on your SoC
|
||||
- reg : Should contain 1 register range (address and length)
|
||||
- #gpio-cells : should be <3>.
|
||||
1) bank
|
||||
2) pin number
|
||||
3) flags - should be 0
|
||||
|
||||
Example:
|
||||
|
||||
gpio: gpio-controller@d8110000 {
|
||||
compatible = "via,vt8500-gpio";
|
||||
gpio-controller;
|
||||
reg = <0xd8110000 0x10000>;
|
||||
#gpio-cells = <3>;
|
||||
};
|
||||
|
||||
vibrate {
|
||||
gpios = <&gpio 0 1 0>; /* Bank 0, Pin 1, No flags */
|
||||
};
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
Samsung S3C24XX Interrupt Controllers
|
||||
|
||||
The S3C24XX SoCs contain a custom set of interrupt controllers providing a
|
||||
varying number of interrupt sources. The set consists of a main- and sub-
|
||||
controller and on newer SoCs even a second main controller.
|
||||
|
||||
Required properties:
|
||||
- compatible: Compatible property value should be "samsung,s3c2410-irq"
|
||||
for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later.
|
||||
|
||||
- reg: Physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The value shall be 4 and interrupt descriptor shall
|
||||
have the following format:
|
||||
<ctrl_num parent_irq ctrl_irq type>
|
||||
|
||||
ctrl_num contains the controller to use:
|
||||
- 0 ... main controller
|
||||
- 1 ... sub controller
|
||||
- 2 ... second main controller on s3c2416 and s3c2450
|
||||
parent_irq contains the parent bit in the main controller and will be
|
||||
ignored in main controllers
|
||||
ctrl_irq contains the interrupt bit of the controller
|
||||
type contains the trigger type to use
|
||||
|
||||
Example:
|
||||
|
||||
interrupt-controller@4a000000 {
|
||||
compatible = "samsung,s3c2410-irq";
|
||||
reg = <0x4a000000 0x100>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells=<4>;
|
||||
};
|
||||
|
||||
[...]
|
||||
|
||||
serial@50000000 {
|
||||
compatible = "samsung,s3c2410-uart";
|
||||
reg = <0x50000000 0x4000>;
|
||||
interrupt-parent = <&subintc>;
|
||||
interrupts = <1 28 0 4>, <1 28 1 4>;
|
||||
};
|
||||
|
||||
rtc@57000000 {
|
||||
compatible = "samsung,s3c2410-rtc";
|
||||
reg = <0x57000000 0x100>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 30 0 3>, <0 8 0 3>;
|
||||
};
|
||||
|
|
@ -21,3 +21,24 @@ Required properties:
|
|||
|
||||
- samsung,mfc-l : Base address of the second memory bank used by MFC
|
||||
for DMA contiguous memory allocation and its size.
|
||||
|
||||
Optional properties:
|
||||
- samsung,power-domain : power-domain property defined with a phandle
|
||||
to respective power domain.
|
||||
|
||||
Example:
|
||||
SoC specific DT entry:
|
||||
|
||||
mfc: codec@13400000 {
|
||||
compatible = "samsung,mfc-v5";
|
||||
reg = <0x13400000 0x10000>;
|
||||
interrupts = <0 94 0>;
|
||||
samsung,power-domain = <&pd_mfc>;
|
||||
};
|
||||
|
||||
Board specific DT entry:
|
||||
|
||||
codec@13400000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
};
|
||||
|
|
|
|||
98
Documentation/devicetree/bindings/mtd/gpmc-nor.txt
Normal file
98
Documentation/devicetree/bindings/mtd/gpmc-nor.txt
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
Device tree bindings for NOR flash connect to TI GPMC
|
||||
|
||||
NOR flash connected to the TI GPMC (found on OMAP boards) are represented as
|
||||
child nodes of the GPMC controller with a name of "nor".
|
||||
|
||||
All timing relevant properties as well as generic GPMC child properties are
|
||||
explained in a separate documents. Please refer to
|
||||
Documentation/devicetree/bindings/bus/ti-gpmc.txt
|
||||
|
||||
Required properties:
|
||||
- bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and
|
||||
16-bit devices and so must be either 1 or 2 bytes.
|
||||
- compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
|
||||
- gpmc,cs-on-ns: Chip-select assertion time
|
||||
- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
|
||||
- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
|
||||
- gpmc,oe-on-ns: Output-enable assertion time
|
||||
- gpmc,oe-off-ns: Output-enable de-assertion time
|
||||
- gpmc,we-on-ns Write-enable assertion time
|
||||
- gpmc,we-off-ns: Write-enable de-assertion time
|
||||
- gpmc,access-ns: Start cycle to first data capture (read access)
|
||||
- gpmc,rd-cycle-ns: Total read cycle time
|
||||
- gpmc,wr-cycle-ns: Total write cycle time
|
||||
- linux,mtd-name: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
|
||||
- reg: Chip-select, base address (relative to chip-select)
|
||||
and size of NOR flash. Note that base address will be
|
||||
typically 0 as this is the start of the chip-select.
|
||||
|
||||
Optional properties:
|
||||
- gpmc,XXX Additional GPMC timings and settings parameters. See
|
||||
Documentation/devicetree/bindings/bus/ti-gpmc.txt
|
||||
|
||||
Optional properties for partiton table parsing:
|
||||
- #address-cells: should be set to 1
|
||||
- #size-cells: should be set to 1
|
||||
|
||||
Example:
|
||||
|
||||
gpmc: gpmc@6e000000 {
|
||||
compatible = "ti,omap3430-gpmc", "simple-bus";
|
||||
ti,hwmods = "gpmc";
|
||||
reg = <0x6e000000 0x1000>;
|
||||
interrupts = <20>;
|
||||
gpmc,num-cs = <8>;
|
||||
gpmc,num-waitpins = <4>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ranges = <0 0 0x10000000 0x08000000>;
|
||||
|
||||
nor@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
linux,mtd-name= "intel,pf48f6000m0y1be";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0 0 0x08000000>;
|
||||
bank-width = <2>;
|
||||
|
||||
gpmc,mux-add-data;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <186>;
|
||||
gpmc,cs-wr-off-ns = <186>;
|
||||
gpmc,adv-on-ns = <12>;
|
||||
gpmc,adv-rd-off-ns = <48>;
|
||||
gpmc,adv-wr-off-ns = <48>;
|
||||
gpmc,oe-on-ns = <54>;
|
||||
gpmc,oe-off-ns = <168>;
|
||||
gpmc,we-on-ns = <54>;
|
||||
gpmc,we-off-ns = <168>;
|
||||
gpmc,rd-cycle-ns = <186>;
|
||||
gpmc,wr-cycle-ns = <186>;
|
||||
gpmc,access-ns = <114>;
|
||||
gpmc,page-burst-access-ns = <6>;
|
||||
gpmc,bus-turnaround-ns = <12>;
|
||||
gpmc,cycle2cycle-delay-ns = <18>;
|
||||
gpmc,wr-data-mux-bus-ns = <90>;
|
||||
gpmc,wr-access-ns = <186>;
|
||||
gpmc,cycle2cycle-samecsen;
|
||||
gpmc,cycle2cycle-diffcsen;
|
||||
|
||||
partition@0 {
|
||||
label = "bootloader-nor";
|
||||
reg = <0 0x40000>;
|
||||
};
|
||||
partition@0x40000 {
|
||||
label = "params-nor";
|
||||
reg = <0x40000 0x40000>;
|
||||
};
|
||||
partition@0x80000 {
|
||||
label = "kernel-nor";
|
||||
reg = <0x80000 0x200000>;
|
||||
};
|
||||
partition@0x280000 {
|
||||
label = "filesystem-nor";
|
||||
reg = <0x240000 0x7d80000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -10,6 +10,8 @@ Documentation/devicetree/bindings/bus/ti-gpmc.txt
|
|||
Required properties:
|
||||
|
||||
- reg: The CS line the peripheral is connected to
|
||||
- gpmc,device-width Width of the ONENAND device connected to the GPMC
|
||||
in bytes. Must be 1 or 2.
|
||||
|
||||
Optional properties:
|
||||
|
||||
|
|
@ -34,6 +36,7 @@ Example for an OMAP3430 board:
|
|||
|
||||
onenand@0 {
|
||||
reg = <0 0 0>; /* CS0, offset 0 */
|
||||
gpmc,device-width = <2>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
|
|||
97
Documentation/devicetree/bindings/net/gpmc-eth.txt
Normal file
97
Documentation/devicetree/bindings/net/gpmc-eth.txt
Normal file
|
|
@ -0,0 +1,97 @@
|
|||
Device tree bindings for Ethernet chip connected to TI GPMC
|
||||
|
||||
Besides being used to interface with external memory devices, the
|
||||
General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
|
||||
such as ethernet controllers to processors using the TI GPMC as a data bus.
|
||||
|
||||
Ethernet controllers connected to TI GPMC are represented as child nodes of
|
||||
the GPMC controller with an "ethernet" name.
|
||||
|
||||
All timing relevant properties as well as generic GPMC child properties are
|
||||
explained in a separate documents. Please refer to
|
||||
Documentation/devicetree/bindings/bus/ti-gpmc.txt
|
||||
|
||||
For the properties relevant to the ethernet controller connected to the GPMC
|
||||
refer to the binding documentation of the device. For example, the documentation
|
||||
for the SMSC 911x is Documentation/devicetree/bindings/net/smsc911x.txt
|
||||
|
||||
Child nodes need to specify the GPMC bus address width using the "bank-width"
|
||||
property but is possible that an ethernet controller also has a property to
|
||||
specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
|
||||
address width, it supports devices with 32-bit word registers.
|
||||
For example with an SMSC LAN911x/912x controller connected to the TI GPMC on an
|
||||
OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
|
||||
|
||||
Required properties:
|
||||
- bank-width: Address width of the device in bytes. GPMC supports 8-bit
|
||||
and 16-bit devices and so must be either 1 or 2 bytes.
|
||||
- compatible: Compatible string property for the ethernet child device.
|
||||
- gpmc,cs-on: Chip-select assertion time
|
||||
- gpmc,cs-rd-off: Chip-select de-assertion time for reads
|
||||
- gpmc,cs-wr-off: Chip-select de-assertion time for writes
|
||||
- gpmc,oe-on: Output-enable assertion time
|
||||
- gpmc,oe-off Output-enable de-assertion time
|
||||
- gpmc,we-on: Write-enable assertion time
|
||||
- gpmc,we-off: Write-enable de-assertion time
|
||||
- gpmc,access: Start cycle to first data capture (read access)
|
||||
- gpmc,rd-cycle: Total read cycle time
|
||||
- gpmc,wr-cycle: Total write cycle time
|
||||
- reg: Chip-select, base address (relative to chip-select)
|
||||
and size of the memory mapped for the device.
|
||||
Note that base address will be typically 0 as this
|
||||
is the start of the chip-select.
|
||||
|
||||
Optional properties:
|
||||
- gpmc,XXX Additional GPMC timings and settings parameters. See
|
||||
Documentation/devicetree/bindings/bus/ti-gpmc.txt
|
||||
|
||||
Example:
|
||||
|
||||
gpmc: gpmc@6e000000 {
|
||||
compatible = "ti,omap3430-gpmc";
|
||||
ti,hwmods = "gpmc";
|
||||
reg = <0x6e000000 0x1000>;
|
||||
interrupts = <20>;
|
||||
gpmc,num-cs = <8>;
|
||||
gpmc,num-waitpins = <4>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ranges = <5 0 0x2c000000 0x1000000>;
|
||||
|
||||
ethernet@5,0 {
|
||||
compatible = "smsc,lan9221", "smsc,lan9115";
|
||||
reg = <5 0 0xff>;
|
||||
bank-width = <2>;
|
||||
|
||||
gpmc,mux-add-data;
|
||||
gpmc,cs-on = <0>;
|
||||
gpmc,cs-rd-off = <186>;
|
||||
gpmc,cs-wr-off = <186>;
|
||||
gpmc,adv-on = <12>;
|
||||
gpmc,adv-rd-off = <48>;
|
||||
gpmc,adv-wr-off = <48>;
|
||||
gpmc,oe-on = <54>;
|
||||
gpmc,oe-off = <168>;
|
||||
gpmc,we-on = <54>;
|
||||
gpmc,we-off = <168>;
|
||||
gpmc,rd-cycle = <186>;
|
||||
gpmc,wr-cycle = <186>;
|
||||
gpmc,access = <114>;
|
||||
gpmc,page-burst-access = <6>;
|
||||
gpmc,bus-turnaround = <12>;
|
||||
gpmc,cycle2cycle-delay = <18>;
|
||||
gpmc,wr-data-mux-bus = <90>;
|
||||
gpmc,wr-access = <186>;
|
||||
gpmc,cycle2cycle-samecsen;
|
||||
gpmc,cycle2cycle-diffcsen;
|
||||
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <16>;
|
||||
vmmc-supply = <&vddvario>;
|
||||
vmmc_aux-supply = <&vdd33a>;
|
||||
reg-io-width = <4>;
|
||||
|
||||
smsc,save-mac-address;
|
||||
};
|
||||
};
|
||||
57
Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt
Normal file
57
Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller
|
||||
|
||||
These SoCs contain a combined Pinmux/GPIO module. Each pin may operate as
|
||||
either a GPIO in, GPIO out or as an alternate function (I2C, SPI etc).
|
||||
|
||||
Required properties:
|
||||
- compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl",
|
||||
"wm8750-pinctrl" or "wm,wm8850-pinctrl"
|
||||
- reg: Should contain the physical address of the module's registers.
|
||||
- interrupt-controller: Marks the device node as an interrupt controller.
|
||||
- #interrupt-cells: Should be two.
|
||||
- gpio-controller: Marks the device node as a GPIO controller.
|
||||
- #gpio-cells : Should be two. The first cell is the pin number and the
|
||||
second cell is used to specify optional parameters.
|
||||
bit 0 - active low
|
||||
|
||||
Please refer to ../gpio/gpio.txt for a general description of GPIO bindings.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Each pin configuration node lists the pin(s) to which it applies, and one or
|
||||
more of the mux functions to select on those pin(s), and pull-up/down
|
||||
configuration. Each subnode only affects those parameters that are explicitly
|
||||
listed. In other words, a subnode that lists only a mux function implies no
|
||||
information about any pull configuration. Similarly, a subnode that lists only
|
||||
a pull parameter implies no information about the mux function.
|
||||
|
||||
Required subnode-properties:
|
||||
- wm,pins: An array of cells. Each cell contains the ID of a pin.
|
||||
|
||||
Optional subnode-properties:
|
||||
- wm,function: Integer, containing the function to mux to the pin(s):
|
||||
0: GPIO in
|
||||
1: GPIO out
|
||||
2: alternate
|
||||
|
||||
- wm,pull: Integer, representing the pull-down/up to apply to the pin(s):
|
||||
0: none
|
||||
1: down
|
||||
2: up
|
||||
|
||||
Each of wm,function and wm,pull may contain either a single value which
|
||||
will be applied to all pins in wm,pins, or one value for each entry in
|
||||
wm,pins.
|
||||
|
||||
Example:
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "wm,wm8505-pinctrl";
|
||||
reg = <0xD8110000 0x10000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
75
Documentation/devicetree/bindings/reset/reset.txt
Normal file
75
Documentation/devicetree/bindings/reset/reset.txt
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
= Reset Signal Device Tree Bindings =
|
||||
|
||||
This binding is intended to represent the hardware reset signals present
|
||||
internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
|
||||
standalone chips are most likely better represented as GPIOs, although there
|
||||
are likely to be exceptions to this rule.
|
||||
|
||||
Hardware blocks typically receive a reset signal. This signal is generated by
|
||||
a reset provider (e.g. power management or clock module) and received by a
|
||||
reset consumer (the module being reset, or a module managing when a sub-
|
||||
ordinate module is reset). This binding exists to represent the provider and
|
||||
consumer, and provide a way to couple the two together.
|
||||
|
||||
A reset signal is represented by the phandle of the provider, plus a reset
|
||||
specifier - a list of DT cells that represents the reset signal within the
|
||||
provider. The length (number of cells) and semantics of the reset specifier
|
||||
are dictated by the binding of the reset provider, although common schemes
|
||||
are described below.
|
||||
|
||||
A word on where to place reset signal consumers in device tree: It is possible
|
||||
in hardware for a reset signal to affect multiple logically separate HW blocks
|
||||
at once. In this case, it would be unwise to represent this reset signal in
|
||||
the DT node of each affected HW block, since if activated, an unrelated block
|
||||
may be reset. Instead, reset signals should be represented in the DT node
|
||||
where it makes most sense to control it; this may be a bus node if all
|
||||
children of the bus are affected by the reset signal, or an individual HW
|
||||
block node for dedicated reset signals. The intent of this binding is to give
|
||||
appropriate software access to the reset signals in order to manage the HW,
|
||||
rather than to slavishly enumerate the reset signal that affects each HW
|
||||
block.
|
||||
|
||||
= Reset providers =
|
||||
|
||||
Required properties:
|
||||
#reset-cells: Number of cells in a reset specifier; Typically 0 for nodes
|
||||
with a single reset output and 1 for nodes with multiple
|
||||
reset outputs.
|
||||
|
||||
For example:
|
||||
|
||||
rst: reset-controller {
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
= Reset consumers =
|
||||
|
||||
Required properties:
|
||||
resets: List of phandle and reset specifier pairs, one pair
|
||||
for each reset signal that affects the device, or that the
|
||||
device manages. Note: if the reset provider specifies '0' for
|
||||
#reset-cells, then only the phandle portion of the pair will
|
||||
appear.
|
||||
|
||||
Optional properties:
|
||||
reset-names: List of reset signal name strings sorted in the same order as
|
||||
the resets property. Consumers drivers will use reset-names to
|
||||
match reset signal names with reset specifiers.
|
||||
|
||||
For example:
|
||||
|
||||
device {
|
||||
resets = <&rst 20>;
|
||||
reset-names = "reset";
|
||||
};
|
||||
|
||||
This represents a device with a single reset signal named "reset".
|
||||
|
||||
bus {
|
||||
resets = <&rst 10> <&rst 11> <&rst 12> <&rst 11>;
|
||||
reset-names = "i2s1", "i2s2", "dma", "mixer";
|
||||
};
|
||||
|
||||
This represents a bus that controls the reset signal of each of four sub-
|
||||
ordinate devices. Consider for example a bus that fails to operate unless no
|
||||
child device has reset asserted.
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
Cadence TTC - Triple Timer Counter
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "cdns,ttc".
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupts : A list of 3 interrupts; one per timer channel.
|
||||
- clocks: phandle to the source clock
|
||||
|
||||
Example:
|
||||
|
||||
ttc0: ttc0@f8001000 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = < 0 10 4 0 11 4 0 12 4 >;
|
||||
compatible = "cdns,ttc";
|
||||
reg = <0xF8001000 0x1000>;
|
||||
clocks = <&cpu_clk 3>;
|
||||
};
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
Samsung's Multi Core Timer (MCT)
|
||||
|
||||
The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
|
||||
global timer and CPU local timers. The global timer is a 64-bit free running
|
||||
up-counter and can generate 4 interrupts when the counter reaches one of the
|
||||
four preset counter values. The CPU local timers are 32-bit free running
|
||||
down-counters and generate an interrupt when the counter expires. There is
|
||||
one CPU local timer instantiated in MCT for every CPU in the system.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be "samsung,exynos4210-mct".
|
||||
(a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct.
|
||||
(b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct.
|
||||
|
||||
- reg: base address of the mct controller and length of the address space
|
||||
it occupies.
|
||||
|
||||
- interrupts: the list of interrupts generated by the controller. The following
|
||||
should be the order of the interrupts specified. The local timer interrupts
|
||||
should be specified after the four global timer interrupts have been
|
||||
specified.
|
||||
|
||||
0: Global Timer Interrupt 0
|
||||
1: Global Timer Interrupt 1
|
||||
2: Global Timer Interrupt 2
|
||||
3: Global Timer Interrupt 3
|
||||
4: Local Timer Interrupt 0
|
||||
5: Local Timer Interrupt 1
|
||||
6: ..
|
||||
7: ..
|
||||
i: Local Timer Interrupt n
|
||||
|
||||
Example 1: In this example, the system uses only the first global timer
|
||||
interrupt generated by MCT and the remaining three global timer
|
||||
interrupts are unused. Two local timer interrupts have been
|
||||
specified.
|
||||
|
||||
mct@10050000 {
|
||||
compatible = "samsung,exynos4210-mct";
|
||||
reg = <0x10050000 0x800>;
|
||||
interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
|
||||
<0 42 0>, <0 48 0>;
|
||||
};
|
||||
|
||||
Example 2: In this example, the MCT global and local timer interrupts are
|
||||
connected to two seperate interrupt controllers. Hence, an
|
||||
interrupt-map is created to map the interrupts to the respective
|
||||
interrupt controllers.
|
||||
|
||||
mct@101C0000 {
|
||||
compatible = "samsung,exynos4210-mct";
|
||||
reg = <0x101C0000 0x800>;
|
||||
interrupt-controller;
|
||||
#interrups-cells = <2>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>;
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0x0 0 &combiner 23 3>,
|
||||
<0x4 0 &gic 0 120 0>,
|
||||
<0x5 0 &gic 0 121 0>;
|
||||
};
|
||||
};
|
||||
40
Documentation/devicetree/bindings/usb/exynos-usb.txt
Normal file
40
Documentation/devicetree/bindings/usb/exynos-usb.txt
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
Samsung Exynos SoC USB controller
|
||||
|
||||
The USB devices interface with USB controllers on Exynos SOCs.
|
||||
The device node has following properties.
|
||||
|
||||
EHCI
|
||||
Required properties:
|
||||
- compatible: should be "samsung,exynos4210-ehci" for USB 2.0
|
||||
EHCI controller in host mode.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- interrupts: interrupt number to the cpu.
|
||||
|
||||
Optional properties:
|
||||
- samsung,vbus-gpio: if present, specifies the GPIO that
|
||||
needs to be pulled up for the bus to be powered.
|
||||
|
||||
Example:
|
||||
|
||||
usb@12110000 {
|
||||
compatible = "samsung,exynos4210-ehci";
|
||||
reg = <0x12110000 0x100>;
|
||||
interrupts = <0 71 0>;
|
||||
samsung,vbus-gpio = <&gpx2 6 1 3 3>;
|
||||
};
|
||||
|
||||
OHCI
|
||||
Required properties:
|
||||
- compatible: should be "samsung,exynos4210-ohci" for USB 2.0
|
||||
OHCI companion controller in host mode.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- interrupts: interrupt number to the cpu.
|
||||
|
||||
Example:
|
||||
usb@12120000 {
|
||||
compatible = "samsung,exynos4210-ohci";
|
||||
reg = <0x12120000 0x100>;
|
||||
interrupts = <0 71 0>;
|
||||
};
|
||||
|
|
@ -689,12 +689,15 @@ config ARCH_SA1100
|
|||
config ARCH_S3C24XX
|
||||
bool "Samsung S3C24XX SoCs"
|
||||
select ARCH_HAS_CPUFREQ
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select CLKDEV_LOOKUP
|
||||
select CLKSRC_MMIO
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_CLK
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
select HAVE_S3C_RTC if RTC_CLASS
|
||||
select MULTI_IRQ_HANDLER
|
||||
select NEED_MACH_GPIO_H
|
||||
select NEED_MACH_IO_H
|
||||
help
|
||||
|
|
@ -707,10 +710,11 @@ config ARCH_S3C64XX
|
|||
bool "Samsung S3C64XX"
|
||||
select ARCH_HAS_CPUFREQ
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select ARM_VIC
|
||||
select CLKDEV_LOOKUP
|
||||
select CLKSRC_MMIO
|
||||
select CPU_V6
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_CLK
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
|
|
@ -744,9 +748,11 @@ config ARCH_S5P64X0
|
|||
|
||||
config ARCH_S5PC100
|
||||
bool "Samsung S5PC100"
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select CLKDEV_LOOKUP
|
||||
select CLKSRC_MMIO
|
||||
select CPU_V7
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_CLK
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
|
|
@ -779,6 +785,7 @@ config ARCH_EXYNOS
|
|||
select ARCH_HAS_HOLES_MEMORYMODEL
|
||||
select ARCH_SPARSEMEM_ENABLE
|
||||
select CLKDEV_LOOKUP
|
||||
select COMMON_CLK
|
||||
select CPU_V7
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_CLK
|
||||
|
|
@ -1552,7 +1559,8 @@ config ARCH_NR_GPIO
|
|||
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
|
||||
default 512 if SOC_OMAP5
|
||||
default 392 if ARCH_U8500
|
||||
default 288 if ARCH_VT8500 || ARCH_SUNXI
|
||||
default 352 if ARCH_VT8500
|
||||
default 288 if ARCH_SUNXI
|
||||
default 264 if MACH_H4700
|
||||
default 0
|
||||
help
|
||||
|
|
|
|||
|
|
@ -49,7 +49,10 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
|
|||
dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
|
||||
exynos4210-smdkv310.dtb \
|
||||
exynos4210-trats.dtb \
|
||||
exynos4412-odroidx.dtb \
|
||||
exynos4412-smdk4412.dtb \
|
||||
exynos4412-origen.dtb \
|
||||
exynos5250-arndale.dtb \
|
||||
exynos5250-smdk5250.dtb \
|
||||
exynos5250-snow.dtb \
|
||||
exynos5440-ssdk5440.dtb
|
||||
|
|
|
|||
|
|
@ -24,6 +24,144 @@ i2c@12C60000 {
|
|||
samsung,i2c-max-bus-freq = <378000>;
|
||||
gpios = <&gpb3 0 2 3 0>,
|
||||
<&gpb3 1 2 3 0>;
|
||||
|
||||
max77686@09 {
|
||||
compatible = "maxim,max77686";
|
||||
reg = <0x09>;
|
||||
|
||||
voltage-regulators {
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "P1.0V_LDO_OUT1";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "P1.8V_LDO_OUT2";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: LDO3 {
|
||||
regulator-name = "P1.8V_LDO_OUT3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo7_reg: LDO7 {
|
||||
regulator-name = "P1.1V_LDO_OUT7";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo8_reg: LDO8 {
|
||||
regulator-name = "P1.0V_LDO_OUT8";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo10_reg: LDO10 {
|
||||
regulator-name = "P1.8V_LDO_OUT10";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo12_reg: LDO12 {
|
||||
regulator-name = "P3.0V_LDO_OUT12";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo14_reg: LDO14 {
|
||||
regulator-name = "P1.8V_LDO_OUT14";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo15_reg: LDO15 {
|
||||
regulator-name = "P1.0V_LDO_OUT15";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo16_reg: LDO16 {
|
||||
regulator-name = "P1.8V_LDO_OUT16";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "vdd_mif";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck2_reg: BUCK2 {
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck3_reg: BUCK3 {
|
||||
regulator-name = "vdd_int";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck4_reg: BUCK4 {
|
||||
regulator-name = "vdd_g3d";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
regulator-name = "P1.8V_BUCK_OUT5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck6_reg: BUCK6 {
|
||||
regulator-name = "P1.35V_BUCK_OUT6";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck7_reg: BUCK7 {
|
||||
regulator-name = "P2.0V_BUCK_OUT7";
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck8_reg: BUCK8 {
|
||||
regulator-name = "P2.85V_BUCK_OUT8";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@12C70000 {
|
||||
|
|
|
|||
|
|
@ -86,6 +86,8 @@ watchdog@10060000 {
|
|||
compatible = "samsung,s3c2410-wdt";
|
||||
reg = <0x10060000 0x100>;
|
||||
interrupts = <0 43 0>;
|
||||
clocks = <&clock 345>;
|
||||
clock-names = "watchdog";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -93,6 +95,8 @@ rtc@10070000 {
|
|||
compatible = "samsung,s3c6410-rtc";
|
||||
reg = <0x10070000 0x100>;
|
||||
interrupts = <0 44 0>, <0 45 0>;
|
||||
clocks = <&clock 346>;
|
||||
clock-names = "rtc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -100,6 +104,8 @@ keypad@100A0000 {
|
|||
compatible = "samsung,s5pv210-keypad";
|
||||
reg = <0x100A0000 0x100>;
|
||||
interrupts = <0 109 0>;
|
||||
clocks = <&clock 347>;
|
||||
clock-names = "keypad";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -107,6 +113,8 @@ sdhci@12510000 {
|
|||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12510000 0x100>;
|
||||
interrupts = <0 73 0>;
|
||||
clocks = <&clock 297>, <&clock 145>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -114,6 +122,8 @@ sdhci@12520000 {
|
|||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12520000 0x100>;
|
||||
interrupts = <0 74 0>;
|
||||
clocks = <&clock 298>, <&clock 146>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -121,6 +131,8 @@ sdhci@12530000 {
|
|||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12530000 0x100>;
|
||||
interrupts = <0 75 0>;
|
||||
clocks = <&clock 299>, <&clock 147>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -128,6 +140,16 @@ sdhci@12540000 {
|
|||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12540000 0x100>;
|
||||
interrupts = <0 76 0>;
|
||||
clocks = <&clock 300>, <&clock 148>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mfc: codec@13400000 {
|
||||
compatible = "samsung,mfc-v5";
|
||||
reg = <0x13400000 0x10000>;
|
||||
interrupts = <0 94 0>;
|
||||
samsung,power-domain = <&pd_mfc>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -135,6 +157,8 @@ serial@13800000 {
|
|||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13800000 0x100>;
|
||||
interrupts = <0 52 0>;
|
||||
clocks = <&clock 312>, <&clock 151>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -142,6 +166,8 @@ serial@13810000 {
|
|||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13810000 0x100>;
|
||||
interrupts = <0 53 0>;
|
||||
clocks = <&clock 313>, <&clock 152>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -149,6 +175,8 @@ serial@13820000 {
|
|||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13820000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
clocks = <&clock 314>, <&clock 153>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -156,6 +184,8 @@ serial@13830000 {
|
|||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13830000 0x100>;
|
||||
interrupts = <0 55 0>;
|
||||
clocks = <&clock 315>, <&clock 154>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -165,6 +195,8 @@ i2c_0: i2c@13860000 {
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13860000 0x100>;
|
||||
interrupts = <0 58 0>;
|
||||
clocks = <&clock 317>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -174,6 +206,8 @@ i2c_1: i2c@13870000 {
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13870000 0x100>;
|
||||
interrupts = <0 59 0>;
|
||||
clocks = <&clock 318>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -183,6 +217,8 @@ i2c_2: i2c@13880000 {
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13880000 0x100>;
|
||||
interrupts = <0 60 0>;
|
||||
clocks = <&clock 319>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -192,6 +228,8 @@ i2c_3: i2c@13890000 {
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13890000 0x100>;
|
||||
interrupts = <0 61 0>;
|
||||
clocks = <&clock 320>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -201,6 +239,8 @@ i2c_4: i2c@138A0000 {
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x138A0000 0x100>;
|
||||
interrupts = <0 62 0>;
|
||||
clocks = <&clock 321>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -210,6 +250,8 @@ i2c_5: i2c@138B0000 {
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x138B0000 0x100>;
|
||||
interrupts = <0 63 0>;
|
||||
clocks = <&clock 322>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -219,6 +261,8 @@ i2c_6: i2c@138C0000 {
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x138C0000 0x100>;
|
||||
interrupts = <0 64 0>;
|
||||
clocks = <&clock 323>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -228,6 +272,8 @@ i2c_7: i2c@138D0000 {
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x138D0000 0x100>;
|
||||
interrupts = <0 65 0>;
|
||||
clocks = <&clock 324>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -239,6 +285,8 @@ spi_0: spi@13920000 {
|
|||
rx-dma-channel = <&pdma0 6>; /* preliminary */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 327>, <&clock 159>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -250,6 +298,8 @@ spi_1: spi@13930000 {
|
|||
rx-dma-channel = <&pdma1 6>; /* preliminary */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 328>, <&clock 160>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -261,6 +311,8 @@ spi_2: spi@13940000 {
|
|||
rx-dma-channel = <&pdma0 8>; /* preliminary */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 329>, <&clock 161>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -275,6 +327,8 @@ pdma0: pdma@12680000 {
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x12680000 0x1000>;
|
||||
interrupts = <0 35 0>;
|
||||
clocks = <&clock 292>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
|
|
@ -284,6 +338,8 @@ pdma1: pdma@12690000 {
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x12690000 0x1000>;
|
||||
interrupts = <0 36 0>;
|
||||
clocks = <&clock 293>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
|
|
@ -293,6 +349,8 @@ mdma1: mdma@12850000 {
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x12850000 0x1000>;
|
||||
interrupts = <0 34 0>;
|
||||
clocks = <&clock 279>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <1>;
|
||||
|
|
|
|||
|
|
@ -57,6 +57,12 @@ sdhci@12510000 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
codec@13400000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -121,4 +127,16 @@ status {
|
|||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -43,6 +43,12 @@ sdhci@12530000 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
codec@13400000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -189,4 +195,16 @@ partition@40000 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -289,4 +289,16 @@ safe2_sreg: ESAFEOUT2 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -47,6 +47,42 @@ combiner:interrupt-controller@10440000 {
|
|||
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
|
||||
};
|
||||
|
||||
mct@10050000 {
|
||||
compatible = "samsung,exynos4210-mct";
|
||||
reg = <0x10050000 0x800>;
|
||||
interrupt-controller;
|
||||
#interrups-cells = <2>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>;
|
||||
clocks = <&clock 3>, <&clock 344>;
|
||||
clock-names = "fin_pll", "mct";
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0x0 0 &gic 0 57 0>,
|
||||
<0x1 0 &gic 0 69 0>,
|
||||
<0x2 0 &combiner 12 6>,
|
||||
<0x3 0 &combiner 12 7>,
|
||||
<0x4 0 &gic 0 42 0>,
|
||||
<0x5 0 &gic 0 48 0>;
|
||||
};
|
||||
};
|
||||
|
||||
clock: clock-controller@0x10030000 {
|
||||
compatible = "samsung,exynos4210-clock";
|
||||
reg = <0x10030000 0x20000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupt-parent = <&combiner>;
|
||||
interrupts = <2 2>, <3 2>;
|
||||
};
|
||||
|
||||
pinctrl_0: pinctrl@11400000 {
|
||||
compatible = "samsung,exynos4210-pinctrl";
|
||||
reg = <0x11400000 0x1000>;
|
||||
|
|
|
|||
|
|
@ -25,4 +25,26 @@ / {
|
|||
gic:interrupt-controller@10490000 {
|
||||
cpu-offset = <0x8000>;
|
||||
};
|
||||
|
||||
mct@10050000 {
|
||||
compatible = "samsung,exynos4412-mct";
|
||||
reg = <0x10050000 0x800>;
|
||||
interrupt-controller;
|
||||
#interrups-cells = <2>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>;
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0x0 0 &gic 0 57 0>,
|
||||
<0x1 0 &combiner 12 5>,
|
||||
<0x2 0 &combiner 12 6>,
|
||||
<0x3 0 &combiner 12 7>,
|
||||
<0x4 0 &gic 1 12 0>,
|
||||
<0x5 0 &gic 1 12 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
111
arch/arm/boot/dts/exynos4412-odroidx.dts
Normal file
111
arch/arm/boot/dts/exynos4412-odroidx.dts
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/*
|
||||
* Hardkernel's Exynos4412 based ODROID-X board device tree source
|
||||
*
|
||||
* Copyright (c) 2012 Dongjin Kim <tobetter@gmail.com>
|
||||
*
|
||||
* Device tree source file for Hardkernel's ODROID-X board which is based on
|
||||
* Samsung's Exynos4412 SoC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "exynos4412.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Hardkernel ODROID-X board based on Exynos4412";
|
||||
compatible = "hardkernel,odroid-x", "samsung,exynos4412";
|
||||
|
||||
memory {
|
||||
reg = <0x40000000 0x40000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led1 {
|
||||
label = "led1:heart";
|
||||
gpios = <&gpc1 0 1>;
|
||||
default-state = "on";
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
led2 {
|
||||
label = "led2:mmc0";
|
||||
gpios = <&gpc1 2 1>;
|
||||
default-state = "on";
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
};
|
||||
|
||||
mshc@12550000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
broken-cd;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
regulator_p3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "p3v3_en";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpa1 1 1>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
rtc@10070000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13810000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13820000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13830000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
432
arch/arm/boot/dts/exynos4412-origen.dts
Normal file
432
arch/arm/boot/dts/exynos4412-origen.dts
Normal file
|
|
@ -0,0 +1,432 @@
|
|||
/*
|
||||
* Insignal's Exynos4412 based Origen board device tree source
|
||||
*
|
||||
* Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Device tree source file for Insignal's Origen board which is based on
|
||||
* Samsung's Exynos4412 SoC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "exynos4412.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Insignal Origen evaluation board based on Exynos4412";
|
||||
compatible = "insignal,origen4412", "samsung,exynos4412";
|
||||
|
||||
memory {
|
||||
reg = <0x40000000 0x40000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs ="console=ttySAC2,115200";
|
||||
};
|
||||
|
||||
mmc_reg: voltage-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VMEM_VDD_2.8V";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
gpio = <&gpx1 1 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
|
||||
pinctrl-names = "default";
|
||||
vmmc-supply = <&mmc_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mshc@12550000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
broken-cd;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
codec@13400000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13810000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13820000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13830000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@13860000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <20000>;
|
||||
pinctrl-0 = <&i2c0_bus>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
s5m8767_pmic@66 {
|
||||
compatible = "samsung,s5m8767-pmic";
|
||||
reg = <0x66>;
|
||||
|
||||
s5m8767,pmic-buck-default-dvs-idx = <3>;
|
||||
|
||||
s5m8767,pmic-buck-dvs-gpios = <&gpx2 3 0>,
|
||||
<&gpx2 4 0>,
|
||||
<&gpx2 5 0>;
|
||||
|
||||
s5m8767,pmic-buck-ds-gpios = <&gpm3 5 0>,
|
||||
<&gpm3 6 0>,
|
||||
<&gpm3 7 0>;
|
||||
|
||||
s5m8767,pmic-buck2-dvs-voltage = <1250000>, <1200000>,
|
||||
<1200000>, <1200000>,
|
||||
<1200000>, <1200000>,
|
||||
<1200000>, <1200000>;
|
||||
|
||||
s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>,
|
||||
<1100000>, <1100000>,
|
||||
<1100000>, <1100000>,
|
||||
<1100000>, <1100000>;
|
||||
|
||||
s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>,
|
||||
<1200000>, <1200000>,
|
||||
<1200000>, <1200000>,
|
||||
<1200000>, <1200000>;
|
||||
|
||||
regulators {
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "VDD_ALIVE";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "VDDQ_M12";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo3_reg: LDO3 {
|
||||
regulator-name = "VDDIOAP_18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo4_reg: LDO4 {
|
||||
regulator-name = "VDDQ_PRE";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo5_reg: LDO5 {
|
||||
regulator-name = "VDD18_2M";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo6_reg: LDO6 {
|
||||
regulator-name = "VDD10_MPLL";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo7_reg: LDO7 {
|
||||
regulator-name = "VDD10_XPLL";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo8_reg: LDO8 {
|
||||
regulator-name = "VDD10_MIPI";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo9_reg: LDO9 {
|
||||
regulator-name = "VDD33_LCD";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo10_reg: LDO10 {
|
||||
regulator-name = "VDD18_MIPI";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo11_reg: LDO11 {
|
||||
regulator-name = "VDD18_ABB1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo12_reg: LDO12 {
|
||||
regulator-name = "VDD33_UOTG";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo13_reg: LDO13 {
|
||||
regulator-name = "VDDIOPERI_18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo14_reg: LDO14 {
|
||||
regulator-name = "VDD18_ABB02";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo15_reg: LDO15 {
|
||||
regulator-name = "VDD10_USH";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo16_reg: LDO16 {
|
||||
regulator-name = "VDD18_HSIC";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo17_reg: LDO17 {
|
||||
regulator-name = "VDDIOAP_MMC012_28";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo18_reg: LDO18 {
|
||||
regulator-name = "VDDIOPERI_28";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo19_reg: LDO19 {
|
||||
regulator-name = "DVDD25";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo20_reg: LDO20 {
|
||||
regulator-name = "VDD28_CAM";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo21_reg: LDO21 {
|
||||
regulator-name = "VDD28_AF";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo22_reg: LDO22 {
|
||||
regulator-name = "VDDA28_2M";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo23_reg: LDO23 {
|
||||
regulator-name = "VDD28_TF";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo24_reg: LDO24 {
|
||||
regulator-name = "VDD33_A31";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo25_reg: LDO25 {
|
||||
regulator-name = "VDD18_CAM";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo26_reg: LDO26 {
|
||||
regulator-name = "VDD18_A31";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo27_reg: LDO27 {
|
||||
regulator-name = "GPS_1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo28_reg: LDO28 {
|
||||
regulator-name = "DVDD12";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "vdd_mif";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck2_reg: BUCK2 {
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck3_reg: BUCK3 {
|
||||
regulator-name = "vdd_int";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck4_reg: BUCK4 {
|
||||
regulator-name = "vdd_g3d";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
regulator-name = "vdd_m12";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck6_reg: BUCK6 {
|
||||
regulator-name = "vdd12_5m";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck9_reg: BUCK9 {
|
||||
regulator-name = "vddf28_emmc";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -27,6 +27,19 @@ chosen {
|
|||
bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
|
||||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
codec@13400000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -42,4 +55,16 @@ serial@13820000 {
|
|||
serial@13830000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -25,4 +25,30 @@ / {
|
|||
gic:interrupt-controller@10490000 {
|
||||
cpu-offset = <0x4000>;
|
||||
};
|
||||
|
||||
mct@10050000 {
|
||||
compatible = "samsung,exynos4412-mct";
|
||||
reg = <0x10050000 0x800>;
|
||||
interrupt-controller;
|
||||
#interrups-cells = <2>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>, <6 0>, <7 0>;
|
||||
clocks = <&clock 3>, <&clock 344>;
|
||||
clock-names = "fin_pll", "mct";
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0x0 0 &gic 0 57 0>,
|
||||
<0x1 0 &combiner 12 5>,
|
||||
<0x2 0 &combiner 12 6>,
|
||||
<0x3 0 &combiner 12 7>,
|
||||
<0x4 0 &gic 1 12 0>,
|
||||
<0x5 0 &gic 1 12 0>,
|
||||
<0x6 0 &gic 1 12 0>,
|
||||
<0x7 0 &gic 1 12 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -36,6 +36,12 @@ combiner:interrupt-controller@10440000 {
|
|||
<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
|
||||
};
|
||||
|
||||
clock: clock-controller@0x10030000 {
|
||||
compatible = "samsung,exynos4412-clock";
|
||||
reg = <0x10030000 0x20000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pinctrl_0: pinctrl@11400000 {
|
||||
compatible = "samsung,exynos4x12-pinctrl";
|
||||
reg = <0x11400000 0x1000>;
|
||||
|
|
|
|||
129
arch/arm/boot/dts/exynos5250-arndale.dts
Normal file
129
arch/arm/boot/dts/exynos5250-arndale.dts
Normal file
|
|
@ -0,0 +1,129 @@
|
|||
/*
|
||||
* Samsung's Exynos5250 based Arndale board device tree source
|
||||
*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "exynos5250.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Insignal Arndale evaluation board based on EXYNOS5250";
|
||||
compatible = "insignal,arndale", "samsung,exynos5250";
|
||||
|
||||
memory {
|
||||
reg = <0x40000000 0x80000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttySAC2,115200";
|
||||
};
|
||||
|
||||
i2c@12C60000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12C70000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12C80000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12C90000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12CA0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12CB0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12CC0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12CD0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@121D0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dwmmc_0: dwmmc0@12200000 {
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
broken-cd;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <8>;
|
||||
gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
|
||||
<&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
|
||||
<&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>,
|
||||
<&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
|
||||
<&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>;
|
||||
};
|
||||
};
|
||||
|
||||
dwmmc_1: dwmmc1@12210000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dwmmc_2: dwmmc2@12220000 {
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
|
||||
gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
|
||||
<&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
|
||||
<&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
|
||||
};
|
||||
};
|
||||
|
||||
dwmmc_3: dwmmc3@12230000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi_0: spi@12d20000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi_1: spi@12d30000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi_2: spi@12d40000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -231,4 +231,24 @@ sound {
|
|||
samsung,i2s-controller = <&i2s0>;
|
||||
samsung,audio-codec = <&wm8994>;
|
||||
};
|
||||
|
||||
usb@12110000 {
|
||||
samsung,vbus-gpio = <&gpx2 6 1 3 3>;
|
||||
};
|
||||
|
||||
dp-controller {
|
||||
samsung,color-space = <0>;
|
||||
samsung,dynamic-range = <0>;
|
||||
samsung,ycbcr-coeff = <0>;
|
||||
samsung,color-depth = <1>;
|
||||
samsung,link-rate = <0x0a>;
|
||||
samsung,lane-count = <4>;
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -40,4 +40,15 @@ slot@0 {
|
|||
<&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@12110000 {
|
||||
samsung,vbus-gpio = <&gpx1 1 1 3 3>;
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -46,6 +46,22 @@ aliases {
|
|||
i2c8 = &i2c_8;
|
||||
};
|
||||
|
||||
pd_gsc: gsc-power-domain@0x10044000 {
|
||||
compatible = "samsung,exynos4210-pd";
|
||||
reg = <0x10044000 0x20>;
|
||||
};
|
||||
|
||||
pd_mfc: mfc-power-domain@0x10044040 {
|
||||
compatible = "samsung,exynos4210-pd";
|
||||
reg = <0x10044040 0x20>;
|
||||
};
|
||||
|
||||
clock: clock-controller@0x10010000 {
|
||||
compatible = "samsung,exynos5250-clock";
|
||||
reg = <0x10010000 0x30000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gic:interrupt-controller@10481000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
@ -69,58 +85,106 @@ combiner:interrupt-controller@10440000 {
|
|||
<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
|
||||
};
|
||||
|
||||
mct@101C0000 {
|
||||
compatible = "samsung,exynos4210-mct";
|
||||
reg = <0x101C0000 0x800>;
|
||||
interrupt-controller;
|
||||
#interrups-cells = <2>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>;
|
||||
clocks = <&clock 1>, <&clock 335>;
|
||||
clock-names = "fin_pll", "mct";
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0x0 0 &combiner 23 3>,
|
||||
<0x1 0 &combiner 23 4>,
|
||||
<0x2 0 &combiner 25 2>,
|
||||
<0x3 0 &combiner 25 3>,
|
||||
<0x4 0 &gic 0 120 0>,
|
||||
<0x5 0 &gic 0 121 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a15-pmu";
|
||||
interrupt-parent = <&combiner>;
|
||||
interrupts = <1 2>, <22 4>;
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "samsung,s3c2410-wdt";
|
||||
reg = <0x101D0000 0x100>;
|
||||
interrupts = <0 42 0>;
|
||||
clocks = <&clock 336>;
|
||||
clock-names = "watchdog";
|
||||
};
|
||||
|
||||
codec@11000000 {
|
||||
compatible = "samsung,mfc-v6";
|
||||
reg = <0x11000000 0x10000>;
|
||||
interrupts = <0 96 0>;
|
||||
samsung,power-domain = <&pd_mfc>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
compatible = "samsung,s3c6410-rtc";
|
||||
reg = <0x101E0000 0x100>;
|
||||
interrupts = <0 43 0>, <0 44 0>;
|
||||
clocks = <&clock 337>;
|
||||
clock-names = "rtc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu@10060000 {
|
||||
compatible = "samsung,exynos5250-tmu";
|
||||
reg = <0x10060000 0x100>;
|
||||
interrupts = <0 65 0>;
|
||||
clocks = <&clock 338>;
|
||||
clock-names = "tmu_apbif";
|
||||
};
|
||||
|
||||
serial@12C00000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C00000 0x100>;
|
||||
interrupts = <0 51 0>;
|
||||
clocks = <&clock 289>, <&clock 146>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C10000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C10000 0x100>;
|
||||
interrupts = <0 52 0>;
|
||||
clocks = <&clock 290>, <&clock 147>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C20000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C20000 0x100>;
|
||||
interrupts = <0 53 0>;
|
||||
clocks = <&clock 291>, <&clock 148>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C30000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C30000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
clocks = <&clock 292>, <&clock 149>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
sata@122F0000 {
|
||||
compatible = "samsung,exynos5-sata-ahci";
|
||||
reg = <0x122F0000 0x1ff>;
|
||||
interrupts = <0 115 0>;
|
||||
clocks = <&clock 277>, <&clock 143>;
|
||||
clock-names = "sata", "sclk_sata";
|
||||
};
|
||||
|
||||
sata-phy@12170000 {
|
||||
|
|
@ -134,6 +198,8 @@ i2c_0: i2c@12C60000 {
|
|||
interrupts = <0 56 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 294>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_1: i2c@12C70000 {
|
||||
|
|
@ -142,6 +208,8 @@ i2c_1: i2c@12C70000 {
|
|||
interrupts = <0 57 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 295>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_2: i2c@12C80000 {
|
||||
|
|
@ -150,6 +218,8 @@ i2c_2: i2c@12C80000 {
|
|||
interrupts = <0 58 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 296>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_3: i2c@12C90000 {
|
||||
|
|
@ -158,6 +228,8 @@ i2c_3: i2c@12C90000 {
|
|||
interrupts = <0 59 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 297>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_4: i2c@12CA0000 {
|
||||
|
|
@ -166,6 +238,8 @@ i2c_4: i2c@12CA0000 {
|
|||
interrupts = <0 60 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 298>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_5: i2c@12CB0000 {
|
||||
|
|
@ -174,6 +248,8 @@ i2c_5: i2c@12CB0000 {
|
|||
interrupts = <0 61 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 299>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_6: i2c@12CC0000 {
|
||||
|
|
@ -182,6 +258,8 @@ i2c_6: i2c@12CC0000 {
|
|||
interrupts = <0 62 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 300>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_7: i2c@12CD0000 {
|
||||
|
|
@ -190,6 +268,8 @@ i2c_7: i2c@12CD0000 {
|
|||
interrupts = <0 63 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 301>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_8: i2c@12CE0000 {
|
||||
|
|
@ -198,6 +278,8 @@ i2c_8: i2c@12CE0000 {
|
|||
interrupts = <0 64 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 302>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c@121D0000 {
|
||||
|
|
@ -205,6 +287,8 @@ i2c@121D0000 {
|
|||
reg = <0x121D0000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 288>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
spi_0: spi@12d20000 {
|
||||
|
|
@ -216,6 +300,8 @@ spi_0: spi@12d20000 {
|
|||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 304>, <&clock 154>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
};
|
||||
|
||||
spi_1: spi@12d30000 {
|
||||
|
|
@ -227,6 +313,8 @@ spi_1: spi@12d30000 {
|
|||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 305>, <&clock 155>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
};
|
||||
|
||||
spi_2: spi@12d40000 {
|
||||
|
|
@ -238,6 +326,8 @@ spi_2: spi@12d40000 {
|
|||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 306>, <&clock 156>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
};
|
||||
|
||||
dwmmc_0: dwmmc0@12200000 {
|
||||
|
|
@ -246,6 +336,8 @@ dwmmc_0: dwmmc0@12200000 {
|
|||
interrupts = <0 75 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 280>, <&clock 139>;
|
||||
clock-names = "biu", "ciu";
|
||||
};
|
||||
|
||||
dwmmc_1: dwmmc1@12210000 {
|
||||
|
|
@ -254,6 +346,8 @@ dwmmc_1: dwmmc1@12210000 {
|
|||
interrupts = <0 76 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 281>, <&clock 140>;
|
||||
clock-names = "biu", "ciu";
|
||||
};
|
||||
|
||||
dwmmc_2: dwmmc2@12220000 {
|
||||
|
|
@ -262,6 +356,8 @@ dwmmc_2: dwmmc2@12220000 {
|
|||
interrupts = <0 77 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 282>, <&clock 141>;
|
||||
clock-names = "biu", "ciu";
|
||||
};
|
||||
|
||||
dwmmc_3: dwmmc3@12230000 {
|
||||
|
|
@ -270,6 +366,8 @@ dwmmc_3: dwmmc3@12230000 {
|
|||
interrupts = <0 78 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 283>, <&clock 142>;
|
||||
clock-names = "biu", "ciu";
|
||||
};
|
||||
|
||||
i2s0: i2s@03830000 {
|
||||
|
|
@ -301,6 +399,18 @@ i2s2: i2s@12D70000 {
|
|||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
usb@12110000 {
|
||||
compatible = "samsung,exynos4210-ehci";
|
||||
reg = <0x12110000 0x100>;
|
||||
interrupts = <0 71 0>;
|
||||
};
|
||||
|
||||
usb@12120000 {
|
||||
compatible = "samsung,exynos4210-ohci";
|
||||
reg = <0x12120000 0x100>;
|
||||
interrupts = <0 71 0>;
|
||||
};
|
||||
|
||||
amba {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -312,6 +422,8 @@ pdma0: pdma@121A0000 {
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121A0000 0x1000>;
|
||||
interrupts = <0 34 0>;
|
||||
clocks = <&clock 275>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
|
|
@ -321,6 +433,8 @@ pdma1: pdma@121B0000 {
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121B0000 0x1000>;
|
||||
interrupts = <0 35 0>;
|
||||
clocks = <&clock 276>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
|
|
@ -330,6 +444,8 @@ mdma0: mdma@10800000 {
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x10800000 0x1000>;
|
||||
interrupts = <0 33 0>;
|
||||
clocks = <&clock 271>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <1>;
|
||||
|
|
@ -339,6 +455,8 @@ mdma1: mdma@11C10000 {
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x11C10000 0x1000>;
|
||||
interrupts = <0 124 0>;
|
||||
clocks = <&clock 271>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <1>;
|
||||
|
|
@ -592,34 +710,51 @@ gpz: gpio-controller@03860000 {
|
|||
};
|
||||
};
|
||||
|
||||
|
||||
gsc_0: gsc@0x13e00000 {
|
||||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e00000 0x1000>;
|
||||
interrupts = <0 85 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock 256>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
gsc_1: gsc@0x13e10000 {
|
||||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e10000 0x1000>;
|
||||
interrupts = <0 86 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock 257>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
gsc_2: gsc@0x13e20000 {
|
||||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e20000 0x1000>;
|
||||
interrupts = <0 87 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock 258>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
gsc_3: gsc@0x13e30000 {
|
||||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e30000 0x1000>;
|
||||
interrupts = <0 88 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock 259>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
hdmi {
|
||||
compatible = "samsung,exynos5-hdmi";
|
||||
reg = <0x14530000 0x70000>;
|
||||
interrupts = <0 95 0>;
|
||||
clocks = <&clock 333>, <&clock 136>, <&clock 137>,
|
||||
<&clock 333>, <&clock 333>;
|
||||
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
|
||||
"sclk_hdmiphy", "hdmiphy";
|
||||
};
|
||||
|
||||
mixer {
|
||||
|
|
@ -627,4 +762,18 @@ mixer {
|
|||
reg = <0x14450000 0x10000>;
|
||||
interrupts = <0 94 0>;
|
||||
};
|
||||
|
||||
dp-controller {
|
||||
compatible = "samsung,exynos5-dp";
|
||||
reg = <0x145b0000 0x1000>;
|
||||
interrupts = <10 3>;
|
||||
interrupt-parent = <&combiner>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dptx-phy {
|
||||
reg = <0x10040720>;
|
||||
samsung,enable-mask = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -28,19 +28,10 @@ spi {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@F0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@100000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc {
|
||||
status = "disabled";
|
||||
fixed-rate-clocks {
|
||||
xtal {
|
||||
compatible = "samsung,clock-xtal";
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -16,6 +16,12 @@ / {
|
|||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
clock: clock-controller@0x160000 {
|
||||
compatible = "samsung,exynos5440-clock";
|
||||
reg = <0x160000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gic:interrupt-controller@2E0000 {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
@ -24,55 +30,51 @@ gic:interrupt-controller@2E0000 {
|
|||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a15";
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 13 0xf08>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a15";
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 14 0xf08>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
reg = <1>;
|
||||
};
|
||||
cpu@2 {
|
||||
compatible = "arm,cortex-a15";
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 14 0xf08>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
reg = <2>;
|
||||
};
|
||||
cpu@3 {
|
||||
compatible = "arm,cortex-a15";
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 14 0xf08>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
common {
|
||||
compatible = "samsung,exynos5440";
|
||||
|
||||
timer {
|
||||
compatible = "arm,cortex-a15-timer",
|
||||
"arm,armv7-timer";
|
||||
interrupts = <1 13 0xf08>,
|
||||
<1 14 0xf08>,
|
||||
<1 11 0xf08>,
|
||||
<1 10 0xf08>;
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
serial@B0000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0xB0000 0x1000>;
|
||||
interrupts = <0 2 0>;
|
||||
clocks = <&clock 21>, <&clock 21>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@C0000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0xC0000 0x1000>;
|
||||
interrupts = <0 3 0>;
|
||||
clocks = <&clock 21>, <&clock 21>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
spi {
|
||||
|
|
@ -83,6 +85,8 @@ spi {
|
|||
rx-dma-channel = <&pdma0 4>; /* preliminary */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 21>, <&clock 16>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
};
|
||||
|
||||
pinctrl {
|
||||
|
|
@ -110,25 +114,31 @@ uart1: uart1 {
|
|||
};
|
||||
|
||||
i2c@F0000 {
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
compatible = "samsung,exynos5440-i2c";
|
||||
reg = <0xF0000 0x1000>;
|
||||
interrupts = <0 5 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c@100000 {
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
compatible = "samsung,exynos5440-i2c";
|
||||
reg = <0x100000 0x1000>;
|
||||
interrupts = <0 6 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "samsung,s3c2410-wdt";
|
||||
reg = <0x110000 0x1000>;
|
||||
interrupts = <0 1 0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "watchdog";
|
||||
};
|
||||
|
||||
amba {
|
||||
|
|
@ -142,6 +152,8 @@ pdma0: pdma@121A0000 {
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x120000 0x1000>;
|
||||
interrupts = <0 34 0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
|
|
@ -151,6 +163,8 @@ pdma1: pdma@121B0000 {
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121000 0x1000>;
|
||||
interrupts = <0 35 0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
|
|
@ -161,5 +175,8 @@ rtc {
|
|||
compatible = "samsung,s3c6410-rtc";
|
||||
reg = <0x130000 0x1000>;
|
||||
interrupts = <0 17 0>, <0 16 0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "rtc";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -38,6 +38,57 @@ mmc {
|
|||
};
|
||||
};
|
||||
|
||||
/* HS USB Port 2 RESET */
|
||||
hsusb2_reset: hsusb2_reset_reg {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "hsusb2_reset";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio5 19 0>; /* gpio_147 */
|
||||
startup-delay-us = <70000>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
/* HS USB Port 2 Power */
|
||||
hsusb2_power: hsusb2_power_reg {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "hsusb2_vbus";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&twl_gpio 18 0>; /* GPIO LEDA */
|
||||
startup-delay-us = <70000>;
|
||||
};
|
||||
|
||||
/* HS USB Host PHY on PORT 2 */
|
||||
hsusb2_phy: hsusb2_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
reset-supply = <&hsusb2_reset>;
|
||||
vcc-supply = <&hsusb2_power>;
|
||||
};
|
||||
};
|
||||
|
||||
&omap3_pmx_core {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <
|
||||
&hsusbb2_pins
|
||||
>;
|
||||
|
||||
hsusbb2_pins: pinmux_hsusbb2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x5c0 0x3 /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */
|
||||
0x5c2 0x3 /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */
|
||||
0x5c4 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */
|
||||
0x5c6 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */
|
||||
0x5c8 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */
|
||||
0x5cA 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */
|
||||
0x1a4 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */
|
||||
0x1a6 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */
|
||||
0x1a8 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */
|
||||
0x1aa 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */
|
||||
0x1ac 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */
|
||||
0x1ae 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
|
|
@ -65,3 +116,23 @@ &mmc2 {
|
|||
&mmc3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usbhshost {
|
||||
port2-mode = "ehci-phy";
|
||||
};
|
||||
|
||||
&usbhsehci {
|
||||
phys = <0 &hsusb2_phy>;
|
||||
};
|
||||
|
||||
&twl_gpio {
|
||||
ti,use-leds;
|
||||
/* pullups: BIT(1) */
|
||||
ti,pullups = <0x000002>;
|
||||
/*
|
||||
* pulldowns:
|
||||
* BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
|
||||
* BIT(15), BIT(16), BIT(17)
|
||||
*/
|
||||
ti,pulldowns = <0x03a1c4>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -397,5 +397,36 @@ timer12: timer@48304000 {
|
|||
ti,timer-alwon;
|
||||
ti,timer-secure;
|
||||
};
|
||||
|
||||
usbhstll: usbhstll@48062000 {
|
||||
compatible = "ti,usbhs-tll";
|
||||
reg = <0x48062000 0x1000>;
|
||||
interrupts = <78>;
|
||||
ti,hwmods = "usb_tll_hs";
|
||||
};
|
||||
|
||||
usbhshost: usbhshost@48064000 {
|
||||
compatible = "ti,usbhs-host";
|
||||
reg = <0x48064000 0x400>;
|
||||
ti,hwmods = "usb_host_hs";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
usbhsohci: ohci@48064400 {
|
||||
compatible = "ti,ohci-omap3", "usb-ohci";
|
||||
reg = <0x48064400 0x400>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <76>;
|
||||
};
|
||||
|
||||
usbhsehci: ehci@48064800 {
|
||||
compatible = "ti,ehci-omap", "usb-ehci";
|
||||
reg = <0x48064800 0x400>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <77>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -529,5 +529,35 @@ timer11: timer@48088000 {
|
|||
ti,hwmods = "timer11";
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
usbhstll: usbhstll@4a062000 {
|
||||
compatible = "ti,usbhs-tll";
|
||||
reg = <0x4a062000 0x1000>;
|
||||
interrupts = <0 78 0x4>;
|
||||
ti,hwmods = "usb_tll_hs";
|
||||
};
|
||||
|
||||
usbhshost: usbhshost@4a064000 {
|
||||
compatible = "ti,usbhs-host";
|
||||
reg = <0x4a064000 0x800>;
|
||||
ti,hwmods = "usb_host_hs";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
usbhsohci: ohci@4a064800 {
|
||||
compatible = "ti,ohci-omap3", "usb-ohci";
|
||||
reg = <0x4a064800 0x400>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 76 0x4>;
|
||||
};
|
||||
|
||||
usbhsehci: ehci@4a064c00 {
|
||||
compatible = "ti,ehci-omap", "usb-ehci";
|
||||
reg = <0x4a064c00 0x400>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 77 0x4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@ memory {
|
|||
|
||||
serial@70006300 {
|
||||
status = "okay";
|
||||
clock-frequency = <408000000>;
|
||||
};
|
||||
|
||||
pmc {
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@ memory {
|
|||
|
||||
serial@70006300 {
|
||||
status = "okay";
|
||||
clock-frequency = <408000000>;
|
||||
};
|
||||
|
||||
pmc {
|
||||
|
|
|
|||
|
|
@ -24,10 +24,11 @@ timer@60005000 {
|
|||
0 42 0x04
|
||||
0 121 0x04
|
||||
0 122 0x04>;
|
||||
clocks = <&tegra_car 5>;
|
||||
};
|
||||
|
||||
tegra_car: clock {
|
||||
compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
|
||||
compatible = "nvidia,tegra114-car";
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -66,6 +67,7 @@ serial@70006000 {
|
|||
reg-shift = <2>;
|
||||
interrupts = <0 36 0x04>;
|
||||
status = "disabled";
|
||||
clocks = <&tegra_car 6>;
|
||||
};
|
||||
|
||||
serial@70006040 {
|
||||
|
|
@ -74,6 +76,7 @@ serial@70006040 {
|
|||
reg-shift = <2>;
|
||||
interrupts = <0 37 0x04>;
|
||||
status = "disabled";
|
||||
clocks = <&tegra_car 192>;
|
||||
};
|
||||
|
||||
serial@70006200 {
|
||||
|
|
@ -82,6 +85,7 @@ serial@70006200 {
|
|||
reg-shift = <2>;
|
||||
interrupts = <0 46 0x04>;
|
||||
status = "disabled";
|
||||
clocks = <&tegra_car 55>;
|
||||
};
|
||||
|
||||
serial@70006300 {
|
||||
|
|
@ -90,12 +94,14 @@ serial@70006300 {
|
|||
reg-shift = <2>;
|
||||
interrupts = <0 90 0x04>;
|
||||
status = "disabled";
|
||||
clocks = <&tegra_car 65>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
|
||||
reg = <0x7000e000 0x100>;
|
||||
interrupts = <0 2 0x04>;
|
||||
clocks = <&tegra_car 4>;
|
||||
};
|
||||
|
||||
pmc {
|
||||
|
|
|
|||
|
|
@ -25,11 +25,13 @@ intc: interrupt-controller@d8140000 {
|
|||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio: gpio-controller@d8110000 {
|
||||
compatible = "via,vt8500-gpio";
|
||||
gpio-controller;
|
||||
pinctrl: pinctrl@d8110000 {
|
||||
compatible = "via,vt8500-pinctrl";
|
||||
reg = <0xd8110000 0x10000>;
|
||||
#gpio-cells = <3>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
pmc@d8130000 {
|
||||
|
|
|
|||
|
|
@ -40,11 +40,13 @@ intc1: interrupt-controller@d8150000 {
|
|||
interrupts = <56 57 58 59 60 61 62 63>;
|
||||
};
|
||||
|
||||
gpio: gpio-controller@d8110000 {
|
||||
compatible = "wm,wm8505-gpio";
|
||||
gpio-controller;
|
||||
pinctrl: pinctrl@d8110000 {
|
||||
compatible = "wm,wm8505-pinctrl";
|
||||
reg = <0xd8110000 0x10000>;
|
||||
#gpio-cells = <3>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
pmc@d8130000 {
|
||||
|
|
|
|||
|
|
@ -34,11 +34,13 @@ intc1: interrupt-controller@d8150000 {
|
|||
interrupts = <56 57 58 59 60 61 62 63>;
|
||||
};
|
||||
|
||||
gpio: gpio-controller@d8110000 {
|
||||
compatible = "wm,wm8650-gpio";
|
||||
gpio-controller;
|
||||
pinctrl: pinctrl@d8110000 {
|
||||
compatible = "wm,wm8650-pinctrl";
|
||||
reg = <0xd8110000 0x10000>;
|
||||
#gpio-cells = <3>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
pmc@d8130000 {
|
||||
|
|
|
|||
|
|
@ -41,11 +41,13 @@ intc1: interrupt-controller@d8150000 {
|
|||
interrupts = <56 57 58 59 60 61 62 63>;
|
||||
};
|
||||
|
||||
gpio: gpio-controller@d8110000 {
|
||||
compatible = "wm,wm8650-gpio";
|
||||
gpio-controller;
|
||||
pinctrl: pinctrl@d8110000 {
|
||||
compatible = "wm,wm8850-pinctrl";
|
||||
reg = <0xd8110000 0x10000>;
|
||||
#gpio-cells = <3>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
pmc@d8130000 {
|
||||
|
|
|
|||
|
|
@ -118,56 +118,23 @@ cpu_clk: cpu_clk {
|
|||
};
|
||||
|
||||
ttc0: ttc0@f8001000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "xlnx,ttc";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = < 0 10 4 0 11 4 0 12 4 >;
|
||||
compatible = "cdns,ttc";
|
||||
reg = <0xF8001000 0x1000>;
|
||||
clocks = <&cpu_clk 3>;
|
||||
clock-names = "cpu_1x";
|
||||
clock-ranges;
|
||||
|
||||
ttc0_0: ttc0.0 {
|
||||
status = "disabled";
|
||||
reg = <0>;
|
||||
interrupts = <0 10 4>;
|
||||
};
|
||||
ttc0_1: ttc0.1 {
|
||||
status = "disabled";
|
||||
reg = <1>;
|
||||
interrupts = <0 11 4>;
|
||||
};
|
||||
ttc0_2: ttc0.2 {
|
||||
status = "disabled";
|
||||
reg = <2>;
|
||||
interrupts = <0 12 4>;
|
||||
};
|
||||
};
|
||||
|
||||
ttc1: ttc1@f8002000 {
|
||||
#interrupt-parent = <&intc>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "xlnx,ttc";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = < 0 37 4 0 38 4 0 39 4 >;
|
||||
compatible = "cdns,ttc";
|
||||
reg = <0xF8002000 0x1000>;
|
||||
clocks = <&cpu_clk 3>;
|
||||
clock-names = "cpu_1x";
|
||||
clock-ranges;
|
||||
|
||||
ttc1_0: ttc1.0 {
|
||||
status = "disabled";
|
||||
reg = <0>;
|
||||
interrupts = <0 37 4>;
|
||||
};
|
||||
ttc1_1: ttc1.1 {
|
||||
status = "disabled";
|
||||
reg = <1>;
|
||||
interrupts = <0 38 4>;
|
||||
};
|
||||
ttc1_2: ttc1.2 {
|
||||
status = "disabled";
|
||||
reg = <2>;
|
||||
interrupts = <0 39 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -32,13 +32,3 @@ chosen {
|
|||
&ps_clk {
|
||||
clock-frequency = <33333330>;
|
||||
};
|
||||
|
||||
&ttc0_0 {
|
||||
status = "ok";
|
||||
compatible = "xlnx,ttc-counter-clocksource";
|
||||
};
|
||||
|
||||
&ttc0_1 {
|
||||
status = "ok";
|
||||
compatible = "xlnx,ttc-counter-clockevent";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -169,6 +169,8 @@ static struct clk *periph_clocks[] __initdata = {
|
|||
};
|
||||
|
||||
static struct clk_lookup periph_clocks_lookups[] = {
|
||||
CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1),
|
||||
CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1),
|
||||
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
|
||||
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
|
||||
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
|
||||
|
|
|
|||
|
|
@ -488,7 +488,6 @@ static struct resource lcdc_resources[] = {
|
|||
};
|
||||
|
||||
static struct platform_device at91_lcdc_device = {
|
||||
.name = "atmel_lcdfb",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &lcdc_dmamask,
|
||||
|
|
@ -505,6 +504,11 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
|
|||
return;
|
||||
}
|
||||
|
||||
if (cpu_is_at91sam9g10())
|
||||
at91_lcdc_device.name = "at91sam9g10-lcdfb";
|
||||
else
|
||||
at91_lcdc_device.name = "at91sam9261-lcdfb";
|
||||
|
||||
#if defined(CONFIG_FB_ATMEL_STN)
|
||||
at91_set_A_periph(AT91_PIN_PB0, 0); /* LCDVSYNC */
|
||||
at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
|
||||
|
|
|
|||
|
|
@ -190,6 +190,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
|
|||
CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
|
||||
CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
|
||||
CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
|
||||
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
|
||||
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
|
||||
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
|
||||
|
|
|
|||
|
|
@ -848,7 +848,7 @@ static struct resource lcdc_resources[] = {
|
|||
};
|
||||
|
||||
static struct platform_device at91_lcdc_device = {
|
||||
.name = "atmel_lcdfb",
|
||||
.name = "at91sam9263-lcdfb",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &lcdc_dmamask,
|
||||
|
|
|
|||
|
|
@ -228,6 +228,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
|
|||
CLKDEV_CON_ID("hclk", &macb_clk),
|
||||
/* One additional fake clock for ohci */
|
||||
CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
|
||||
CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
|
||||
CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
|
||||
|
|
|
|||
|
|
@ -981,7 +981,6 @@ static struct resource lcdc_resources[] = {
|
|||
};
|
||||
|
||||
static struct platform_device at91_lcdc_device = {
|
||||
.name = "atmel_lcdfb",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &lcdc_dmamask,
|
||||
|
|
@ -997,6 +996,11 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
|
|||
if (!data)
|
||||
return;
|
||||
|
||||
if (cpu_is_at91sam9g45es())
|
||||
at91_lcdc_device.name = "at91sam9g45es-lcdfb";
|
||||
else
|
||||
at91_lcdc_device.name = "at91sam9g45-lcdfb";
|
||||
|
||||
at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
|
||||
|
||||
at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
|
||||
|
|
|
|||
|
|
@ -179,6 +179,7 @@ static struct clk *periph_clocks[] __initdata = {
|
|||
};
|
||||
|
||||
static struct clk_lookup periph_clocks_lookups[] = {
|
||||
CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
|
||||
CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
|
||||
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
|
||||
|
|
|
|||
|
|
@ -514,7 +514,7 @@ static struct resource lcdc_resources[] = {
|
|||
};
|
||||
|
||||
static struct platform_device at91_lcdc_device = {
|
||||
.name = "atmel_lcdfb",
|
||||
.name = "at91sam9rl-lcdfb",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &lcdc_dmamask,
|
||||
|
|
|
|||
|
|
@ -63,6 +63,7 @@ config SOC_EXYNOS5250
|
|||
bool "SAMSUNG EXYNOS5250"
|
||||
default y
|
||||
depends on ARCH_EXYNOS5
|
||||
select PM_GENERIC_DOMAINS if PM
|
||||
select S5P_PM if PM
|
||||
select S5P_SLEEP if PM
|
||||
select S5P_DEV_MFC
|
||||
|
|
@ -83,12 +84,6 @@ config SOC_EXYNOS5440
|
|||
help
|
||||
Enable EXYNOS5440 SoC support
|
||||
|
||||
config EXYNOS4_MCT
|
||||
bool
|
||||
default y
|
||||
help
|
||||
Use MCT (Multi Core Timer) as kernel timers
|
||||
|
||||
config EXYNOS_ATAGS
|
||||
bool "ATAGS based boot for EXYNOS (deprecated)"
|
||||
depends on !ARCH_MULTIPLATFORM
|
||||
|
|
@ -285,8 +280,8 @@ config MACH_UNIVERSAL_C210
|
|||
select S5P_DEV_ONENAND
|
||||
select S5P_DEV_TV
|
||||
select S5P_GPIO_INT
|
||||
select S5P_HRT
|
||||
select S5P_SETUP_MIPIPHY
|
||||
select SAMSUNG_HRT
|
||||
help
|
||||
Machine support for Samsung Mobile Universal S5PC210 Reference
|
||||
Board.
|
||||
|
|
@ -414,10 +409,12 @@ config MACH_EXYNOS4_DT
|
|||
bool "Samsung Exynos4 Machine using device tree"
|
||||
depends on ARCH_EXYNOS4
|
||||
select ARM_AMBA
|
||||
select CLKSRC_OF
|
||||
select CPU_EXYNOS4210
|
||||
select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
|
||||
select PINCTRL
|
||||
select PINCTRL_EXYNOS
|
||||
select S5P_DEV_MFC
|
||||
select USE_OF
|
||||
help
|
||||
Machine support for Samsung Exynos4 machine with device tree enabled.
|
||||
|
|
@ -430,6 +427,7 @@ config MACH_EXYNOS5_DT
|
|||
default y
|
||||
depends on ARCH_EXYNOS5
|
||||
select ARM_AMBA
|
||||
select CLKSRC_OF
|
||||
select USE_OF
|
||||
help
|
||||
Machine support for Samsung EXYNOS5 machine with device tree enabled.
|
||||
|
|
|
|||
|
|
@ -13,10 +13,6 @@ obj- :=
|
|||
# Core
|
||||
|
||||
obj-$(CONFIG_ARCH_EXYNOS) += common.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
|
||||
obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
|
||||
obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
|
||||
obj-$(CONFIG_SOC_EXYNOS5250) += clock-exynos5.o
|
||||
|
||||
obj-$(CONFIG_PM) += pm.o
|
||||
obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
|
||||
|
|
@ -26,8 +22,6 @@ obj-$(CONFIG_ARCH_EXYNOS) += pmu.o
|
|||
|
||||
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
|
||||
obj-$(CONFIG_EXYNOS4_MCT) += mct.o
|
||||
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
|
||||
# machine support
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,35 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Header file for exynos4 clock support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_CLOCK_H
|
||||
#define __ASM_ARCH_CLOCK_H __FILE__
|
||||
|
||||
#include <linux/clk.h>
|
||||
|
||||
extern struct clksrc_clk exynos4_clk_aclk_133;
|
||||
extern struct clksrc_clk exynos4_clk_mout_mpll;
|
||||
|
||||
extern struct clksrc_sources exynos4_clkset_mout_corebus;
|
||||
extern struct clksrc_sources exynos4_clkset_group;
|
||||
|
||||
extern struct clk *exynos4_clkset_aclk_top_list[];
|
||||
extern struct clk *exynos4_clkset_group_list[];
|
||||
|
||||
extern struct clksrc_sources exynos4_clkset_mout_g2d0;
|
||||
extern struct clksrc_sources exynos4_clkset_mout_g2d1;
|
||||
|
||||
extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
|
||||
|
||||
#endif /* __ASM_ARCH_CLOCK_H */
|
||||
|
|
@ -1,187 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4210 - Clock support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include <plat/cpu-freq.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/pll.h>
|
||||
#include <plat/s5p-clock.h>
|
||||
#include <plat/clock-clksrc.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "clock-exynos4.h"
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save exynos4210_clock_save[] = {
|
||||
SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct clksrc_clk *sysclks[] = {
|
||||
/* nothing here yet */
|
||||
};
|
||||
|
||||
static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
|
||||
.clk = {
|
||||
.name = "mout_g2d0",
|
||||
},
|
||||
.sources = &exynos4_clkset_mout_g2d0,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
|
||||
.clk = {
|
||||
.name = "mout_g2d1",
|
||||
},
|
||||
.sources = &exynos4_clkset_mout_g2d1,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clk *exynos4210_clkset_mout_g2d_list[] = {
|
||||
[0] = &exynos4210_clk_mout_g2d0.clk,
|
||||
[1] = &exynos4210_clk_mout_g2d1.clk,
|
||||
};
|
||||
|
||||
static struct clksrc_sources exynos4210_clkset_mout_g2d = {
|
||||
.sources = exynos4210_clkset_mout_g2d_list,
|
||||
.nr_sources = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),
|
||||
};
|
||||
|
||||
static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
|
||||
}
|
||||
|
||||
static struct clksrc_clk clksrcs[] = {
|
||||
{
|
||||
.clk = {
|
||||
.name = "sclk_sata",
|
||||
.id = -1,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
},
|
||||
.sources = &exynos4_clkset_mout_corebus,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
|
||||
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimd",
|
||||
.devname = "exynos4-fb.1",
|
||||
.enable = exynos4_clksrc_mask_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
.sources = &exynos4_clkset_group,
|
||||
.reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
|
||||
.reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimg2d",
|
||||
},
|
||||
.sources = &exynos4210_clkset_mout_g2d,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
|
||||
.reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk init_clocks_off[] = {
|
||||
{
|
||||
.name = "sataphy",
|
||||
.id = -1,
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "sata",
|
||||
.id = -1,
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 10),
|
||||
}, {
|
||||
.name = "fimd",
|
||||
.devname = "exynos4-fb.1",
|
||||
.enable = exynos4_clk_ip_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.9",
|
||||
.enable = exynos4_clk_ip_image_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.11",
|
||||
.enable = exynos4_clk_ip_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "fimg2d",
|
||||
.enable = exynos4_clk_ip_image_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int exynos4210_clock_suspend(void)
|
||||
{
|
||||
s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos4210_clock_resume(void)
|
||||
{
|
||||
s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
|
||||
}
|
||||
|
||||
#else
|
||||
#define exynos4210_clock_suspend NULL
|
||||
#define exynos4210_clock_resume NULL
|
||||
#endif
|
||||
|
||||
static struct syscore_ops exynos4210_clock_syscore_ops = {
|
||||
.suspend = exynos4210_clock_suspend,
|
||||
.resume = exynos4210_clock_resume,
|
||||
};
|
||||
|
||||
void __init exynos4210_register_clocks(void)
|
||||
{
|
||||
int ptr;
|
||||
|
||||
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
|
||||
exynos4_clk_mout_mpll.reg_src.shift = 8;
|
||||
exynos4_clk_mout_mpll.reg_src.size = 1;
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
|
||||
s3c_register_clksrc(sysclks[ptr], 1);
|
||||
|
||||
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
|
||||
|
||||
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
|
||||
register_syscore_ops(&exynos4210_clock_syscore_ops);
|
||||
}
|
||||
|
|
@ -1,201 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4212 - Clock support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include <plat/cpu-freq.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/pll.h>
|
||||
#include <plat/s5p-clock.h>
|
||||
#include <plat/clock-clksrc.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "clock-exynos4.h"
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save exynos4212_clock_save[] = {
|
||||
SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
|
||||
};
|
||||
#endif
|
||||
|
||||
static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
|
||||
}
|
||||
|
||||
static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
|
||||
}
|
||||
|
||||
static struct clk *clk_src_mpll_user_list[] = {
|
||||
[0] = &clk_fin_mpll,
|
||||
[1] = &exynos4_clk_mout_mpll.clk,
|
||||
};
|
||||
|
||||
static struct clksrc_sources clk_src_mpll_user = {
|
||||
.sources = clk_src_mpll_user_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_mout_mpll_user = {
|
||||
.clk = {
|
||||
.name = "mout_mpll_user",
|
||||
},
|
||||
.sources = &clk_src_mpll_user,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
|
||||
.clk = {
|
||||
.name = "mout_g2d0",
|
||||
},
|
||||
.sources = &exynos4_clkset_mout_g2d0,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
|
||||
.clk = {
|
||||
.name = "mout_g2d1",
|
||||
},
|
||||
.sources = &exynos4_clkset_mout_g2d1,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
|
||||
[0] = &exynos4x12_clk_mout_g2d0.clk,
|
||||
[1] = &exynos4x12_clk_mout_g2d1.clk,
|
||||
};
|
||||
|
||||
static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
|
||||
.sources = exynos4x12_clkset_mout_g2d_list,
|
||||
.nr_sources = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
|
||||
};
|
||||
|
||||
static struct clksrc_clk *sysclks[] = {
|
||||
&clk_mout_mpll_user,
|
||||
};
|
||||
|
||||
static struct clksrc_clk clksrcs[] = {
|
||||
{
|
||||
.clk = {
|
||||
.name = "sclk_fimg2d",
|
||||
},
|
||||
.sources = &exynos4x12_clkset_mout_g2d,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
|
||||
.reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk init_clocks_off[] = {
|
||||
{
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.9",
|
||||
.enable = exynos4_clk_ip_dmc_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.12",
|
||||
.enable = exynos4212_clk_ip_isp0_ctrl,
|
||||
.ctrlbit = (7 << 8),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.13",
|
||||
.enable = exynos4212_clk_ip_isp1_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.14",
|
||||
.enable = exynos4212_clk_ip_isp0_ctrl,
|
||||
.ctrlbit = (1 << 11),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.15",
|
||||
.enable = exynos4212_clk_ip_isp0_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
}, {
|
||||
.name = "flite",
|
||||
.devname = "exynos-fimc-lite.0",
|
||||
.enable = exynos4212_clk_ip_isp0_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "flite",
|
||||
.devname = "exynos-fimc-lite.1",
|
||||
.enable = exynos4212_clk_ip_isp0_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "fimg2d",
|
||||
.enable = exynos4_clk_ip_dmc_ctrl,
|
||||
.ctrlbit = (1 << 23),
|
||||
},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int exynos4212_clock_suspend(void)
|
||||
{
|
||||
s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos4212_clock_resume(void)
|
||||
{
|
||||
s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
|
||||
}
|
||||
|
||||
#else
|
||||
#define exynos4212_clock_suspend NULL
|
||||
#define exynos4212_clock_resume NULL
|
||||
#endif
|
||||
|
||||
static struct syscore_ops exynos4212_clock_syscore_ops = {
|
||||
.suspend = exynos4212_clock_suspend,
|
||||
.resume = exynos4212_clock_resume,
|
||||
};
|
||||
|
||||
void __init exynos4212_register_clocks(void)
|
||||
{
|
||||
int ptr;
|
||||
|
||||
/* usbphy1 is removed */
|
||||
exynos4_clkset_group_list[4] = NULL;
|
||||
|
||||
/* mout_mpll_user is used */
|
||||
exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
|
||||
exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
|
||||
|
||||
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
|
||||
exynos4_clk_mout_mpll.reg_src.shift = 12;
|
||||
exynos4_clk_mout_mpll.reg_src.size = 1;
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
|
||||
s3c_register_clksrc(sysclks[ptr], 1);
|
||||
|
||||
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
|
||||
|
||||
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
|
||||
register_syscore_ops(&exynos4212_clock_syscore_ops);
|
||||
}
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -24,6 +24,8 @@
|
|||
#include <linux/export.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
|
||||
|
|
@ -37,9 +39,9 @@
|
|||
#include <mach/regs-irq.h>
|
||||
#include <mach/regs-pmu.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/pm.h>
|
||||
#include <plat/sdhci.h>
|
||||
|
|
@ -65,17 +67,16 @@ static const char name_exynos5440[] = "EXYNOS5440";
|
|||
static void exynos4_map_io(void);
|
||||
static void exynos5_map_io(void);
|
||||
static void exynos5440_map_io(void);
|
||||
static void exynos4_init_clocks(int xtal);
|
||||
static void exynos5_init_clocks(int xtal);
|
||||
static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
|
||||
static int exynos_init(void);
|
||||
|
||||
unsigned long xxti_f = 0, xusbxti_f = 0;
|
||||
|
||||
static struct cpu_table cpu_ids[] __initdata = {
|
||||
{
|
||||
.idcode = EXYNOS4210_CPU_ID,
|
||||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4210,
|
||||
|
|
@ -83,7 +84,6 @@ static struct cpu_table cpu_ids[] __initdata = {
|
|||
.idcode = EXYNOS4212_CPU_ID,
|
||||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4212,
|
||||
|
|
@ -91,7 +91,6 @@ static struct cpu_table cpu_ids[] __initdata = {
|
|||
.idcode = EXYNOS4412_CPU_ID,
|
||||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4412,
|
||||
|
|
@ -99,7 +98,6 @@ static struct cpu_table cpu_ids[] __initdata = {
|
|||
.idcode = EXYNOS5250_SOC_ID,
|
||||
.idmask = EXYNOS5_SOC_MASK,
|
||||
.map_io = exynos5_map_io,
|
||||
.init_clocks = exynos5_init_clocks,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos5250,
|
||||
}, {
|
||||
|
|
@ -256,11 +254,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
|
|||
.pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_SYSTIMER,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_SYSRAM,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
|
||||
|
|
@ -402,43 +395,26 @@ static void __init exynos5_map_io(void)
|
|||
iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
|
||||
}
|
||||
|
||||
static void __init exynos4_init_clocks(int xtal)
|
||||
{
|
||||
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
|
||||
|
||||
s3c24xx_register_baseclocks(xtal);
|
||||
s5p_register_clocks(xtal);
|
||||
|
||||
if (soc_is_exynos4210())
|
||||
exynos4210_register_clocks();
|
||||
else if (soc_is_exynos4212() || soc_is_exynos4412())
|
||||
exynos4212_register_clocks();
|
||||
|
||||
exynos4_register_clocks();
|
||||
exynos4_setup_clocks();
|
||||
}
|
||||
|
||||
static void __init exynos5440_map_io(void)
|
||||
{
|
||||
iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
|
||||
}
|
||||
|
||||
static void __init exynos5_init_clocks(int xtal)
|
||||
void __init exynos_init_time(void)
|
||||
{
|
||||
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
|
||||
|
||||
/* EXYNOS5440 can support only common clock framework */
|
||||
|
||||
if (soc_is_exynos5440())
|
||||
return;
|
||||
|
||||
#ifdef CONFIG_SOC_EXYNOS5250
|
||||
s3c24xx_register_baseclocks(xtal);
|
||||
s5p_register_clocks(xtal);
|
||||
|
||||
exynos5_register_clocks();
|
||||
exynos5_setup_clocks();
|
||||
if (of_have_populated_dt()) {
|
||||
#ifdef CONFIG_OF
|
||||
of_clk_init(NULL);
|
||||
clocksource_of_init();
|
||||
#endif
|
||||
} else {
|
||||
/* todo: remove after migrating legacy E4 platforms to dt */
|
||||
#ifdef CONFIG_ARCH_EXYNOS4
|
||||
exynos4_clk_init(NULL);
|
||||
exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
|
||||
#endif
|
||||
mct_init();
|
||||
}
|
||||
}
|
||||
|
||||
void __init exynos4_init_irq(void)
|
||||
|
|
@ -824,6 +800,7 @@ static int __init exynos_init_irq_eint(void)
|
|||
static const struct of_device_id exynos_pinctrl_ids[] = {
|
||||
{ .compatible = "samsung,exynos4210-pinctrl", },
|
||||
{ .compatible = "samsung,exynos4x12-pinctrl", },
|
||||
{ .compatible = "samsung,exynos5250-pinctrl", },
|
||||
};
|
||||
struct device_node *pctrl_np, *wkup_np;
|
||||
const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
|
||||
|
|
@ -877,3 +854,30 @@ static int __init exynos_init_irq_eint(void)
|
|||
return 0;
|
||||
}
|
||||
arch_initcall(exynos_init_irq_eint);
|
||||
|
||||
static struct resource exynos4_pmu_resource[] = {
|
||||
DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
|
||||
DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
|
||||
#if defined(CONFIG_SOC_EXYNOS4412)
|
||||
DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
|
||||
DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct platform_device exynos4_device_pmu = {
|
||||
.name = "arm-pmu",
|
||||
.num_resources = ARRAY_SIZE(exynos4_pmu_resource),
|
||||
.resource = exynos4_pmu_resource,
|
||||
};
|
||||
|
||||
static int __init exynos_armpmu_init(void)
|
||||
{
|
||||
if (!of_have_populated_dt()) {
|
||||
if (soc_is_exynos4210() || soc_is_exynos4212())
|
||||
exynos4_device_pmu.num_resources = 2;
|
||||
platform_device_register(&exynos4_device_pmu);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(exynos_armpmu_init);
|
||||
|
|
|
|||
|
|
@ -12,7 +12,11 @@
|
|||
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
|
||||
#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
|
||||
|
||||
extern void exynos4_timer_init(void);
|
||||
#include <linux/of.h>
|
||||
|
||||
extern void mct_init(void);
|
||||
void exynos_init_time(void);
|
||||
extern unsigned long xxti_f, xusbxti_f;
|
||||
|
||||
struct map_desc;
|
||||
void exynos_init_io(struct map_desc *mach_desc, int size);
|
||||
|
|
@ -22,6 +26,10 @@ void exynos4_restart(char mode, const char *cmd);
|
|||
void exynos5_restart(char mode, const char *cmd);
|
||||
void exynos_init_late(void);
|
||||
|
||||
/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
|
||||
void exynos4_clk_init(struct device_node *np);
|
||||
void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
|
||||
|
||||
#ifdef CONFIG_PM_GENERIC_DOMAINS
|
||||
int exynos_pm_late_initcall(void);
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -30,8 +30,6 @@
|
|||
|
||||
/* For EXYNOS4 and EXYNOS5 */
|
||||
|
||||
#define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12)
|
||||
|
||||
#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
|
||||
|
||||
/* For EXYNOS4 SoCs */
|
||||
|
|
@ -128,7 +126,7 @@
|
|||
#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
|
||||
#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
|
||||
#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
|
||||
#define EXYNOS4_IRQ_PMU IRQ_SPI(110)
|
||||
#define EXYNOS4_IRQ_POWER_PMU IRQ_SPI(110)
|
||||
#define EXYNOS4_IRQ_GPS IRQ_SPI(111)
|
||||
#define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
|
||||
#define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113)
|
||||
|
|
@ -136,6 +134,11 @@
|
|||
#define EXYNOS4_IRQ_TSI IRQ_SPI(115)
|
||||
#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
|
||||
|
||||
#define EXYNOS4_IRQ_PMU COMBINER_IRQ(2, 2)
|
||||
#define EXYNOS4_IRQ_PMU_CPU1 COMBINER_IRQ(3, 2)
|
||||
#define EXYNOS4_IRQ_PMU_CPU2 COMBINER_IRQ(18, 2)
|
||||
#define EXYNOS4_IRQ_PMU_CPU3 COMBINER_IRQ(19, 2)
|
||||
|
||||
#define EXYNOS4_IRQ_TMU_TRIG0 COMBINER_IRQ(2, 4)
|
||||
#define EXYNOS4_IRQ_TMU_TRIG1 COMBINER_IRQ(3, 4)
|
||||
|
||||
|
|
@ -168,7 +171,10 @@
|
|||
#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
|
||||
#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
|
||||
|
||||
#define EXYNOS4_MAX_COMBINER_NR 16
|
||||
#define EXYNOS4210_MAX_COMBINER_NR 16
|
||||
#define EXYNOS4212_MAX_COMBINER_NR 18
|
||||
#define EXYNOS4412_MAX_COMBINER_NR 20
|
||||
#define EXYNOS4_MAX_COMBINER_NR EXYNOS4412_MAX_COMBINER_NR
|
||||
|
||||
#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16
|
||||
#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9
|
||||
|
|
@ -233,7 +239,6 @@
|
|||
#define IRQ_TC EXYNOS4_IRQ_PEN0
|
||||
|
||||
#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
|
||||
#define IRQ_PMU EXYNOS4_IRQ_PMU
|
||||
|
||||
#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
|
||||
#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
|
||||
|
|
@ -323,8 +328,6 @@
|
|||
#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
|
||||
#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
|
||||
|
||||
#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120)
|
||||
#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121)
|
||||
#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
|
||||
#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
|
||||
#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
|
||||
|
|
@ -419,8 +422,6 @@
|
|||
#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
|
||||
#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
|
||||
#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
|
||||
|
|
|
|||
|
|
@ -65,7 +65,6 @@
|
|||
#define EXYNOS5_PA_CMU 0x10010000
|
||||
|
||||
#define EXYNOS4_PA_SYSTIMER 0x10050000
|
||||
#define EXYNOS5_PA_SYSTIMER 0x101C0000
|
||||
|
||||
#define EXYNOS4_PA_WATCHDOG 0x10060000
|
||||
#define EXYNOS5_PA_WATCHDOG 0x101D0000
|
||||
|
|
|
|||
|
|
@ -1,53 +0,0 @@
|
|||
/* arch/arm/mach-exynos4/include/mach/regs-mct.h
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4 MCT configutation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_REGS_MCT_H
|
||||
#define __ASM_ARCH_REGS_MCT_H __FILE__
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
#define EXYNOS4_MCTREG(x) (S5P_VA_SYSTIMER + (x))
|
||||
|
||||
#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
|
||||
#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
|
||||
#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
|
||||
|
||||
#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
|
||||
#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
|
||||
#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
|
||||
|
||||
#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
|
||||
|
||||
#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
|
||||
#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
|
||||
#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
|
||||
|
||||
#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
|
||||
#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
|
||||
#define EXYNOS4_MCT_L_MASK (0xffffff00)
|
||||
|
||||
#define MCT_L_TCNTB_OFFSET (0x00)
|
||||
#define MCT_L_ICNTB_OFFSET (0x08)
|
||||
#define MCT_L_TCON_OFFSET (0x20)
|
||||
#define MCT_L_INT_CSTAT_OFFSET (0x30)
|
||||
#define MCT_L_INT_ENB_OFFSET (0x34)
|
||||
#define MCT_L_WSTAT_OFFSET (0x40)
|
||||
|
||||
#define MCT_G_TCON_START (1 << 8)
|
||||
#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
|
||||
#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
|
||||
|
||||
#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
|
||||
#define MCT_L_TCON_INT_START (1 << 1)
|
||||
#define MCT_L_TCON_TIMER_START (1 << 0)
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_MCT_H */
|
||||
|
|
@ -178,7 +178,6 @@ static void __init armlex4210_smsc911x_init(void)
|
|||
static void __init armlex4210_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
s3c24xx_init_uarts(armlex4210_uartcfgs,
|
||||
ARRAY_SIZE(armlex4210_uartcfgs));
|
||||
}
|
||||
|
|
@ -203,6 +202,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
|
|||
.map_io = armlex4210_map_io,
|
||||
.init_machine = armlex4210_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -11,121 +11,26 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/clocksource.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/mfc.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
/*
|
||||
* The following lookup table is used to override device names when devices
|
||||
* are registered from device tree. This is temporarily added to enable
|
||||
* device tree support addition for the Exynos4 architecture.
|
||||
*
|
||||
* For drivers that require platform data to be provided from the machine
|
||||
* file, a platform data pointer can also be supplied along with the
|
||||
* devices names. Usually, the platform data elements that cannot be parsed
|
||||
* from the device tree by the drivers (example: function pointers) are
|
||||
* supplied. But it should be noted that this is a temporary mechanism and
|
||||
* at some point, the drivers should be capable of parsing all the platform
|
||||
* data from the device tree.
|
||||
*/
|
||||
static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
|
||||
"exynos4210-uart.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
|
||||
"exynos4210-uart.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
|
||||
"exynos4210-uart.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
|
||||
"exynos4210-uart.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
|
||||
"exynos4-sdhci.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1),
|
||||
"exynos4-sdhci.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2),
|
||||
"exynos4-sdhci.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3),
|
||||
"exynos4-sdhci.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
|
||||
"s3c2440-i2c.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(1),
|
||||
"s3c2440-i2c.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(2),
|
||||
"s3c2440-i2c.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(3),
|
||||
"s3c2440-i2c.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(4),
|
||||
"s3c2440-i2c.4", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(5),
|
||||
"s3c2440-i2c.5", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(6),
|
||||
"s3c2440-i2c.6", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(7),
|
||||
"s3c2440-i2c.7", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
|
||||
"exynos4210-spi.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
|
||||
"exynos4210-spi.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
|
||||
"exynos4210-spi.2", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
|
||||
"exynos-tmu", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13620000,
|
||||
"exynos-sysmmu.0", NULL), /* MFC_L */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13630000,
|
||||
"exynos-sysmmu.1", NULL), /* MFC_R */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E20000,
|
||||
"exynos-sysmmu.2", NULL), /* TV */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A60000,
|
||||
"exynos-sysmmu.3", NULL), /* JPEG */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A30000,
|
||||
"exynos-sysmmu.4", NULL), /* ROTATOR */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A20000,
|
||||
"exynos-sysmmu.5", NULL), /* FIMC0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A30000,
|
||||
"exynos-sysmmu.6", NULL), /* FIMC1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A40000,
|
||||
"exynos-sysmmu.7", NULL), /* FIMC2 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A50000,
|
||||
"exynos-sysmmu.8", NULL), /* FIMC3 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A20000,
|
||||
"exynos-sysmmu.9", NULL), /* G2D(4210) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A40000,
|
||||
"exynos-sysmmu.9", NULL), /* G2D(4x12) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11E20000,
|
||||
"exynos-sysmmu.10", NULL), /* FIMD0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12220000,
|
||||
"exynos-sysmmu.11", NULL), /* FIMD1(4210) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12260000,
|
||||
"exynos-sysmmu.12", NULL), /* IS0(4x12) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x122B0000,
|
||||
"exynos-sysmmu.13", NULL), /* IS1(4x12) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123B0000,
|
||||
"exynos-sysmmu.14", NULL), /* FIMC-LITE0(4x12) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123C0000,
|
||||
"exynos-sysmmu.15", NULL), /* FIMC-LITE1(4x12) */
|
||||
{},
|
||||
};
|
||||
|
||||
static void __init exynos4_dt_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
}
|
||||
|
||||
static void __init exynos4_dt_machine_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
exynos4_auxdata_lookup, NULL);
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static char const *exynos4_dt_compat[] __initdata = {
|
||||
|
|
@ -135,6 +40,18 @@ static char const *exynos4_dt_compat[] __initdata = {
|
|||
NULL
|
||||
};
|
||||
|
||||
static void __init exynos4_reserve(void)
|
||||
{
|
||||
#ifdef CONFIG_S5P_DEV_MFC
|
||||
struct s5p_mfc_dt_meminfo mfc_mem;
|
||||
|
||||
/* Reserve memory for MFC only if it's available */
|
||||
mfc_mem.compatible = "samsung,mfc-v5";
|
||||
if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
|
||||
s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
|
||||
mfc_mem.lsize);
|
||||
#endif
|
||||
}
|
||||
DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
|
||||
/* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
|
||||
.smp = smp_ops(exynos_smp_ops),
|
||||
|
|
@ -142,7 +59,8 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
|
|||
.map_io = exynos4_dt_map_io,
|
||||
.init_machine = exynos4_dt_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.dt_compat = exynos4_dt_compat,
|
||||
.restart = exynos4_restart,
|
||||
.reserve = exynos4_reserve,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -11,151 +11,21 @@
|
|||
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clocksource.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-pmu.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/mfc.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
/*
|
||||
* The following lookup table is used to override device names when devices
|
||||
* are registered from device tree. This is temporarily added to enable
|
||||
* device tree support addition for the EXYNOS5 architecture.
|
||||
*
|
||||
* For drivers that require platform data to be provided from the machine
|
||||
* file, a platform data pointer can also be supplied along with the
|
||||
* devices names. Usually, the platform data elements that cannot be parsed
|
||||
* from the device tree by the drivers (example: function pointers) are
|
||||
* supplied. But it should be noted that this is a temporary mechanism and
|
||||
* at some point, the drivers should be capable of parsing all the platform
|
||||
* data from the device tree.
|
||||
*/
|
||||
static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
|
||||
"exynos4210-uart.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
|
||||
"exynos4210-uart.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
|
||||
"exynos4210-uart.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
|
||||
"exynos4210-uart.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
|
||||
"s3c2440-i2c.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
|
||||
"s3c2440-i2c.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
|
||||
"s3c2440-i2c.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
|
||||
"s3c2440-i2c.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
|
||||
"s3c2440-i2c.4", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
|
||||
"s3c2440-i2c.5", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
|
||||
"s3c2440-i2c.6", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
|
||||
"s3c2440-i2c.7", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-hdmiphy-i2c", EXYNOS5_PA_IIC(8),
|
||||
"s3c2440-hdmiphy-i2c", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
|
||||
"dw_mmc.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1,
|
||||
"dw_mmc.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI2,
|
||||
"dw_mmc.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI3,
|
||||
"dw_mmc.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
|
||||
"exynos4210-spi.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
|
||||
"exynos4210-spi.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
|
||||
"exynos4210-spi.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
|
||||
"exynos5-sata", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000,
|
||||
"exynos5-sata-phy", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
|
||||
"exynos5-sata-phy-i2c", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC0,
|
||||
"exynos-gsc.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC1,
|
||||
"exynos-gsc.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC2,
|
||||
"exynos-gsc.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
|
||||
"exynos-gsc.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
|
||||
"exynos5-hdmi", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-mixer", 0x14450000,
|
||||
"exynos5-mixer", NULL),
|
||||
OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
|
||||
"exynos-tmu", NULL),
|
||||
OF_DEV_AUXDATA("samsung,i2s-v5", 0x03830000,
|
||||
"samsung-i2s.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D60000,
|
||||
"samsung-i2s.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D70000,
|
||||
"samsung-i2s.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11210000,
|
||||
"exynos-sysmmu.0", "mfc"), /* MFC_L */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11200000,
|
||||
"exynos-sysmmu.1", "mfc"), /* MFC_R */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14650000,
|
||||
"exynos-sysmmu.2", NULL), /* TV */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11F20000,
|
||||
"exynos-sysmmu.3", "jpeg"), /* JPEG */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11D40000,
|
||||
"exynos-sysmmu.4", NULL), /* ROTATOR */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E80000,
|
||||
"exynos-sysmmu.5", "gscl"), /* GSCL0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E90000,
|
||||
"exynos-sysmmu.6", "gscl"), /* GSCL1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EA0000,
|
||||
"exynos-sysmmu.7", "gscl"), /* GSCL2 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EB0000,
|
||||
"exynos-sysmmu.8", "gscl"), /* GSCL3 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13260000,
|
||||
"exynos-sysmmu.9", NULL), /* FIMC-IS0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x132C0000,
|
||||
"exynos-sysmmu.10", NULL), /* FIMC-IS1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14640000,
|
||||
"exynos-sysmmu.11", NULL), /* FIMD1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C40000,
|
||||
"exynos-sysmmu.12", NULL), /* FIMC-LITE0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C50000,
|
||||
"exynos-sysmmu.13", NULL), /* FIMC-LITE1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A60000,
|
||||
"exynos-sysmmu.14", NULL), /* G2D */
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0,
|
||||
"exynos4210-uart.0", NULL),
|
||||
{},
|
||||
};
|
||||
|
||||
static void __init exynos5_dt_map_io(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
|
||||
exynos_init_io(NULL, 0);
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "samsung,exynos5250"))
|
||||
s3c24xx_init_clocks(24000000);
|
||||
}
|
||||
|
||||
static void __init exynos5_dt_machine_init(void)
|
||||
|
|
@ -182,12 +52,7 @@ static void __init exynos5_dt_machine_init(void)
|
|||
}
|
||||
}
|
||||
|
||||
if (of_machine_is_compatible("samsung,exynos5250"))
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
exynos5250_auxdata_lookup, NULL);
|
||||
else if (of_machine_is_compatible("samsung,exynos5440"))
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
exynos5440_auxdata_lookup, NULL);
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static char const *exynos5_dt_compat[] __initdata = {
|
||||
|
|
@ -216,7 +81,7 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
|
|||
.map_io = exynos5_dt_map_io,
|
||||
.init_machine = exynos5_dt_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.dt_compat = exynos5_dt_compat,
|
||||
.restart = exynos5_restart,
|
||||
.reserve = exynos5_reserve,
|
||||
|
|
|
|||
|
|
@ -1331,8 +1331,9 @@ static struct platform_device *nuri_devices[] __initdata = {
|
|||
static void __init nuri_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
|
||||
xxti_f = 0;
|
||||
xusbxti_f = 24000000;
|
||||
}
|
||||
|
||||
static void __init nuri_reserve(void)
|
||||
|
|
@ -1381,7 +1382,7 @@ MACHINE_START(NURI, "NURI")
|
|||
.map_io = nuri_map_io,
|
||||
.init_machine = nuri_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.reserve = &nuri_reserve,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -755,8 +755,9 @@ static void s5p_tv_setup(void)
|
|||
static void __init origen_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
|
||||
xxti_f = 0;
|
||||
xusbxti_f = 24000000;
|
||||
}
|
||||
|
||||
static void __init origen_power_init(void)
|
||||
|
|
@ -816,7 +817,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
|
|||
.map_io = origen_map_io,
|
||||
.init_machine = origen_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.reserve = &origen_reserve,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -323,7 +323,6 @@ static struct platform_device *smdk4x12_devices[] __initdata = {
|
|||
static void __init smdk4x12_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
|
||||
}
|
||||
|
||||
|
|
@ -377,7 +376,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
|
|||
.init_irq = exynos4_init_irq,
|
||||
.map_io = smdk4x12_map_io,
|
||||
.init_machine = smdk4x12_machine_init,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.restart = exynos4_restart,
|
||||
.reserve = &smdk4x12_reserve,
|
||||
MACHINE_END
|
||||
|
|
@ -391,7 +390,7 @@ MACHINE_START(SMDK4412, "SMDK4412")
|
|||
.map_io = smdk4x12_map_io,
|
||||
.init_machine = smdk4x12_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.restart = exynos4_restart,
|
||||
.reserve = &smdk4x12_reserve,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -372,8 +372,9 @@ static void s5p_tv_setup(void)
|
|||
static void __init smdkv310_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
|
||||
xxti_f = 12000000;
|
||||
xusbxti_f = 24000000;
|
||||
}
|
||||
|
||||
static void __init smdkv310_reserve(void)
|
||||
|
|
@ -424,7 +425,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
|
|||
.init_irq = exynos4_init_irq,
|
||||
.map_io = smdkv310_map_io,
|
||||
.init_machine = smdkv310_machine_init,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.reserve = &smdkv310_reserve,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
@ -437,7 +438,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
|
|||
.map_io = smdkv310_map_io,
|
||||
.init_machine = smdkv310_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.reserve = &smdkv310_reserve,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@
|
|||
#include <plat/mfc.h>
|
||||
#include <plat/sdhci.h>
|
||||
#include <plat/fimc-core.h>
|
||||
#include <plat/s5p-time.h>
|
||||
#include <plat/samsung-time.h>
|
||||
#include <plat/camport.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
|
@ -1093,9 +1093,10 @@ static struct platform_device *universal_devices[] __initdata = {
|
|||
static void __init universal_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
|
||||
s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
|
||||
samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
|
||||
xxti_f = 0;
|
||||
xusbxti_f = 24000000;
|
||||
}
|
||||
|
||||
static void s5p_tv_setup(void)
|
||||
|
|
@ -1153,7 +1154,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
|
|||
.map_io = universal_map_io,
|
||||
.init_machine = universal_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = s5p_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.reserve = &universal_reserve,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -445,16 +445,23 @@ static void enable_board_wakeup_source(void)
|
|||
OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
|
||||
}
|
||||
|
||||
static struct usbhs_phy_data phy_data[] __initdata = {
|
||||
{
|
||||
.port = 1,
|
||||
.reset_gpio = 57,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
{
|
||||
.port = 2,
|
||||
.reset_gpio = 61,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
|
||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = 57,
|
||||
.reset_gpio_port[1] = 61,
|
||||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
|
|
@ -606,6 +613,8 @@ static void __init omap_3430sdp_init(void)
|
|||
board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
|
||||
sdp3430_display_init();
|
||||
enable_board_wakeup_source();
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
usbhs_init(&usbhs_bdata);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -53,16 +53,23 @@ static void enable_board_wakeup_source(void)
|
|||
OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
|
||||
}
|
||||
|
||||
static struct usbhs_phy_data phy_data[] __initdata = {
|
||||
{
|
||||
.port = 1,
|
||||
.reset_gpio = 126,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
{
|
||||
.port = 2,
|
||||
.reset_gpio = 61,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
|
||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = 126,
|
||||
.reset_gpio_port[1] = 61,
|
||||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
|
|
@ -199,6 +206,8 @@ static void __init omap_sdp_init(void)
|
|||
board_smc91x_init();
|
||||
board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16);
|
||||
enable_board_wakeup_source();
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
usbhs_init(&usbhs_bdata);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -47,15 +47,17 @@ static struct omap_board_mux board_mux[] __initdata = {
|
|||
};
|
||||
#endif
|
||||
|
||||
static struct usbhs_phy_data phy_data[] __initdata = {
|
||||
{
|
||||
.port = 1,
|
||||
.reset_gpio = GPIO_USB_NRESET,
|
||||
.vcc_gpio = GPIO_USB_POWER,
|
||||
.vcc_polarity = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = GPIO_USB_NRESET,
|
||||
.reset_gpio_port[1] = -EINVAL,
|
||||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
static struct mtd_partition crane_nand_partitions[] = {
|
||||
|
|
@ -131,13 +133,7 @@ static void __init am3517_crane_init(void)
|
|||
return;
|
||||
}
|
||||
|
||||
ret = gpio_request_one(GPIO_USB_POWER, GPIOF_OUT_INIT_HIGH,
|
||||
"usb_ehci_enable");
|
||||
if (ret < 0) {
|
||||
pr_err("Can not request GPIO %d\n", GPIO_USB_POWER);
|
||||
return;
|
||||
}
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
usbhs_init(&usbhs_bdata);
|
||||
am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -273,6 +273,14 @@ static __init void am3517_evm_mcbsp1_init(void)
|
|||
omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);
|
||||
}
|
||||
|
||||
static struct usbhs_phy_data phy_data[] __initdata = {
|
||||
{
|
||||
.port = 1,
|
||||
.reset_gpio = 57,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
#if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
|
||||
|
|
@ -281,12 +289,6 @@ static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
|||
#else
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
#endif
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = 57,
|
||||
.reset_gpio_port[1] = -EINVAL,
|
||||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
|
|
@ -348,7 +350,6 @@ static struct omap2_hsmmc_info mmc[] = {
|
|||
{} /* Terminator */
|
||||
};
|
||||
|
||||
|
||||
static void __init am3517_evm_init(void)
|
||||
{
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
|
||||
|
|
@ -360,6 +361,8 @@ static void __init am3517_evm_init(void)
|
|||
|
||||
/* Configure GPIO for EHCI port */
|
||||
omap_mux_init_gpio(57, OMAP_PIN_OUTPUT);
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
usbhs_init(&usbhs_bdata);
|
||||
am3517_evm_hecc_init(&am3517_evm_hecc_pdata);
|
||||
/* DSS */
|
||||
|
|
|
|||
|
|
@ -418,15 +418,22 @@ static struct omap2_hsmmc_info mmc[] = {
|
|||
{} /* Terminator */
|
||||
};
|
||||
|
||||
static struct usbhs_phy_data phy_data[] __initdata = {
|
||||
{
|
||||
.port = 1,
|
||||
.reset_gpio = OMAP_MAX_GPIO_LINES + 6,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
{
|
||||
.port = 2,
|
||||
.reset_gpio = OMAP_MAX_GPIO_LINES + 7,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = OMAP_MAX_GPIO_LINES + 6,
|
||||
.reset_gpio_port[1] = OMAP_MAX_GPIO_LINES + 7,
|
||||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
static void __init cm_t35_init_usbh(void)
|
||||
|
|
@ -443,6 +450,7 @@ static void __init cm_t35_init_usbh(void)
|
|||
msleep(1);
|
||||
}
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
usbhs_init(&usbhs_bdata);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -188,15 +188,22 @@ static inline void cm_t3517_init_rtc(void) {}
|
|||
#define HSUSB2_RESET_GPIO (147)
|
||||
#define USB_HUB_RESET_GPIO (152)
|
||||
|
||||
static struct usbhs_phy_data phy_data[] __initdata = {
|
||||
{
|
||||
.port = 1,
|
||||
.reset_gpio = HSUSB1_RESET_GPIO,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
{
|
||||
.port = 2,
|
||||
.reset_gpio = HSUSB2_RESET_GPIO,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data cm_t3517_ehci_pdata __initdata = {
|
||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = HSUSB1_RESET_GPIO,
|
||||
.reset_gpio_port[1] = HSUSB2_RESET_GPIO,
|
||||
.reset_gpio_port[2] = -EINVAL,
|
||||
};
|
||||
|
||||
static int __init cm_t3517_init_usbh(void)
|
||||
|
|
@ -213,6 +220,7 @@ static int __init cm_t3517_init_usbh(void)
|
|||
msleep(1);
|
||||
}
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
usbhs_init(&cm_t3517_ehci_pdata);
|
||||
|
||||
return 0;
|
||||
|
|
@ -324,6 +332,6 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
|
|||
.handle_irq = omap3_intc_handle_irq,
|
||||
.init_machine = cm_t3517_init,
|
||||
.init_late = am35xx_init_late,
|
||||
.init_time = omap3_gp_gptimer_timer_init,
|
||||
.init_time = omap3_gptimer_timer_init,
|
||||
.restart = omap3xxx_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -436,15 +436,7 @@ static struct platform_device *devkit8000_devices[] __initdata = {
|
|||
};
|
||||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
|
||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = -EINVAL,
|
||||
.reset_gpio_port[1] = -EINVAL,
|
||||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
|
|
|
|||
|
|
@ -140,7 +140,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
|
|||
.init_irq = omap_intc_of_init,
|
||||
.handle_irq = omap3_intc_handle_irq,
|
||||
.init_machine = omap_generic_init,
|
||||
.init_time = omap3_am33xx_gptimer_timer_init,
|
||||
.init_time = omap3_gptimer_timer_init,
|
||||
.dt_compat = am33xx_boards_compat,
|
||||
.restart = am33xx_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -527,26 +527,28 @@ static void __init igep_i2c_init(void)
|
|||
omap3_pmic_init("twl4030", &igep_twldata);
|
||||
}
|
||||
|
||||
static struct usbhs_phy_data igep2_phy_data[] __initdata = {
|
||||
{
|
||||
.port = 1,
|
||||
.reset_gpio = IGEP2_GPIO_USBH_NRESET,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct usbhs_phy_data igep3_phy_data[] __initdata = {
|
||||
{
|
||||
.port = 2,
|
||||
.reset_gpio = IGEP3_GPIO_USBH_NRESET,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data igep2_usbhs_bdata __initdata = {
|
||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = IGEP2_GPIO_USBH_NRESET,
|
||||
.reset_gpio_port[1] = -EINVAL,
|
||||
.reset_gpio_port[2] = -EINVAL,
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data igep3_usbhs_bdata __initdata = {
|
||||
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = -EINVAL,
|
||||
.reset_gpio_port[1] = IGEP3_GPIO_USBH_NRESET,
|
||||
.reset_gpio_port[2] = -EINVAL,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
|
|
@ -642,8 +644,10 @@ static void __init igep_init(void)
|
|||
if (machine_is_igep0020()) {
|
||||
omap_display_init(&igep2_dss_data);
|
||||
igep2_init_smsc911x();
|
||||
usbhs_init_phys(igep2_phy_data, ARRAY_SIZE(igep2_phy_data));
|
||||
usbhs_init(&igep2_usbhs_bdata);
|
||||
} else {
|
||||
usbhs_init_phys(igep3_phy_data, ARRAY_SIZE(igep3_phy_data));
|
||||
usbhs_init(&igep3_usbhs_bdata);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@
|
|||
#include <linux/mtd/nand.h>
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/usb/phy.h>
|
||||
#include <linux/usb/nop-usb-xceiv.h>
|
||||
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/i2c/twl.h>
|
||||
|
|
@ -277,6 +278,21 @@ static struct regulator_consumer_supply beagle_vsim_supply[] = {
|
|||
|
||||
static struct gpio_led gpio_leds[];
|
||||
|
||||
/* PHY's VCC regulator might be added later, so flag that we need it */
|
||||
static struct nop_usb_xceiv_platform_data hsusb2_phy_data = {
|
||||
.needs_vcc = true,
|
||||
};
|
||||
|
||||
static struct usbhs_phy_data phy_data[] = {
|
||||
{
|
||||
.port = 2,
|
||||
.reset_gpio = 147,
|
||||
.vcc_gpio = -1, /* updated in beagle_twl_gpio_setup */
|
||||
.vcc_polarity = 1, /* updated in beagle_twl_gpio_setup */
|
||||
.platform_data = &hsusb2_phy_data,
|
||||
},
|
||||
};
|
||||
|
||||
static int beagle_twl_gpio_setup(struct device *dev,
|
||||
unsigned gpio, unsigned ngpio)
|
||||
{
|
||||
|
|
@ -318,9 +334,11 @@ static int beagle_twl_gpio_setup(struct device *dev,
|
|||
}
|
||||
dvi_panel.power_down_gpio = beagle_config.dvi_pd_gpio;
|
||||
|
||||
gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level,
|
||||
"nEN_USB_PWR");
|
||||
/* TWL4030_GPIO_MAX i.e. LED_GPO controls HS USB Port 2 power */
|
||||
phy_data[0].vcc_gpio = gpio + TWL4030_GPIO_MAX;
|
||||
phy_data[0].vcc_polarity = beagle_config.usb_pwr_level;
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -453,15 +471,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = {
|
|||
};
|
||||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
|
||||
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = -EINVAL,
|
||||
.reset_gpio_port[1] = 147,
|
||||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
|
|
@ -543,7 +553,9 @@ static void __init omap3_beagle_init(void)
|
|||
|
||||
usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
|
||||
usb_musb_init(NULL);
|
||||
|
||||
usbhs_init(&usbhs_bdata);
|
||||
|
||||
board_nand_init(omap3beagle_nand_partitions,
|
||||
ARRAY_SIZE(omap3beagle_nand_partitions), NAND_CS,
|
||||
NAND_BUSWIDTH_16, NULL);
|
||||
|
|
|
|||
|
|
@ -496,7 +496,7 @@ struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
|
|||
static struct regulator_consumer_supply omap3evm_vaux2_supplies[] = {
|
||||
REGULATOR_SUPPLY("VDD_CSIPHY1", "omap3isp"), /* OMAP ISP */
|
||||
REGULATOR_SUPPLY("VDD_CSIPHY2", "omap3isp"), /* OMAP ISP */
|
||||
REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"),
|
||||
REGULATOR_SUPPLY("vcc", "nop_usb_xceiv.2"), /* hsusb port 2 */
|
||||
REGULATOR_SUPPLY("vaux2", NULL),
|
||||
};
|
||||
|
||||
|
|
@ -539,17 +539,16 @@ static int __init omap3_evm_i2c_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct usbhs_phy_data phy_data[] __initdata = {
|
||||
{
|
||||
.port = 2,
|
||||
.reset_gpio = -1, /* set at runtime */
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
|
||||
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
/* PHY reset GPIO will be runtime programmed based on EVM version */
|
||||
.reset_gpio_port[0] = -EINVAL,
|
||||
.reset_gpio_port[1] = -EINVAL,
|
||||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
|
|
@ -725,7 +724,7 @@ static void __init omap3_evm_init(void)
|
|||
|
||||
/* setup EHCI phy reset config */
|
||||
omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
|
||||
usbhs_bdata.reset_gpio_port[1] = 21;
|
||||
phy_data[0].reset_gpio = 21;
|
||||
|
||||
/* EVM REV >= E can supply 500mA with EXTVBUS programming */
|
||||
musb_board_data.power = 500;
|
||||
|
|
@ -733,10 +732,12 @@ static void __init omap3_evm_init(void)
|
|||
} else {
|
||||
/* setup EHCI phy reset on MDC */
|
||||
omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
|
||||
usbhs_bdata.reset_gpio_port[1] = 135;
|
||||
phy_data[0].reset_gpio = 135;
|
||||
}
|
||||
usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
|
||||
usb_musb_init(&musb_board_data);
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
usbhs_init(&usbhs_bdata);
|
||||
board_nand_init(omap3evm_nand_partitions,
|
||||
ARRAY_SIZE(omap3evm_nand_partitions), NAND_CS,
|
||||
|
|
|
|||
|
|
@ -346,7 +346,7 @@ static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = {
|
|||
};
|
||||
|
||||
static struct regulator_consumer_supply pandora_usb_phy_supply[] = {
|
||||
REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"),
|
||||
REGULATOR_SUPPLY("vcc", "nop_usb_xceiv.2"), /* hsusb port 2 */
|
||||
};
|
||||
|
||||
/* ads7846 on SPI and 2 nub controllers on I2C */
|
||||
|
|
@ -561,6 +561,14 @@ static void __init pandora_wl1251_init(void)
|
|||
printk(KERN_ERR "wl1251 board initialisation failed\n");
|
||||
}
|
||||
|
||||
static struct usbhs_phy_data phy_data[] __initdata = {
|
||||
{
|
||||
.port = 2,
|
||||
.reset_gpio = 16,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *omap3pandora_devices[] __initdata = {
|
||||
&pandora_leds_gpio,
|
||||
&pandora_keys_gpio,
|
||||
|
|
@ -569,15 +577,7 @@ static struct platform_device *omap3pandora_devices[] __initdata = {
|
|||
};
|
||||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
|
||||
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = -EINVAL,
|
||||
.reset_gpio_port[1] = 16,
|
||||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
|
|
@ -601,7 +601,10 @@ static void __init omap3pandora_init(void)
|
|||
spi_register_board_info(omap3pandora_spi_board_info,
|
||||
ARRAY_SIZE(omap3pandora_spi_board_info));
|
||||
omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL);
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
usbhs_init(&usbhs_bdata);
|
||||
|
||||
usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
|
||||
usb_musb_init(NULL);
|
||||
gpmc_nand_init(&pandora_nand_data, NULL);
|
||||
|
|
|
|||
|
|
@ -357,19 +357,20 @@ static int __init omap3_stalker_i2c_init(void)
|
|||
|
||||
#define OMAP3_STALKER_TS_GPIO 175
|
||||
|
||||
static struct usbhs_phy_data phy_data[] __initdata = {
|
||||
{
|
||||
.port = 2,
|
||||
.reset_gpio = 21,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *omap3_stalker_devices[] __initdata = {
|
||||
&keys_gpio,
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = -EINVAL,
|
||||
.reset_gpio_port[1] = 21,
|
||||
.reset_gpio_port[2] = -EINVAL,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
|
|
@ -406,6 +407,8 @@ static void __init omap3_stalker_init(void)
|
|||
omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
|
||||
usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
|
||||
usb_musb_init(NULL);
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
usbhs_init(&usbhs_bdata);
|
||||
omap_ads7846_init(1, OMAP3_STALKER_TS_GPIO, 310, NULL);
|
||||
|
||||
|
|
|
|||
|
|
@ -305,21 +305,22 @@ static struct omap_board_mux board_mux[] __initdata = {
|
|||
};
|
||||
#endif
|
||||
|
||||
static struct usbhs_phy_data phy_data[] __initdata = {
|
||||
{
|
||||
.port = 2,
|
||||
.reset_gpio = 147,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *omap3_touchbook_devices[] __initdata = {
|
||||
&leds_gpio,
|
||||
&keys_gpio,
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
|
||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = -EINVAL,
|
||||
.reset_gpio_port[1] = 147,
|
||||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
static void omap3_touchbook_poweroff(void)
|
||||
|
|
@ -368,6 +369,8 @@ static void __init omap3_touchbook_init(void)
|
|||
omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata);
|
||||
usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
|
||||
usb_musb_init(NULL);
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
usbhs_init(&usbhs_bdata);
|
||||
board_nand_init(omap3touchbook_nand_partitions,
|
||||
ARRAY_SIZE(omap3touchbook_nand_partitions), NAND_CS,
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@
|
|||
#include <linux/ti_wilink_st.h>
|
||||
#include <linux/usb/musb.h>
|
||||
#include <linux/usb/phy.h>
|
||||
#include <linux/usb/nop-usb-xceiv.h>
|
||||
#include <linux/wl12xx.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/platform_data/omap-abe-twl6040.h>
|
||||
|
|
@ -132,6 +133,22 @@ static struct platform_device btwilink_device = {
|
|||
.id = -1,
|
||||
};
|
||||
|
||||
/* PHY device on HS USB Port 1 i.e. nop_usb_xceiv.1 */
|
||||
static struct nop_usb_xceiv_platform_data hsusb1_phy_data = {
|
||||
/* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
|
||||
.clk_rate = 19200000,
|
||||
};
|
||||
|
||||
static struct usbhs_phy_data phy_data[] __initdata = {
|
||||
{
|
||||
.port = 1,
|
||||
.reset_gpio = GPIO_HUB_NRESET,
|
||||
.vcc_gpio = GPIO_HUB_POWER,
|
||||
.vcc_polarity = 1,
|
||||
.platform_data = &hsusb1_phy_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *panda_devices[] __initdata = {
|
||||
&leds_gpio,
|
||||
&wl1271_device,
|
||||
|
|
@ -142,49 +159,19 @@ static struct platform_device *panda_devices[] __initdata = {
|
|||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.phy_reset = false,
|
||||
.reset_gpio_port[0] = -EINVAL,
|
||||
.reset_gpio_port[1] = -EINVAL,
|
||||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
static struct gpio panda_ehci_gpios[] __initdata = {
|
||||
{ GPIO_HUB_POWER, GPIOF_OUT_INIT_LOW, "hub_power" },
|
||||
{ GPIO_HUB_NRESET, GPIOF_OUT_INIT_LOW, "hub_nreset" },
|
||||
};
|
||||
|
||||
static void __init omap4_ehci_init(void)
|
||||
{
|
||||
int ret;
|
||||
struct clk *phy_ref_clk;
|
||||
|
||||
/* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
|
||||
phy_ref_clk = clk_get(NULL, "auxclk3_ck");
|
||||
if (IS_ERR(phy_ref_clk)) {
|
||||
pr_err("Cannot request auxclk3\n");
|
||||
return;
|
||||
}
|
||||
clk_set_rate(phy_ref_clk, 19200000);
|
||||
clk_prepare_enable(phy_ref_clk);
|
||||
|
||||
/* disable the power to the usb hub prior to init and reset phy+hub */
|
||||
ret = gpio_request_array(panda_ehci_gpios,
|
||||
ARRAY_SIZE(panda_ehci_gpios));
|
||||
if (ret) {
|
||||
pr_err("Unable to initialize EHCI power/reset\n");
|
||||
return;
|
||||
}
|
||||
|
||||
gpio_export(GPIO_HUB_POWER, 0);
|
||||
gpio_export(GPIO_HUB_NRESET, 0);
|
||||
gpio_set_value(GPIO_HUB_NRESET, 1);
|
||||
ret = clk_add_alias("main_clk", "nop_usb_xceiv.1", "auxclk3_ck", NULL);
|
||||
if (ret)
|
||||
pr_err("Failed to add main_clk alias to auxclk3_ck\n");
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
usbhs_init(&usbhs_bdata);
|
||||
|
||||
/* enable power to hub */
|
||||
gpio_set_value(GPIO_HUB_POWER, 1);
|
||||
}
|
||||
|
||||
static struct omap_musb_board_data musb_board_data = {
|
||||
|
|
|
|||
|
|
@ -457,14 +457,16 @@ static int __init overo_spi_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct usbhs_phy_data phy_data[] __initdata = {
|
||||
{
|
||||
.port = 2,
|
||||
.reset_gpio = OVERO_GPIO_USBH_NRESET,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = -EINVAL,
|
||||
.reset_gpio_port[1] = OVERO_GPIO_USBH_NRESET,
|
||||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
|
|
@ -501,6 +503,8 @@ static void __init overo_init(void)
|
|||
ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL);
|
||||
usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
|
||||
usb_musb_init(NULL);
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
usbhs_init(&usbhs_bdata);
|
||||
overo_spi_init();
|
||||
overo_init_smsc911x();
|
||||
|
|
|
|||
|
|
@ -92,14 +92,16 @@ static struct mtd_partition zoom_nand_partitions[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct usbhs_phy_data phy_data[] __initdata = {
|
||||
{
|
||||
.port = 2,
|
||||
.reset_gpio = ZOOM3_EHCI_RESET_GPIO,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = -EINVAL,
|
||||
.reset_gpio_port[1] = ZOOM3_EHCI_RESET_GPIO,
|
||||
.reset_gpio_port[2] = -EINVAL,
|
||||
};
|
||||
|
||||
static void __init omap_zoom_init(void)
|
||||
|
|
@ -109,6 +111,8 @@ static void __init omap_zoom_init(void)
|
|||
} else if (machine_is_omap_zoom3()) {
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
|
||||
omap_mux_init_gpio(ZOOM3_EHCI_RESET_GPIO, OMAP_PIN_OUTPUT);
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
usbhs_init(&usbhs_bdata);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -82,8 +82,7 @@ extern void omap2_init_common_infrastructure(void);
|
|||
extern void omap2_sync32k_timer_init(void);
|
||||
extern void omap3_sync32k_timer_init(void);
|
||||
extern void omap3_secure_sync32k_timer_init(void);
|
||||
extern void omap3_gp_gptimer_timer_init(void);
|
||||
extern void omap3_am33xx_gptimer_timer_init(void);
|
||||
extern void omap3_gptimer_timer_init(void);
|
||||
extern void omap4_local_timer_init(void);
|
||||
extern void omap5_realtime_timer_init(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -74,14 +74,6 @@ static int omap2_nand_gpmc_retime(
|
|||
t.cs_wr_off = gpmc_t->cs_wr_off;
|
||||
t.wr_cycle = gpmc_t->wr_cycle;
|
||||
|
||||
/* Configure GPMC */
|
||||
if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
|
||||
gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1);
|
||||
else
|
||||
gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
|
||||
gpmc_cs_configure(gpmc_nand_data->cs,
|
||||
GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
|
||||
gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_WP, 0);
|
||||
err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
|
||||
if (err)
|
||||
return err;
|
||||
|
|
@ -115,14 +107,18 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
|
|||
struct gpmc_timings *gpmc_t)
|
||||
{
|
||||
int err = 0;
|
||||
struct gpmc_settings s;
|
||||
struct device *dev = &gpmc_nand_device.dev;
|
||||
|
||||
memset(&s, 0, sizeof(struct gpmc_settings));
|
||||
|
||||
gpmc_nand_device.dev.platform_data = gpmc_nand_data;
|
||||
|
||||
err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
|
||||
(unsigned long *)&gpmc_nand_resource[0].start);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "Cannot request GPMC CS\n");
|
||||
dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
|
||||
gpmc_nand_data->cs, err);
|
||||
return err;
|
||||
}
|
||||
|
||||
|
|
@ -140,11 +136,31 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
|
|||
dev_err(dev, "Unable to set gpmc timings: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable RD PIN Monitoring Reg */
|
||||
if (gpmc_nand_data->dev_ready) {
|
||||
gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1);
|
||||
if (gpmc_nand_data->of_node) {
|
||||
gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
|
||||
} else {
|
||||
s.device_nand = true;
|
||||
|
||||
/* Enable RD PIN Monitoring Reg */
|
||||
if (gpmc_nand_data->dev_ready) {
|
||||
s.wait_on_read = true;
|
||||
s.wait_on_write = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
|
||||
s.device_width = GPMC_DEVWIDTH_16BIT;
|
||||
else
|
||||
s.device_width = GPMC_DEVWIDTH_8BIT;
|
||||
|
||||
err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
|
||||
if (err < 0)
|
||||
goto out_free_cs;
|
||||
|
||||
err = gpmc_configure(GPMC_CONFIG_WP, 0);
|
||||
if (err < 0)
|
||||
goto out_free_cs;
|
||||
}
|
||||
|
||||
gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
|
||||
|
|
|
|||
|
|
@ -47,11 +47,23 @@ static struct platform_device gpmc_onenand_device = {
|
|||
.resource = &gpmc_onenand_resource,
|
||||
};
|
||||
|
||||
static struct gpmc_timings omap2_onenand_calc_async_timings(void)
|
||||
static struct gpmc_settings onenand_async = {
|
||||
.device_width = GPMC_DEVWIDTH_16BIT,
|
||||
.mux_add_data = GPMC_MUX_AD,
|
||||
};
|
||||
|
||||
static struct gpmc_settings onenand_sync = {
|
||||
.burst_read = true,
|
||||
.burst_wrap = true,
|
||||
.burst_len = GPMC_BURST_16,
|
||||
.device_width = GPMC_DEVWIDTH_16BIT,
|
||||
.mux_add_data = GPMC_MUX_AD,
|
||||
.wait_pin = 0,
|
||||
};
|
||||
|
||||
static void omap2_onenand_calc_async_timings(struct gpmc_timings *t)
|
||||
{
|
||||
struct gpmc_device_timings dev_t;
|
||||
struct gpmc_timings t;
|
||||
|
||||
const int t_cer = 15;
|
||||
const int t_avdp = 12;
|
||||
const int t_aavdh = 7;
|
||||
|
|
@ -64,7 +76,6 @@ static struct gpmc_timings omap2_onenand_calc_async_timings(void)
|
|||
|
||||
memset(&dev_t, 0, sizeof(dev_t));
|
||||
|
||||
dev_t.mux = true;
|
||||
dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
|
||||
dev_t.t_avdp_w = dev_t.t_avdp_r;
|
||||
dev_t.t_aavdh = t_aavdh * 1000;
|
||||
|
|
@ -76,19 +87,7 @@ static struct gpmc_timings omap2_onenand_calc_async_timings(void)
|
|||
dev_t.t_wpl = t_wpl * 1000;
|
||||
dev_t.t_wph = t_wph * 1000;
|
||||
|
||||
gpmc_calc_timings(&t, &dev_t);
|
||||
|
||||
return t;
|
||||
}
|
||||
|
||||
static int gpmc_set_async_mode(int cs, struct gpmc_timings *t)
|
||||
{
|
||||
/* Configure GPMC for asynchronous read */
|
||||
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
|
||||
GPMC_CONFIG1_DEVICESIZE_16 |
|
||||
GPMC_CONFIG1_MUXADDDATA);
|
||||
|
||||
return gpmc_cs_set_timings(cs, t);
|
||||
gpmc_calc_timings(t, &onenand_async, &dev_t);
|
||||
}
|
||||
|
||||
static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
|
||||
|
|
@ -158,12 +157,11 @@ static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
|
|||
return freq;
|
||||
}
|
||||
|
||||
static struct gpmc_timings
|
||||
omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
|
||||
int freq)
|
||||
static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
|
||||
unsigned int flags,
|
||||
int freq)
|
||||
{
|
||||
struct gpmc_device_timings dev_t;
|
||||
struct gpmc_timings t;
|
||||
const int t_cer = 15;
|
||||
const int t_avdp = 12;
|
||||
const int t_cez = 20; /* max of t_cez, t_oez */
|
||||
|
|
@ -172,9 +170,9 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
|
|||
int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
|
||||
int div, gpmc_clk_ns;
|
||||
|
||||
if (cfg->flags & ONENAND_SYNC_READ)
|
||||
if (flags & ONENAND_SYNC_READ)
|
||||
onenand_flags = ONENAND_FLAG_SYNCREAD;
|
||||
else if (cfg->flags & ONENAND_SYNC_READWRITE)
|
||||
else if (flags & ONENAND_SYNC_READWRITE)
|
||||
onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
|
||||
|
||||
switch (freq) {
|
||||
|
|
@ -239,10 +237,11 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
|
|||
/* Set synchronous read timings */
|
||||
memset(&dev_t, 0, sizeof(dev_t));
|
||||
|
||||
dev_t.mux = true;
|
||||
dev_t.sync_read = true;
|
||||
if (onenand_flags & ONENAND_FLAG_SYNCREAD)
|
||||
onenand_sync.sync_read = true;
|
||||
if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
|
||||
dev_t.sync_write = true;
|
||||
onenand_sync.sync_write = true;
|
||||
onenand_sync.burst_write = true;
|
||||
} else {
|
||||
dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
|
||||
dev_t.t_wpl = t_wpl * 1000;
|
||||
|
|
@ -265,32 +264,7 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
|
|||
dev_t.cyc_aavdh_oe = 1;
|
||||
dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
|
||||
|
||||
gpmc_calc_timings(&t, &dev_t);
|
||||
|
||||
return t;
|
||||
}
|
||||
|
||||
static int gpmc_set_sync_mode(int cs, struct gpmc_timings *t)
|
||||
{
|
||||
unsigned sync_read = onenand_flags & ONENAND_FLAG_SYNCREAD;
|
||||
unsigned sync_write = onenand_flags & ONENAND_FLAG_SYNCWRITE;
|
||||
|
||||
/* Configure GPMC for synchronous read */
|
||||
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
|
||||
GPMC_CONFIG1_WRAPBURST_SUPP |
|
||||
GPMC_CONFIG1_READMULTIPLE_SUPP |
|
||||
(sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) |
|
||||
(sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
|
||||
(sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
|
||||
GPMC_CONFIG1_PAGE_LEN(2) |
|
||||
(cpu_is_omap34xx() ? 0 :
|
||||
(GPMC_CONFIG1_WAIT_READ_MON |
|
||||
GPMC_CONFIG1_WAIT_PIN_SEL(0))) |
|
||||
GPMC_CONFIG1_DEVICESIZE_16 |
|
||||
GPMC_CONFIG1_DEVICETYPE_NOR |
|
||||
GPMC_CONFIG1_MUXADDDATA);
|
||||
|
||||
return gpmc_cs_set_timings(cs, t);
|
||||
gpmc_calc_timings(t, &onenand_sync, &dev_t);
|
||||
}
|
||||
|
||||
static int omap2_onenand_setup_async(void __iomem *onenand_base)
|
||||
|
|
@ -298,11 +272,19 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base)
|
|||
struct gpmc_timings t;
|
||||
int ret;
|
||||
|
||||
if (gpmc_onenand_data->of_node)
|
||||
gpmc_read_settings_dt(gpmc_onenand_data->of_node,
|
||||
&onenand_async);
|
||||
|
||||
omap2_onenand_set_async_mode(onenand_base);
|
||||
|
||||
t = omap2_onenand_calc_async_timings();
|
||||
omap2_onenand_calc_async_timings(&t);
|
||||
|
||||
ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t);
|
||||
ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
|
@ -322,9 +304,25 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
|
|||
set_onenand_cfg(onenand_base);
|
||||
}
|
||||
|
||||
t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq);
|
||||
if (gpmc_onenand_data->of_node) {
|
||||
gpmc_read_settings_dt(gpmc_onenand_data->of_node,
|
||||
&onenand_sync);
|
||||
} else {
|
||||
/*
|
||||
* FIXME: Appears to be legacy code from initial ONENAND commit.
|
||||
* Unclear what boards this is for and if this can be removed.
|
||||
*/
|
||||
if (!cpu_is_omap34xx())
|
||||
onenand_sync.wait_on_read = true;
|
||||
}
|
||||
|
||||
ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t);
|
||||
omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq);
|
||||
|
||||
ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
|
@ -359,6 +357,7 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
|
|||
void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
|
||||
{
|
||||
int err;
|
||||
struct device *dev = &gpmc_onenand_device.dev;
|
||||
|
||||
gpmc_onenand_data = _onenand_data;
|
||||
gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
|
||||
|
|
@ -366,7 +365,7 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
|
|||
|
||||
if (cpu_is_omap24xx() &&
|
||||
(gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
|
||||
printk(KERN_ERR "Onenand using only SYNC_READ on 24xx\n");
|
||||
dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n");
|
||||
gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
|
||||
gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
|
||||
}
|
||||
|
|
@ -379,7 +378,8 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
|
|||
err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
|
||||
(unsigned long *)&gpmc_onenand_resource.start);
|
||||
if (err < 0) {
|
||||
pr_err("%s: Cannot request GPMC CS\n", __func__);
|
||||
dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
|
||||
gpmc_onenand_data->cs, err);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -387,7 +387,7 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
|
|||
ONENAND_IO_SIZE - 1;
|
||||
|
||||
if (platform_device_register(&gpmc_onenand_device) < 0) {
|
||||
pr_err("%s: Unable to register OneNAND device\n", __func__);
|
||||
dev_err(dev, "Unable to register OneNAND device\n");
|
||||
gpmc_cs_free(gpmc_onenand_data->cs);
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -49,6 +49,10 @@ static struct platform_device gpmc_smc91x_device = {
|
|||
.resource = gpmc_smc91x_resources,
|
||||
};
|
||||
|
||||
static struct gpmc_settings smc91x_settings = {
|
||||
.device_width = GPMC_DEVWIDTH_16BIT,
|
||||
};
|
||||
|
||||
/*
|
||||
* Set the gpmc timings for smc91c96. The timings are taken
|
||||
* from the data sheet available at:
|
||||
|
|
@ -67,18 +71,6 @@ static int smc91c96_gpmc_retime(void)
|
|||
const int t7 = 5; /* Figure 12.4 write */
|
||||
const int t8 = 5; /* Figure 12.4 write */
|
||||
const int t20 = 185; /* Figure 12.2 read and 12.4 write */
|
||||
u32 l;
|
||||
|
||||
l = GPMC_CONFIG1_DEVICESIZE_16;
|
||||
if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
|
||||
l |= GPMC_CONFIG1_MUXADDDATA;
|
||||
if (gpmc_cfg->flags & GPMC_READ_MON)
|
||||
l |= GPMC_CONFIG1_WAIT_READ_MON;
|
||||
if (gpmc_cfg->flags & GPMC_WRITE_MON)
|
||||
l |= GPMC_CONFIG1_WAIT_WRITE_MON;
|
||||
if (gpmc_cfg->wait_pin)
|
||||
l |= GPMC_CONFIG1_WAIT_PIN_SEL(gpmc_cfg->wait_pin);
|
||||
gpmc_cs_write_reg(gpmc_cfg->cs, GPMC_CS_CONFIG1, l);
|
||||
|
||||
/*
|
||||
* FIXME: Calculate the address and data bus muxed timings.
|
||||
|
|
@ -104,7 +96,7 @@ static int smc91c96_gpmc_retime(void)
|
|||
dev_t.t_cez_w = t4_w * 1000;
|
||||
dev_t.t_wr_cycle = (t20 - t3) * 1000;
|
||||
|
||||
gpmc_calc_timings(&t, &dev_t);
|
||||
gpmc_calc_timings(&t, &smc91x_settings, &dev_t);
|
||||
|
||||
return gpmc_cs_set_timings(gpmc_cfg->cs, &t);
|
||||
}
|
||||
|
|
@ -133,6 +125,18 @@ void __init gpmc_smc91x_init(struct omap_smc91x_platform_data *board_data)
|
|||
gpmc_smc91x_resources[0].end = cs_mem_base + 0x30f;
|
||||
gpmc_smc91x_resources[1].flags |= (gpmc_cfg->flags & IRQF_TRIGGER_MASK);
|
||||
|
||||
if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
|
||||
smc91x_settings.mux_add_data = GPMC_MUX_AD;
|
||||
if (gpmc_cfg->flags & GPMC_READ_MON)
|
||||
smc91x_settings.wait_on_read = true;
|
||||
if (gpmc_cfg->flags & GPMC_WRITE_MON)
|
||||
smc91x_settings.wait_on_write = true;
|
||||
if (gpmc_cfg->wait_pin)
|
||||
smc91x_settings.wait_pin = gpmc_cfg->wait_pin;
|
||||
ret = gpmc_cs_program_settings(gpmc_cfg->cs, &smc91x_settings);
|
||||
if (ret < 0)
|
||||
goto free1;
|
||||
|
||||
if (gpmc_cfg->retime) {
|
||||
ret = gpmc_cfg->retime();
|
||||
if (ret != 0)
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_mtd.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
|
|
@ -91,9 +92,7 @@
|
|||
#define GPMC_CS_SIZE 0x30
|
||||
#define GPMC_BCH_SIZE 0x10
|
||||
|
||||
#define GPMC_MEM_START 0x00000000
|
||||
#define GPMC_MEM_END 0x3FFFFFFF
|
||||
#define BOOT_ROM_SPACE 0x100000 /* 1MB */
|
||||
|
||||
#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
|
||||
#define GPMC_SECTION_SHIFT 28 /* 128 MB */
|
||||
|
|
@ -107,6 +106,9 @@
|
|||
|
||||
#define GPMC_HAS_WR_ACCESS 0x1
|
||||
#define GPMC_HAS_WR_DATA_MUX_BUS 0x2
|
||||
#define GPMC_HAS_MUX_AAD 0x4
|
||||
|
||||
#define GPMC_NR_WAITPINS 4
|
||||
|
||||
/* XXX: Only NAND irq has been considered,currently these are the only ones used
|
||||
*/
|
||||
|
|
@ -153,6 +155,7 @@ static struct resource gpmc_cs_mem[GPMC_CS_NUM];
|
|||
static DEFINE_SPINLOCK(gpmc_mem_lock);
|
||||
/* Define chip-selects as reserved by default until probe completes */
|
||||
static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
|
||||
static unsigned int gpmc_nr_waitpins;
|
||||
static struct device *gpmc_dev;
|
||||
static int gpmc_irq;
|
||||
static resource_size_t phys_base, mem_size;
|
||||
|
|
@ -181,7 +184,7 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val)
|
|||
__raw_writel(val, reg_addr);
|
||||
}
|
||||
|
||||
u32 gpmc_cs_read_reg(int cs, int idx)
|
||||
static u32 gpmc_cs_read_reg(int cs, int idx)
|
||||
{
|
||||
void __iomem *reg_addr;
|
||||
|
||||
|
|
@ -190,7 +193,7 @@ u32 gpmc_cs_read_reg(int cs, int idx)
|
|||
}
|
||||
|
||||
/* TODO: Add support for gpmc_fck to clock framework and use it */
|
||||
unsigned long gpmc_get_fclk_period(void)
|
||||
static unsigned long gpmc_get_fclk_period(void)
|
||||
{
|
||||
unsigned long rate = clk_get_rate(gpmc_l3_clk);
|
||||
|
||||
|
|
@ -205,7 +208,7 @@ unsigned long gpmc_get_fclk_period(void)
|
|||
return rate;
|
||||
}
|
||||
|
||||
unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
|
||||
static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
|
||||
{
|
||||
unsigned long tick_ps;
|
||||
|
||||
|
|
@ -215,7 +218,7 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
|
|||
return (time_ns * 1000 + tick_ps - 1) / tick_ps;
|
||||
}
|
||||
|
||||
unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
|
||||
static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
|
||||
{
|
||||
unsigned long tick_ps;
|
||||
|
||||
|
|
@ -230,13 +233,6 @@ unsigned int gpmc_ticks_to_ns(unsigned int ticks)
|
|||
return ticks * gpmc_get_fclk_period() / 1000;
|
||||
}
|
||||
|
||||
unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
|
||||
{
|
||||
unsigned long ticks = gpmc_ns_to_ticks(time_ns);
|
||||
|
||||
return ticks * gpmc_get_fclk_period() / 1000;
|
||||
}
|
||||
|
||||
static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
|
||||
{
|
||||
return ticks * gpmc_get_fclk_period();
|
||||
|
|
@ -405,11 +401,18 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
|
||||
static int gpmc_cs_enable_mem(int cs, u32 base, u32 size)
|
||||
{
|
||||
u32 l;
|
||||
u32 mask;
|
||||
|
||||
/*
|
||||
* Ensure that base address is aligned on a
|
||||
* boundary equal to or greater than size.
|
||||
*/
|
||||
if (base & (size - 1))
|
||||
return -EINVAL;
|
||||
|
||||
mask = (1 << GPMC_SECTION_SHIFT) - size;
|
||||
l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
|
||||
l &= ~0x3f;
|
||||
|
|
@ -418,6 +421,8 @@ static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
|
|||
l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
|
||||
l |= GPMC_CONFIG7_CSVALID;
|
||||
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void gpmc_cs_disable_mem(int cs)
|
||||
|
|
@ -448,22 +453,14 @@ static int gpmc_cs_mem_enabled(int cs)
|
|||
return l & GPMC_CONFIG7_CSVALID;
|
||||
}
|
||||
|
||||
int gpmc_cs_set_reserved(int cs, int reserved)
|
||||
static void gpmc_cs_set_reserved(int cs, int reserved)
|
||||
{
|
||||
if (cs > GPMC_CS_NUM)
|
||||
return -ENODEV;
|
||||
|
||||
gpmc_cs_map &= ~(1 << cs);
|
||||
gpmc_cs_map |= (reserved ? 1 : 0) << cs;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int gpmc_cs_reserved(int cs)
|
||||
static bool gpmc_cs_reserved(int cs)
|
||||
{
|
||||
if (cs > GPMC_CS_NUM)
|
||||
return -ENODEV;
|
||||
|
||||
return gpmc_cs_map & (1 << cs);
|
||||
}
|
||||
|
||||
|
|
@ -510,6 +507,39 @@ static int gpmc_cs_delete_mem(int cs)
|
|||
return r;
|
||||
}
|
||||
|
||||
/**
|
||||
* gpmc_cs_remap - remaps a chip-select physical base address
|
||||
* @cs: chip-select to remap
|
||||
* @base: physical base address to re-map chip-select to
|
||||
*
|
||||
* Re-maps a chip-select to a new physical base address specified by
|
||||
* "base". Returns 0 on success and appropriate negative error code
|
||||
* on failure.
|
||||
*/
|
||||
static int gpmc_cs_remap(int cs, u32 base)
|
||||
{
|
||||
int ret;
|
||||
u32 old_base, size;
|
||||
|
||||
if (cs > GPMC_CS_NUM)
|
||||
return -ENODEV;
|
||||
gpmc_cs_get_memconf(cs, &old_base, &size);
|
||||
if (base == old_base)
|
||||
return 0;
|
||||
gpmc_cs_disable_mem(cs);
|
||||
ret = gpmc_cs_delete_mem(cs);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
ret = gpmc_cs_insert_mem(cs, base, size);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
ret = gpmc_cs_enable_mem(cs, base, size);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
|
||||
{
|
||||
struct resource *res = &gpmc_cs_mem[cs];
|
||||
|
|
@ -535,7 +565,12 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
|
|||
if (r < 0)
|
||||
goto out;
|
||||
|
||||
gpmc_cs_enable_mem(cs, res->start, resource_size(res));
|
||||
r = gpmc_cs_enable_mem(cs, res->start, resource_size(res));
|
||||
if (r < 0) {
|
||||
release_resource(res);
|
||||
goto out;
|
||||
}
|
||||
|
||||
*base = res->start;
|
||||
gpmc_cs_set_reserved(cs, 1);
|
||||
out:
|
||||
|
|
@ -561,16 +596,14 @@ void gpmc_cs_free(int cs)
|
|||
EXPORT_SYMBOL(gpmc_cs_free);
|
||||
|
||||
/**
|
||||
* gpmc_cs_configure - write request to configure gpmc
|
||||
* @cs: chip select number
|
||||
* gpmc_configure - write request to configure gpmc
|
||||
* @cmd: command type
|
||||
* @wval: value to write
|
||||
* @return status of the operation
|
||||
*/
|
||||
int gpmc_cs_configure(int cs, int cmd, int wval)
|
||||
int gpmc_configure(int cmd, int wval)
|
||||
{
|
||||
int err = 0;
|
||||
u32 regval = 0;
|
||||
u32 regval;
|
||||
|
||||
switch (cmd) {
|
||||
case GPMC_ENABLE_IRQ:
|
||||
|
|
@ -590,43 +623,14 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
|
|||
gpmc_write_reg(GPMC_CONFIG, regval);
|
||||
break;
|
||||
|
||||
case GPMC_CONFIG_RDY_BSY:
|
||||
regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
|
||||
if (wval)
|
||||
regval |= WR_RD_PIN_MONITORING;
|
||||
else
|
||||
regval &= ~WR_RD_PIN_MONITORING;
|
||||
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
|
||||
break;
|
||||
|
||||
case GPMC_CONFIG_DEV_SIZE:
|
||||
regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
|
||||
|
||||
/* clear 2 target bits */
|
||||
regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
|
||||
|
||||
/* set the proper value */
|
||||
regval |= GPMC_CONFIG1_DEVICESIZE(wval);
|
||||
|
||||
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
|
||||
break;
|
||||
|
||||
case GPMC_CONFIG_DEV_TYPE:
|
||||
regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
|
||||
regval |= GPMC_CONFIG1_DEVICETYPE(wval);
|
||||
if (wval == GPMC_DEVICETYPE_NOR)
|
||||
regval |= GPMC_CONFIG1_MUXADDDATA;
|
||||
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
|
||||
break;
|
||||
|
||||
default:
|
||||
printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
|
||||
err = -EINVAL;
|
||||
pr_err("%s: command not supported\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return err;
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(gpmc_cs_configure);
|
||||
EXPORT_SYMBOL(gpmc_configure);
|
||||
|
||||
void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
|
||||
{
|
||||
|
|
@ -781,16 +785,16 @@ static void gpmc_mem_exit(void)
|
|||
|
||||
}
|
||||
|
||||
static int gpmc_mem_init(void)
|
||||
static void gpmc_mem_init(void)
|
||||
{
|
||||
int cs, rc;
|
||||
unsigned long boot_rom_space = 0;
|
||||
int cs;
|
||||
|
||||
/* never allocate the first page, to facilitate bug detection;
|
||||
* even if we didn't boot from ROM.
|
||||
/*
|
||||
* The first 1MB of GPMC address space is typically mapped to
|
||||
* the internal ROM. Never allocate the first page, to
|
||||
* facilitate bug detection; even if we didn't boot from ROM.
|
||||
*/
|
||||
boot_rom_space = BOOT_ROM_SPACE;
|
||||
gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
|
||||
gpmc_mem_root.start = SZ_1M;
|
||||
gpmc_mem_root.end = GPMC_MEM_END;
|
||||
|
||||
/* Reserve all regions that has been set up by bootloader */
|
||||
|
|
@ -800,16 +804,12 @@ static int gpmc_mem_init(void)
|
|||
if (!gpmc_cs_mem_enabled(cs))
|
||||
continue;
|
||||
gpmc_cs_get_memconf(cs, &base, &size);
|
||||
rc = gpmc_cs_insert_mem(cs, base, size);
|
||||
if (rc < 0) {
|
||||
while (--cs >= 0)
|
||||
if (gpmc_cs_mem_enabled(cs))
|
||||
gpmc_cs_delete_mem(cs);
|
||||
return rc;
|
||||
if (gpmc_cs_insert_mem(cs, base, size)) {
|
||||
pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
|
||||
__func__, cs, base, base + size);
|
||||
gpmc_cs_disable_mem(cs);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
|
||||
|
|
@ -825,9 +825,9 @@ static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
|
|||
|
||||
/* XXX: can the cycles be avoided ? */
|
||||
static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
|
||||
struct gpmc_device_timings *dev_t)
|
||||
struct gpmc_device_timings *dev_t,
|
||||
bool mux)
|
||||
{
|
||||
bool mux = dev_t->mux;
|
||||
u32 temp;
|
||||
|
||||
/* adv_rd_off */
|
||||
|
|
@ -880,9 +880,9 @@ static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
|
|||
}
|
||||
|
||||
static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
|
||||
struct gpmc_device_timings *dev_t)
|
||||
struct gpmc_device_timings *dev_t,
|
||||
bool mux)
|
||||
{
|
||||
bool mux = dev_t->mux;
|
||||
u32 temp;
|
||||
|
||||
/* adv_wr_off */
|
||||
|
|
@ -942,9 +942,9 @@ static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
|
|||
}
|
||||
|
||||
static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
|
||||
struct gpmc_device_timings *dev_t)
|
||||
struct gpmc_device_timings *dev_t,
|
||||
bool mux)
|
||||
{
|
||||
bool mux = dev_t->mux;
|
||||
u32 temp;
|
||||
|
||||
/* adv_rd_off */
|
||||
|
|
@ -982,9 +982,9 @@ static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
|
|||
}
|
||||
|
||||
static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
|
||||
struct gpmc_device_timings *dev_t)
|
||||
struct gpmc_device_timings *dev_t,
|
||||
bool mux)
|
||||
{
|
||||
bool mux = dev_t->mux;
|
||||
u32 temp;
|
||||
|
||||
/* adv_wr_off */
|
||||
|
|
@ -1054,7 +1054,8 @@ static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
|
|||
}
|
||||
|
||||
static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
|
||||
struct gpmc_device_timings *dev_t)
|
||||
struct gpmc_device_timings *dev_t,
|
||||
bool sync)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
|
|
@ -1068,7 +1069,7 @@ static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
|
|||
gpmc_t->cs_on + dev_t->t_ce_avd);
|
||||
gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
|
||||
|
||||
if (dev_t->sync_write || dev_t->sync_read)
|
||||
if (sync)
|
||||
gpmc_calc_sync_common_timings(gpmc_t, dev_t);
|
||||
|
||||
return 0;
|
||||
|
|
@ -1103,21 +1104,29 @@ static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
|
|||
}
|
||||
|
||||
int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
|
||||
struct gpmc_device_timings *dev_t)
|
||||
struct gpmc_settings *gpmc_s,
|
||||
struct gpmc_device_timings *dev_t)
|
||||
{
|
||||
bool mux = false, sync = false;
|
||||
|
||||
if (gpmc_s) {
|
||||
mux = gpmc_s->mux_add_data ? true : false;
|
||||
sync = (gpmc_s->sync_read || gpmc_s->sync_write);
|
||||
}
|
||||
|
||||
memset(gpmc_t, 0, sizeof(*gpmc_t));
|
||||
|
||||
gpmc_calc_common_timings(gpmc_t, dev_t);
|
||||
gpmc_calc_common_timings(gpmc_t, dev_t, sync);
|
||||
|
||||
if (dev_t->sync_read)
|
||||
gpmc_calc_sync_read_timings(gpmc_t, dev_t);
|
||||
if (gpmc_s && gpmc_s->sync_read)
|
||||
gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
|
||||
else
|
||||
gpmc_calc_async_read_timings(gpmc_t, dev_t);
|
||||
gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
|
||||
|
||||
if (dev_t->sync_write)
|
||||
gpmc_calc_sync_write_timings(gpmc_t, dev_t);
|
||||
if (gpmc_s && gpmc_s->sync_write)
|
||||
gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
|
||||
else
|
||||
gpmc_calc_async_write_timings(gpmc_t, dev_t);
|
||||
gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
|
||||
|
||||
/* TODO: remove, see function definition */
|
||||
gpmc_convert_ps_to_ns(gpmc_t);
|
||||
|
|
@ -1125,6 +1134,90 @@ int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* gpmc_cs_program_settings - programs non-timing related settings
|
||||
* @cs: GPMC chip-select to program
|
||||
* @p: pointer to GPMC settings structure
|
||||
*
|
||||
* Programs non-timing related settings for a GPMC chip-select, such as
|
||||
* bus-width, burst configuration, etc. Function should be called once
|
||||
* for each chip-select that is being used and must be called before
|
||||
* calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
|
||||
* register will be initialised to zero by this function. Returns 0 on
|
||||
* success and appropriate negative error code on failure.
|
||||
*/
|
||||
int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
|
||||
{
|
||||
u32 config1;
|
||||
|
||||
if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
|
||||
pr_err("%s: invalid width %d!", __func__, p->device_width);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Address-data multiplexing not supported for NAND devices */
|
||||
if (p->device_nand && p->mux_add_data) {
|
||||
pr_err("%s: invalid configuration!\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if ((p->mux_add_data > GPMC_MUX_AD) ||
|
||||
((p->mux_add_data == GPMC_MUX_AAD) &&
|
||||
!(gpmc_capability & GPMC_HAS_MUX_AAD))) {
|
||||
pr_err("%s: invalid multiplex configuration!\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Page/burst mode supports lengths of 4, 8 and 16 bytes */
|
||||
if (p->burst_read || p->burst_write) {
|
||||
switch (p->burst_len) {
|
||||
case GPMC_BURST_4:
|
||||
case GPMC_BURST_8:
|
||||
case GPMC_BURST_16:
|
||||
break;
|
||||
default:
|
||||
pr_err("%s: invalid page/burst-length (%d)\n",
|
||||
__func__, p->burst_len);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
if ((p->wait_on_read || p->wait_on_write) &&
|
||||
(p->wait_pin > gpmc_nr_waitpins)) {
|
||||
pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
|
||||
|
||||
if (p->sync_read)
|
||||
config1 |= GPMC_CONFIG1_READTYPE_SYNC;
|
||||
if (p->sync_write)
|
||||
config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
|
||||
if (p->wait_on_read)
|
||||
config1 |= GPMC_CONFIG1_WAIT_READ_MON;
|
||||
if (p->wait_on_write)
|
||||
config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
|
||||
if (p->wait_on_read || p->wait_on_write)
|
||||
config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
|
||||
if (p->device_nand)
|
||||
config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
|
||||
if (p->mux_add_data)
|
||||
config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
|
||||
if (p->burst_read)
|
||||
config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
|
||||
if (p->burst_write)
|
||||
config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
|
||||
if (p->burst_read || p->burst_write) {
|
||||
config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
|
||||
config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
|
||||
}
|
||||
|
||||
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static struct of_device_id gpmc_dt_ids[] = {
|
||||
{ .compatible = "ti,omap2420-gpmc" },
|
||||
|
|
@ -1136,70 +1229,110 @@ static struct of_device_id gpmc_dt_ids[] = {
|
|||
};
|
||||
MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
|
||||
|
||||
/**
|
||||
* gpmc_read_settings_dt - read gpmc settings from device-tree
|
||||
* @np: pointer to device-tree node for a gpmc child device
|
||||
* @p: pointer to gpmc settings structure
|
||||
*
|
||||
* Reads the GPMC settings for a GPMC child device from device-tree and
|
||||
* stores them in the GPMC settings structure passed. The GPMC settings
|
||||
* structure is initialised to zero by this function and so any
|
||||
* previously stored settings will be cleared.
|
||||
*/
|
||||
void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
|
||||
{
|
||||
memset(p, 0, sizeof(struct gpmc_settings));
|
||||
|
||||
p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
|
||||
p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
|
||||
p->device_nand = of_property_read_bool(np, "gpmc,device-nand");
|
||||
of_property_read_u32(np, "gpmc,device-width", &p->device_width);
|
||||
of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
|
||||
p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
|
||||
p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
|
||||
p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
|
||||
if (!p->burst_read && !p->burst_write)
|
||||
pr_warn("%s: page/burst-length set but not used!\n",
|
||||
__func__);
|
||||
}
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
|
||||
p->wait_on_read = of_property_read_bool(np,
|
||||
"gpmc,wait-on-read");
|
||||
p->wait_on_write = of_property_read_bool(np,
|
||||
"gpmc,wait-on-write");
|
||||
if (!p->wait_on_read && !p->wait_on_write)
|
||||
pr_warn("%s: read/write wait monitoring not enabled!\n",
|
||||
__func__);
|
||||
}
|
||||
}
|
||||
|
||||
static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
|
||||
struct gpmc_timings *gpmc_t)
|
||||
{
|
||||
u32 val;
|
||||
struct gpmc_bool_timings *p;
|
||||
|
||||
if (!np || !gpmc_t)
|
||||
return;
|
||||
|
||||
memset(gpmc_t, 0, sizeof(*gpmc_t));
|
||||
|
||||
/* minimum clock period for syncronous mode */
|
||||
if (!of_property_read_u32(np, "gpmc,sync-clk", &val))
|
||||
gpmc_t->sync_clk = val;
|
||||
of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
|
||||
|
||||
/* chip select timtings */
|
||||
if (!of_property_read_u32(np, "gpmc,cs-on", &val))
|
||||
gpmc_t->cs_on = val;
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val))
|
||||
gpmc_t->cs_rd_off = val;
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val))
|
||||
gpmc_t->cs_wr_off = val;
|
||||
of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
|
||||
of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
|
||||
of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
|
||||
|
||||
/* ADV signal timings */
|
||||
if (!of_property_read_u32(np, "gpmc,adv-on", &val))
|
||||
gpmc_t->adv_on = val;
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val))
|
||||
gpmc_t->adv_rd_off = val;
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val))
|
||||
gpmc_t->adv_wr_off = val;
|
||||
of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
|
||||
of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
|
||||
of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
|
||||
|
||||
/* WE signal timings */
|
||||
if (!of_property_read_u32(np, "gpmc,we-on", &val))
|
||||
gpmc_t->we_on = val;
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,we-off", &val))
|
||||
gpmc_t->we_off = val;
|
||||
of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
|
||||
of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
|
||||
|
||||
/* OE signal timings */
|
||||
if (!of_property_read_u32(np, "gpmc,oe-on", &val))
|
||||
gpmc_t->oe_on = val;
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,oe-off", &val))
|
||||
gpmc_t->oe_off = val;
|
||||
of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
|
||||
of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
|
||||
|
||||
/* access and cycle timings */
|
||||
if (!of_property_read_u32(np, "gpmc,page-burst-access", &val))
|
||||
gpmc_t->page_burst_access = val;
|
||||
of_property_read_u32(np, "gpmc,page-burst-access-ns",
|
||||
&gpmc_t->page_burst_access);
|
||||
of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
|
||||
of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
|
||||
of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
|
||||
of_property_read_u32(np, "gpmc,bus-turnaround-ns",
|
||||
&gpmc_t->bus_turnaround);
|
||||
of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
|
||||
&gpmc_t->cycle2cycle_delay);
|
||||
of_property_read_u32(np, "gpmc,wait-monitoring-ns",
|
||||
&gpmc_t->wait_monitoring);
|
||||
of_property_read_u32(np, "gpmc,clk-activation-ns",
|
||||
&gpmc_t->clk_activation);
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,access", &val))
|
||||
gpmc_t->access = val;
|
||||
/* only applicable to OMAP3+ */
|
||||
of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
|
||||
of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
|
||||
&gpmc_t->wr_data_mux_bus);
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,rd-cycle", &val))
|
||||
gpmc_t->rd_cycle = val;
|
||||
/* bool timing parameters */
|
||||
p = &gpmc_t->bool_timings;
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,wr-cycle", &val))
|
||||
gpmc_t->wr_cycle = val;
|
||||
|
||||
/* only for OMAP3430 */
|
||||
if (!of_property_read_u32(np, "gpmc,wr-access", &val))
|
||||
gpmc_t->wr_access = val;
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val))
|
||||
gpmc_t->wr_data_mux_bus = val;
|
||||
p->cycle2cyclediffcsen =
|
||||
of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
|
||||
p->cycle2cyclesamecsen =
|
||||
of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
|
||||
p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
|
||||
p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
|
||||
p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
|
||||
p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
|
||||
p->time_para_granularity =
|
||||
of_property_read_bool(np, "gpmc,time-para-granularity");
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MTD_NAND
|
||||
|
|
@ -1295,6 +1428,81 @@ static int gpmc_probe_onenand_child(struct platform_device *pdev,
|
|||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* gpmc_probe_generic_child - configures the gpmc for a child device
|
||||
* @pdev: pointer to gpmc platform device
|
||||
* @child: pointer to device-tree node for child device
|
||||
*
|
||||
* Allocates and configures a GPMC chip-select for a child device.
|
||||
* Returns 0 on success and appropriate negative error code on failure.
|
||||
*/
|
||||
static int gpmc_probe_generic_child(struct platform_device *pdev,
|
||||
struct device_node *child)
|
||||
{
|
||||
struct gpmc_settings gpmc_s;
|
||||
struct gpmc_timings gpmc_t;
|
||||
struct resource res;
|
||||
unsigned long base;
|
||||
int ret, cs;
|
||||
|
||||
if (of_property_read_u32(child, "reg", &cs) < 0) {
|
||||
dev_err(&pdev->dev, "%s has no 'reg' property\n",
|
||||
child->full_name);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (of_address_to_resource(child, 0, &res) < 0) {
|
||||
dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
|
||||
child->full_name);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = gpmc_cs_request(cs, resource_size(&res), &base);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* FIXME: gpmc_cs_request() will map the CS to an arbitary
|
||||
* location in the gpmc address space. When booting with
|
||||
* device-tree we want the NOR flash to be mapped to the
|
||||
* location specified in the device-tree blob. So remap the
|
||||
* CS to this location. Once DT migration is complete should
|
||||
* just make gpmc_cs_request() map a specific address.
|
||||
*/
|
||||
ret = gpmc_cs_remap(cs, res.start);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "cannot remap GPMC CS %d to 0x%x\n",
|
||||
cs, res.start);
|
||||
goto err;
|
||||
}
|
||||
|
||||
gpmc_read_settings_dt(child, &gpmc_s);
|
||||
|
||||
ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
|
||||
ret = gpmc_cs_program_settings(cs, &gpmc_s);
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
|
||||
gpmc_read_timings_dt(child, &gpmc_t);
|
||||
gpmc_cs_set_timings(cs, &gpmc_t);
|
||||
|
||||
if (of_platform_device_create(child, NULL, &pdev->dev))
|
||||
return 0;
|
||||
|
||||
dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
|
||||
ret = -ENODEV;
|
||||
|
||||
err:
|
||||
gpmc_cs_free(cs);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int gpmc_probe_dt(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
|
|
@ -1305,6 +1513,13 @@ static int gpmc_probe_dt(struct platform_device *pdev)
|
|||
if (!of_id)
|
||||
return 0;
|
||||
|
||||
ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
|
||||
&gpmc_nr_waitpins);
|
||||
if (ret < 0) {
|
||||
pr_err("%s: number of wait pins not found!\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
for_each_node_by_name(child, "nand") {
|
||||
ret = gpmc_probe_nand_child(pdev, child);
|
||||
if (ret < 0) {
|
||||
|
|
@ -1320,6 +1535,23 @@ static int gpmc_probe_dt(struct platform_device *pdev)
|
|||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
for_each_node_by_name(child, "nor") {
|
||||
ret = gpmc_probe_generic_child(pdev, child);
|
||||
if (ret < 0) {
|
||||
of_node_put(child);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
for_each_node_by_name(child, "ethernet") {
|
||||
ret = gpmc_probe_generic_child(pdev, child);
|
||||
if (ret < 0) {
|
||||
of_node_put(child);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
|
|
@ -1364,18 +1596,27 @@ static int gpmc_probe(struct platform_device *pdev)
|
|||
gpmc_dev = &pdev->dev;
|
||||
|
||||
l = gpmc_read_reg(GPMC_REVISION);
|
||||
|
||||
/*
|
||||
* FIXME: Once device-tree migration is complete the below flags
|
||||
* should be populated based upon the device-tree compatible
|
||||
* string. For now just use the IP revision. OMAP3+ devices have
|
||||
* the wr_access and wr_data_mux_bus register fields. OMAP4+
|
||||
* devices support the addr-addr-data multiplex protocol.
|
||||
*
|
||||
* GPMC IP revisions:
|
||||
* - OMAP24xx = 2.0
|
||||
* - OMAP3xxx = 5.0
|
||||
* - OMAP44xx/54xx/AM335x = 6.0
|
||||
*/
|
||||
if (GPMC_REVISION_MAJOR(l) > 0x4)
|
||||
gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
|
||||
if (GPMC_REVISION_MAJOR(l) > 0x5)
|
||||
gpmc_capability |= GPMC_HAS_MUX_AAD;
|
||||
dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
|
||||
GPMC_REVISION_MINOR(l));
|
||||
|
||||
rc = gpmc_mem_init();
|
||||
if (rc < 0) {
|
||||
clk_disable_unprepare(gpmc_l3_clk);
|
||||
clk_put(gpmc_l3_clk);
|
||||
dev_err(gpmc_dev, "failed to reserve memory\n");
|
||||
return rc;
|
||||
}
|
||||
gpmc_mem_init();
|
||||
|
||||
if (gpmc_setup_irq() < 0)
|
||||
dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
|
||||
|
|
@ -1383,6 +1624,9 @@ static int gpmc_probe(struct platform_device *pdev)
|
|||
/* Now the GPMC is initialised, unreserve the chip-selects */
|
||||
gpmc_cs_map = 0;
|
||||
|
||||
if (!pdev->dev.of_node)
|
||||
gpmc_nr_waitpins = GPMC_NR_WAITPINS;
|
||||
|
||||
rc = gpmc_probe_dt(pdev);
|
||||
if (rc < 0) {
|
||||
clk_disable_unprepare(gpmc_l3_clk);
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@
|
|||
#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
|
||||
#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
|
||||
#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
|
||||
#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
|
||||
#define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
|
||||
#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
|
||||
#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
|
||||
#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
|
||||
|
|
@ -73,6 +73,13 @@
|
|||
#define GPMC_IRQ_FIFOEVENTENABLE 0x01
|
||||
#define GPMC_IRQ_COUNT_EVENT 0x02
|
||||
|
||||
#define GPMC_BURST_4 4 /* 4 word burst */
|
||||
#define GPMC_BURST_8 8 /* 8 word burst */
|
||||
#define GPMC_BURST_16 16 /* 16 word burst */
|
||||
#define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
|
||||
#define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
|
||||
#define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
|
||||
#define GPMC_MUX_AD 2 /* Addr-Data multiplex */
|
||||
|
||||
/* bool type time settings */
|
||||
struct gpmc_bool_timings {
|
||||
|
|
@ -178,10 +185,6 @@ struct gpmc_device_timings {
|
|||
u8 cyc_wpl; /* write deassertion time in cycles */
|
||||
u32 cyc_iaa; /* initial access time in cycles */
|
||||
|
||||
bool mux; /* address & data muxed */
|
||||
bool sync_write;/* synchronous write */
|
||||
bool sync_read; /* synchronous read */
|
||||
|
||||
/* extra delays */
|
||||
bool ce_xdelay;
|
||||
bool avd_xdelay;
|
||||
|
|
@ -189,28 +192,40 @@ struct gpmc_device_timings {
|
|||
bool we_xdelay;
|
||||
};
|
||||
|
||||
struct gpmc_settings {
|
||||
bool burst_wrap; /* enables wrap bursting */
|
||||
bool burst_read; /* enables read page/burst mode */
|
||||
bool burst_write; /* enables write page/burst mode */
|
||||
bool device_nand; /* device is NAND */
|
||||
bool sync_read; /* enables synchronous reads */
|
||||
bool sync_write; /* enables synchronous writes */
|
||||
bool wait_on_read; /* monitor wait on reads */
|
||||
bool wait_on_write; /* monitor wait on writes */
|
||||
u32 burst_len; /* page/burst length */
|
||||
u32 device_width; /* device bus width (8 or 16 bit) */
|
||||
u32 mux_add_data; /* multiplex address & data */
|
||||
u32 wait_pin; /* wait-pin to be used */
|
||||
};
|
||||
|
||||
extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
|
||||
struct gpmc_device_timings *dev_t);
|
||||
struct gpmc_settings *gpmc_s,
|
||||
struct gpmc_device_timings *dev_t);
|
||||
|
||||
extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
|
||||
extern int gpmc_get_client_irq(unsigned irq_config);
|
||||
|
||||
extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
|
||||
extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
|
||||
extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
|
||||
extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
|
||||
extern unsigned long gpmc_get_fclk_period(void);
|
||||
|
||||
extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
|
||||
extern u32 gpmc_cs_read_reg(int cs, int idx);
|
||||
extern int gpmc_calc_divider(unsigned int sync_clk);
|
||||
extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
|
||||
extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
|
||||
extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
|
||||
extern void gpmc_cs_free(int cs);
|
||||
extern int gpmc_cs_set_reserved(int cs, int reserved);
|
||||
extern int gpmc_cs_reserved(int cs);
|
||||
extern void omap3_gpmc_save_context(void);
|
||||
extern void omap3_gpmc_restore_context(void);
|
||||
extern int gpmc_cs_configure(int cs, int cmd, int wval);
|
||||
extern int gpmc_configure(int cmd, int wval);
|
||||
extern void gpmc_read_settings_dt(struct device_node *np,
|
||||
struct gpmc_settings *p);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
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