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drm/i915: Add csr programming registers to dmc debugfs entry
We check these to determine firmware loading status. Include them to help to debug causes of firmware loading fails. v2: Move all CSR specific registers to i915_reg.h (Ville) v3: Rebase v4: Rebase (RPM ref) Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1446220487-32691-1-git-send-email-mika.kuoppala@intel.com Tested-by: Daniel Stone <daniels@collabora.com> # SKL Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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16e11b9946
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3 changed files with 18 additions and 16 deletions
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@ -2802,17 +2802,17 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
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csr = &dev_priv->csr;
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intel_runtime_pm_get(dev_priv);
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seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
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seq_printf(m, "path: %s\n", csr->fw_path);
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if (!csr->dmc_payload)
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return 0;
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goto out;
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seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
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CSR_VERSION_MINOR(csr->version));
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intel_runtime_pm_get(dev_priv);
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if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
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seq_printf(m, "DC3 -> DC5 count: %d\n",
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I915_READ(SKL_CSR_DC3_DC5_COUNT));
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@ -2823,6 +2823,11 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
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I915_READ(BXT_CSR_DC3_DC5_COUNT));
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}
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out:
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seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
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seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
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seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
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intel_runtime_pm_put(dev_priv);
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return 0;
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@ -5698,6 +5698,16 @@ enum skl_disp_power_wells {
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#define GAMMA_MODE_MODE_SPLIT (3 << 0)
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/* DMC/CSR */
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#define CSR_PROGRAM(i) (0x80000 + (i) * 4)
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#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
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#define CSR_HTP_ADDR_SKL 0x00500034
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#define CSR_SSP_BASE 0x8F074
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#define CSR_HTP_SKL 0x8F004
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#define CSR_LAST_WRITE 0x8F034
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#define CSR_LAST_WRITE_VALUE 0xc003b400
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/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
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#define CSR_MMIO_START_RANGE 0x80000
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#define CSR_MMIO_END_RANGE 0x8FFFF
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#define SKL_CSR_DC3_DC5_COUNT 0x80030
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#define SKL_CSR_DC5_DC6_COUNT 0x8002C
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#define BXT_CSR_DC3_DC5_COUNT 0x80038
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@ -49,21 +49,8 @@ MODULE_FIRMWARE(I915_CSR_BXT);
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#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
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/*
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* SKL CSR registers for DC5 and DC6
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*/
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#define CSR_PROGRAM(i) (0x80000 + (i) * 4)
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#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
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#define CSR_HTP_ADDR_SKL 0x00500034
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#define CSR_SSP_BASE 0x8F074
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#define CSR_HTP_SKL 0x8F004
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#define CSR_LAST_WRITE 0x8F034
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#define CSR_LAST_WRITE_VALUE 0xc003b400
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/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
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#define CSR_MAX_FW_SIZE 0x2FFF
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#define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
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#define CSR_MMIO_START_RANGE 0x80000
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#define CSR_MMIO_END_RANGE 0x8FFFF
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struct intel_css_header {
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/* 0x09 for DMC */
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