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drm/amdgpu: refine vce3.0 code and related powerplay pg code.
1. not start vce3.0 when hw_init 2. stop vce3.0 when vce idle. 3. pg mask used to ctrl power down/up vce. 4. change cg pg sequence in powerplay. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
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f1ea278d6f
commit
6fc11b0ed3
3 changed files with 36 additions and 51 deletions
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@ -230,10 +230,6 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
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struct amdgpu_ring *ring;
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struct amdgpu_ring *ring;
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int idx, r;
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int idx, r;
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vce_v3_0_override_vce_clock_gating(adev, true);
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if (!(adev->flags & AMD_IS_APU))
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amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
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ring = &adev->vce.ring[0];
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ring = &adev->vce.ring[0];
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WREG32(mmVCE_RB_RPTR, ring->wptr);
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WREG32(mmVCE_RB_RPTR, ring->wptr);
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WREG32(mmVCE_RB_WPTR, ring->wptr);
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WREG32(mmVCE_RB_WPTR, ring->wptr);
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@ -436,9 +432,9 @@ static int vce_v3_0_hw_init(void *handle)
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int r, i;
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int r, i;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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r = vce_v3_0_start(adev);
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vce_v3_0_override_vce_clock_gating(adev, true);
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if (r)
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if (!(adev->flags & AMD_IS_APU))
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return r;
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amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
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for (i = 0; i < adev->vce.num_rings; i++)
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for (i = 0; i < adev->vce.num_rings; i++)
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adev->vce.ring[i].ready = false;
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adev->vce.ring[i].ready = false;
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@ -766,12 +762,11 @@ static int vce_v3_0_set_powergating_state(void *handle,
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int ret = 0;
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int ret = 0;
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if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
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return 0;
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if (state == AMD_PG_STATE_GATE) {
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if (state == AMD_PG_STATE_GATE) {
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ret = vce_v3_0_stop(adev);
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if (ret)
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goto out;
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adev->vce.is_powergated = true;
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adev->vce.is_powergated = true;
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/* XXX do we need a vce_v3_0_stop()? */
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} else {
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} else {
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ret = vce_v3_0_start(adev);
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ret = vce_v3_0_start(adev);
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if (ret)
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if (ret)
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@ -190,47 +190,34 @@ int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
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{
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{
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struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
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struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
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if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
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if (bgate) {
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PHM_PlatformCaps_VCEPowerGating)) {
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cgs_set_powergating_state(
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if (cz_hwmgr->vce_power_gated != bgate) {
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hwmgr->device,
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if (bgate) {
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AMD_IP_BLOCK_TYPE_VCE,
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cgs_set_clockgating_state(
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AMD_PG_STATE_GATE);
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hwmgr->device,
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cgs_set_clockgating_state(
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AMD_IP_BLOCK_TYPE_VCE,
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hwmgr->device,
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AMD_CG_STATE_GATE);
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AMD_IP_BLOCK_TYPE_VCE,
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cgs_set_powergating_state(
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AMD_CG_STATE_GATE);
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hwmgr->device,
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cz_enable_disable_vce_dpm(hwmgr, false);
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AMD_IP_BLOCK_TYPE_VCE,
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cz_dpm_powerdown_vce(hwmgr);
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AMD_PG_STATE_GATE);
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cz_hwmgr->vce_power_gated = true;
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cz_enable_disable_vce_dpm(hwmgr, false);
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cz_dpm_powerdown_vce(hwmgr);
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cz_hwmgr->vce_power_gated = true;
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} else {
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cz_dpm_powerup_vce(hwmgr);
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cz_hwmgr->vce_power_gated = false;
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cgs_set_powergating_state(
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hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_UNGATE);
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cgs_set_clockgating_state(
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hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_PG_STATE_UNGATE);
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cz_dpm_update_vce_dpm(hwmgr);
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cz_enable_disable_vce_dpm(hwmgr, true);
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return 0;
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}
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}
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} else {
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} else {
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cz_hwmgr->vce_power_gated = bgate;
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cz_dpm_powerup_vce(hwmgr);
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cz_hwmgr->vce_power_gated = false;
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cgs_set_clockgating_state(
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hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_PG_STATE_UNGATE);
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cgs_set_powergating_state(
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hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_UNGATE);
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cz_dpm_update_vce_dpm(hwmgr);
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cz_dpm_update_vce_dpm(hwmgr);
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cz_enable_disable_vce_dpm(hwmgr, !bgate);
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cz_enable_disable_vce_dpm(hwmgr, true);
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return 0;
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return 0;
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}
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}
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if (!cz_hwmgr->vce_power_gated)
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cz_dpm_update_vce_dpm(hwmgr);
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return 0;
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return 0;
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}
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}
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@ -173,12 +173,12 @@ int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
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{
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{
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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if (data->vce_power_gated == bgate)
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return 0;
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data->vce_power_gated = bgate;
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data->vce_power_gated = bgate;
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if (bgate) {
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if (bgate) {
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cgs_set_powergating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_PG_STATE_UNGATE);
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cgs_set_clockgating_state(hwmgr->device,
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cgs_set_clockgating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_GATE);
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AMD_CG_STATE_GATE);
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@ -186,10 +186,13 @@ int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
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smu7_powerdown_vce(hwmgr);
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smu7_powerdown_vce(hwmgr);
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} else {
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} else {
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smu7_powerup_vce(hwmgr);
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smu7_powerup_vce(hwmgr);
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smu7_update_vce_dpm(hwmgr, false);
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cgs_set_clockgating_state(hwmgr->device,
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cgs_set_clockgating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_UNGATE);
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AMD_CG_STATE_UNGATE);
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cgs_set_powergating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_PG_STATE_UNGATE);
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smu7_update_vce_dpm(hwmgr, false);
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}
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}
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return 0;
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return 0;
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}
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}
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