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wifi: wilc1000: add SPI commands retry mechanism
In some situations like, chip wake-up with powersave enabled, SPI commands are failing temporarily. Reissuing commands after reset helps to overcome the failure. So, add the retry limit and reset command sequence API for read/write SPI commands. Signed-off-by: Amisha Patel <amisha.patel@microchip.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20230724163955.4583-1-amisha.patel@microchip.com
This commit is contained in:
Amisha Patel
Kalle Valo
parent
1195852816
commit
6fd879f978
1 changed files with 104 additions and 46 deletions
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@ -74,6 +74,7 @@ static int wilc_spi_reset(struct wilc *wilc);
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#define CMD_SINGLE_READ 0xca
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#define CMD_RESET 0xcf
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#define SPI_RETRY_MAX_LIMIT 10
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#define SPI_ENABLE_VMM_RETRY_LIMIT 2
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/* SPI response fields (section 11.1.2 in ATWILC1000 User Guide): */
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@ -830,59 +831,91 @@ static int wilc_spi_special_cmd(struct wilc *wilc, u8 cmd)
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return 0;
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}
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static void wilc_spi_reset_cmd_sequence(struct wilc *wl, u8 attempt, u32 addr)
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{
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struct spi_device *spi = to_spi_device(wl->dev);
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struct wilc_spi *spi_priv = wl->bus_data;
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if (!spi_priv->probing_crc)
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dev_err(&spi->dev, "Reset and retry %d %x\n", attempt, addr);
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usleep_range(1000, 1100);
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wilc_spi_reset(wl);
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usleep_range(1000, 1100);
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}
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static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
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{
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struct spi_device *spi = to_spi_device(wilc->dev);
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int result;
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u8 cmd = CMD_SINGLE_READ;
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u8 clockless = 0;
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u8 i;
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if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) {
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if (addr <= WILC_SPI_CLOCKLESS_ADDR_LIMIT) {
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/* Clockless register */
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cmd = CMD_INTERNAL_READ;
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clockless = 1;
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}
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result = wilc_spi_single_read(wilc, cmd, addr, data, clockless);
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if (result) {
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for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
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result = wilc_spi_single_read(wilc, cmd, addr, data, clockless);
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if (!result) {
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le32_to_cpus(data);
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return 0;
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}
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/* retry is not applicable for clockless registers */
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if (clockless)
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break;
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dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
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return result;
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wilc_spi_reset_cmd_sequence(wilc, i, addr);
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}
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le32_to_cpus(data);
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return 0;
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return result;
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}
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static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
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{
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struct spi_device *spi = to_spi_device(wilc->dev);
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int result;
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u8 i;
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if (size <= 4)
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return -EINVAL;
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result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr, buf, size);
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if (result) {
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for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
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result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr,
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buf, size);
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if (!result)
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return 0;
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dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
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return result;
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wilc_spi_reset_cmd_sequence(wilc, i, addr);
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}
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return 0;
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return result;
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}
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static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
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{
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struct spi_device *spi = to_spi_device(wilc->dev);
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int result;
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u8 i;
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result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr, dat, 0);
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if (result) {
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for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
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result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr,
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dat, 0);
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if (!result)
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return 0;
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dev_err(&spi->dev, "Failed internal write cmd...\n");
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return result;
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wilc_spi_reset_cmd_sequence(wilc, i, adr);
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}
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return 0;
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return result;
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}
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static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
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@ -890,17 +923,22 @@ static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
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struct spi_device *spi = to_spi_device(wilc->dev);
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struct wilc_spi *spi_priv = wilc->bus_data;
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int result;
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u8 i;
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result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr, data, 0);
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if (result) {
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for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
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result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr,
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data, 0);
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if (!result) {
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le32_to_cpus(data);
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return 0;
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}
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if (!spi_priv->probing_crc)
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dev_err(&spi->dev, "Failed internal read cmd...\n");
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return result;
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wilc_spi_reset_cmd_sequence(wilc, i, adr);
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}
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le32_to_cpus(data);
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return 0;
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return result;
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}
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/********************************************
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@ -915,20 +953,27 @@ static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
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int result;
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u8 cmd = CMD_SINGLE_WRITE;
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u8 clockless = 0;
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u8 i;
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if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) {
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if (addr <= WILC_SPI_CLOCKLESS_ADDR_LIMIT) {
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/* Clockless register */
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cmd = CMD_INTERNAL_WRITE;
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clockless = 1;
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}
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result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless);
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if (result) {
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dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
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return result;
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}
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for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
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result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless);
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if (!result)
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return 0;
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return 0;
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dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
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if (clockless)
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break;
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wilc_spi_reset_cmd_sequence(wilc, i, addr);
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}
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return result;
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}
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static int spi_data_rsp(struct wilc *wilc, u8 cmd)
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@ -981,6 +1026,7 @@ static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
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{
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struct spi_device *spi = to_spi_device(wilc->dev);
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int result;
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u8 i;
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/*
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* has to be greated than 4
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@ -988,26 +1034,38 @@ static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
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if (size <= 4)
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return -EINVAL;
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result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size);
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if (result) {
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dev_err(&spi->dev,
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"Failed cmd, write block (%08x)...\n", addr);
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return result;
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}
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for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
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result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr,
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NULL, size);
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if (result) {
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dev_err(&spi->dev,
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"Failed cmd, write block (%08x)...\n", addr);
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wilc_spi_reset_cmd_sequence(wilc, i, addr);
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continue;
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}
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/*
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* Data
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*/
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result = spi_data_write(wilc, buf, size);
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if (result) {
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dev_err(&spi->dev, "Failed block data write...\n");
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return result;
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}
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/*
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* Data
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*/
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result = spi_data_write(wilc, buf, size);
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if (result) {
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dev_err(&spi->dev, "Failed block data write...\n");
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wilc_spi_reset_cmd_sequence(wilc, i, addr);
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continue;
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}
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/*
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* Data response
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*/
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return spi_data_rsp(wilc, CMD_DMA_EXT_WRITE);
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/*
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* Data response
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*/
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result = spi_data_rsp(wilc, CMD_DMA_EXT_WRITE);
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if (result) {
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dev_err(&spi->dev, "Failed block data rsp...\n");
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wilc_spi_reset_cmd_sequence(wilc, i, addr);
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continue;
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}
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break;
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}
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return result;
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}
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/********************************************
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