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KVM: x86: use correct page table format to check nested page table reserved bits
Intel CPUID on AMD host or vice versa is a weird case, but it can happen. Handle it by checking the host CPU vendor instead of the guest's in reset_tdp_shadow_zero_bits_mask. For speed, the check uses the fact that Intel EPT has an X (executable) bit while AMD NPT has NX. Reported-by: Borislav Petkov <bp@alien8.de> Tested-by: Borislav Petkov <bp@alien8.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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1 changed files with 17 additions and 6 deletions
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@ -3614,7 +3614,7 @@ static void
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__reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
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struct rsvd_bits_validate *rsvd_check,
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int maxphyaddr, int level, bool nx, bool gbpages,
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bool pse)
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bool pse, bool amd)
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{
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u64 exb_bit_rsvd = 0;
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u64 gbpages_bit_rsvd = 0;
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@ -3631,7 +3631,7 @@ __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
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* Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
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* leaf entries) on AMD CPUs only.
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*/
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if (guest_cpuid_is_amd(vcpu))
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if (amd)
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nonleaf_bit8_rsvd = rsvd_bits(8, 8);
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switch (level) {
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@ -3699,7 +3699,7 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
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__reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
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cpuid_maxphyaddr(vcpu), context->root_level,
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context->nx, guest_cpuid_has_gbpages(vcpu),
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is_pse(vcpu));
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is_pse(vcpu), guest_cpuid_is_amd(vcpu));
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}
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static void
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@ -3749,13 +3749,24 @@ static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
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void
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reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
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{
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/*
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* Passing "true" to the last argument is okay; it adds a check
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* on bit 8 of the SPTEs which KVM doesn't use anyway.
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*/
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__reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
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boot_cpu_data.x86_phys_bits,
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context->shadow_root_level, context->nx,
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guest_cpuid_has_gbpages(vcpu), is_pse(vcpu));
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guest_cpuid_has_gbpages(vcpu), is_pse(vcpu),
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true);
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}
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EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
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static inline bool boot_cpu_is_amd(void)
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{
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WARN_ON_ONCE(!tdp_enabled);
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return shadow_x_mask == 0;
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}
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/*
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* the direct page table on host, use as much mmu features as
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* possible, however, kvm currently does not do execution-protection.
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@ -3764,11 +3775,11 @@ static void
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reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
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struct kvm_mmu *context)
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{
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if (guest_cpuid_is_amd(vcpu))
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if (boot_cpu_is_amd())
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__reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
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boot_cpu_data.x86_phys_bits,
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context->shadow_root_level, false,
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cpu_has_gbpages, true);
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cpu_has_gbpages, true, true);
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else
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__reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
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boot_cpu_data.x86_phys_bits,
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