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ASoC: amd: Enabling I2S instance in DMA and DAI
This patch adds I2S SP support in ACP PCM DMA and DAI. Added I2S support in DMA and DAI probe,its hw_params handling its open and close functionalities. This enables to open and close on the SP instance for playback and capture. Signed-off-by: Ravulapati Vishnu vardhan rao <Vishnuvardhanrao.Ravulapati@amd.com> Link: https://lore.kernel.org/r/1577540460-21438-3-git-send-email-Vishnuvardhanrao.Ravulapati@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
parent
c9fe7db6e8
commit
703a6e2288
3 changed files with 310 additions and 102 deletions
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@ -27,10 +27,10 @@ static int acp3x_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
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mode = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
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switch (mode) {
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case SND_SOC_DAIFMT_I2S:
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adata->tdm_mode = false;
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adata->tdm_mode = TDM_DISABLE;
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break;
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case SND_SOC_DAIFMT_DSP_A:
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adata->tdm_mode = true;
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adata->tdm_mode = TDM_ENABLE;
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break;
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default:
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return -EINVAL;
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@ -86,10 +86,22 @@ static int acp3x_i2s_hwparams(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
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{
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struct i2s_stream_instance *rtd;
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struct snd_soc_pcm_runtime *prtd;
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struct snd_soc_card *card;
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struct acp3x_platform_info *pinfo;
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u32 val;
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u32 reg_val;
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prtd = substream->private_data;
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rtd = substream->runtime->private_data;
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card = prtd->card;
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pinfo = snd_soc_card_get_drvdata(card);
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if (pinfo) {
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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rtd->i2s_instance = pinfo->play_i2s_instance;
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else
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rtd->i2s_instance = pinfo->cap_i2s_instance;
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}
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/* These values are as per Hardware Spec */
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switch (params_format(params)) {
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@ -109,11 +121,25 @@ static int acp3x_i2s_hwparams(struct snd_pcm_substream *substream,
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default:
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return -EINVAL;
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}
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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reg_val = mmACP_BTTDM_ITER;
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else
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reg_val = mmACP_BTTDM_IRER;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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switch (rtd->i2s_instance) {
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case I2S_BT_INSTANCE:
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reg_val = mmACP_BTTDM_ITER;
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break;
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case I2S_SP_INSTANCE:
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default:
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reg_val = mmACP_I2STDM_ITER;
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}
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} else {
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switch (rtd->i2s_instance) {
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case I2S_BT_INSTANCE:
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reg_val = mmACP_BTTDM_IRER;
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break;
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case I2S_SP_INSTANCE:
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default:
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reg_val = mmACP_I2STDM_IRER;
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}
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}
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val = rv_readl(rtd->acp3x_base + reg_val);
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val = val | (rtd->xfer_resolution << 3);
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rv_writel(val, rtd->acp3x_base + reg_val);
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@ -124,10 +150,21 @@ static int acp3x_i2s_trigger(struct snd_pcm_substream *substream,
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int cmd, struct snd_soc_dai *dai)
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{
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struct i2s_stream_instance *rtd;
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u32 val, period_bytes;
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int ret, reg_val;
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struct snd_soc_pcm_runtime *prtd;
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struct snd_soc_card *card;
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struct acp3x_platform_info *pinfo;
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u32 ret, val, period_bytes, reg_val, ier_val, water_val;
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prtd = substream->private_data;
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rtd = substream->runtime->private_data;
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card = prtd->card;
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pinfo = snd_soc_card_get_drvdata(card);
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if (pinfo) {
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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rtd->i2s_instance = pinfo->play_i2s_instance;
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else
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rtd->i2s_instance = pinfo->cap_i2s_instance;
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}
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period_bytes = frames_to_bytes(substream->runtime,
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substream->runtime->period_size);
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switch (cmd) {
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@ -137,31 +174,75 @@ static int acp3x_i2s_trigger(struct snd_pcm_substream *substream,
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rtd->bytescount = acp_get_byte_count(rtd,
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substream->stream);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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reg_val = mmACP_BTTDM_ITER;
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rv_writel(period_bytes, rtd->acp3x_base +
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mmACP_BT_TX_INTR_WATERMARK_SIZE);
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switch (rtd->i2s_instance) {
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case I2S_BT_INSTANCE:
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water_val =
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mmACP_BT_TX_INTR_WATERMARK_SIZE;
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reg_val = mmACP_BTTDM_ITER;
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ier_val = mmACP_BTTDM_IER;
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break;
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case I2S_SP_INSTANCE:
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default:
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water_val =
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mmACP_I2S_TX_INTR_WATERMARK_SIZE;
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reg_val = mmACP_I2STDM_ITER;
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ier_val = mmACP_I2STDM_IER;
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}
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} else {
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reg_val = mmACP_BTTDM_IRER;
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rv_writel(period_bytes, rtd->acp3x_base +
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mmACP_BT_RX_INTR_WATERMARK_SIZE);
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switch (rtd->i2s_instance) {
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case I2S_BT_INSTANCE:
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water_val =
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mmACP_BT_RX_INTR_WATERMARK_SIZE;
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reg_val = mmACP_BTTDM_IRER;
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ier_val = mmACP_BTTDM_IER;
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break;
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case I2S_SP_INSTANCE:
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default:
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water_val =
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mmACP_I2S_RX_INTR_WATERMARK_SIZE;
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reg_val = mmACP_I2STDM_IRER;
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ier_val = mmACP_I2STDM_IER;
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}
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}
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rv_writel(period_bytes, rtd->acp3x_base + water_val);
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val = rv_readl(rtd->acp3x_base + reg_val);
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val = val | BIT(0);
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rv_writel(val, rtd->acp3x_base + reg_val);
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rv_writel(1, rtd->acp3x_base + mmACP_BTTDM_IER);
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rv_writel(1, rtd->acp3x_base + ier_val);
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ret = 0;
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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reg_val = mmACP_BTTDM_ITER;
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else
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reg_val = mmACP_BTTDM_IRER;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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switch (rtd->i2s_instance) {
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case I2S_BT_INSTANCE:
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reg_val = mmACP_BTTDM_ITER;
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ier_val = mmACP_BTTDM_IER;
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break;
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case I2S_SP_INSTANCE:
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default:
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reg_val = mmACP_I2STDM_ITER;
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ier_val = mmACP_I2STDM_IER;
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}
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} else {
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switch (rtd->i2s_instance) {
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case I2S_BT_INSTANCE:
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reg_val = mmACP_BTTDM_IRER;
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ier_val = mmACP_BTTDM_IER;
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break;
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case I2S_SP_INSTANCE:
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default:
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reg_val = mmACP_I2STDM_IRER;
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ier_val = mmACP_I2STDM_IER;
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}
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}
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val = rv_readl(rtd->acp3x_base + reg_val);
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val = val & ~BIT(0);
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rv_writel(val, rtd->acp3x_base + reg_val);
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rv_writel(0, rtd->acp3x_base + mmACP_BTTDM_IER);
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rv_writel(0, rtd->acp3x_base + ier_val);
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ret = 0;
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break;
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default:
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ret = -EINVAL;
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@ -193,15 +193,31 @@ static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
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static void config_acp3x_dma(struct i2s_stream_instance *rtd, int direction)
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{
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u16 page_idx;
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u32 low, high, val, acp_fifo_addr;
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dma_addr_t addr = rtd->dma_addr;
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u32 low, high, val, acp_fifo_addr, reg_fifo_addr;
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u32 reg_ringbuf_size, reg_dma_size, reg_fifo_size;
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dma_addr_t addr;
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/* 8 scratch registers used to map one 64 bit address */
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if (direction == SNDRV_PCM_STREAM_PLAYBACK)
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val = 0;
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else
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val = rtd->num_pages * 8;
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addr = rtd->dma_addr;
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if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
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switch (rtd->i2s_instance) {
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case I2S_BT_INSTANCE:
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val = ACP_SRAM_BT_PB_PTE_OFFSET;
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break;
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case I2S_SP_INSTANCE:
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default:
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val = ACP_SRAM_SP_PB_PTE_OFFSET;
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}
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} else {
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switch (rtd->i2s_instance) {
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case I2S_BT_INSTANCE:
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val = ACP_SRAM_BT_CP_PTE_OFFSET;
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break;
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case I2S_SP_INSTANCE:
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default:
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val = ACP_SRAM_SP_CP_PTE_OFFSET;
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}
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}
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/* Group Enable */
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rv_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp3x_base +
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mmACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
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@ -223,38 +239,61 @@ static void config_acp3x_dma(struct i2s_stream_instance *rtd, int direction)
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}
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if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
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/* Config ringbuffer */
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rv_writel(MEM_WINDOW_START, rtd->acp3x_base +
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mmACP_BT_TX_RINGBUFADDR);
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rv_writel(MAX_BUFFER, rtd->acp3x_base +
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mmACP_BT_TX_RINGBUFSIZE);
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rv_writel(DMA_SIZE, rtd->acp3x_base + mmACP_BT_TX_DMA_SIZE);
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switch (rtd->i2s_instance) {
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case I2S_BT_INSTANCE:
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reg_ringbuf_size = mmACP_BT_TX_RINGBUFSIZE;
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reg_dma_size = mmACP_BT_TX_DMA_SIZE;
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acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
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BT_PB_FIFO_ADDR_OFFSET;
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reg_fifo_addr = mmACP_BT_TX_FIFOADDR;
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reg_fifo_size = mmACP_BT_TX_FIFOSIZE;
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rv_writel(I2S_BT_TX_MEM_WINDOW_START,
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rtd->acp3x_base + mmACP_BT_TX_RINGBUFADDR);
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break;
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/* Config audio fifo */
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acp_fifo_addr = ACP_SRAM_PTE_OFFSET + (rtd->num_pages * 8)
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+ PLAYBACK_FIFO_ADDR_OFFSET;
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rv_writel(acp_fifo_addr, rtd->acp3x_base +
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mmACP_BT_TX_FIFOADDR);
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rv_writel(FIFO_SIZE, rtd->acp3x_base + mmACP_BT_TX_FIFOSIZE);
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case I2S_SP_INSTANCE:
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default:
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reg_ringbuf_size = mmACP_I2S_TX_RINGBUFSIZE;
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reg_dma_size = mmACP_I2S_TX_DMA_SIZE;
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acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
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SP_PB_FIFO_ADDR_OFFSET;
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reg_fifo_addr = mmACP_I2S_TX_FIFOADDR;
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reg_fifo_size = mmACP_I2S_TX_FIFOSIZE;
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rv_writel(I2S_SP_TX_MEM_WINDOW_START,
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rtd->acp3x_base + mmACP_I2S_TX_RINGBUFADDR);
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}
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} else {
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/* Config ringbuffer */
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rv_writel(MEM_WINDOW_START + MAX_BUFFER, rtd->acp3x_base +
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mmACP_BT_RX_RINGBUFADDR);
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rv_writel(MAX_BUFFER, rtd->acp3x_base +
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mmACP_BT_RX_RINGBUFSIZE);
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rv_writel(DMA_SIZE, rtd->acp3x_base + mmACP_BT_RX_DMA_SIZE);
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switch (rtd->i2s_instance) {
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case I2S_BT_INSTANCE:
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reg_ringbuf_size = mmACP_BT_RX_RINGBUFSIZE;
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reg_dma_size = mmACP_BT_RX_DMA_SIZE;
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acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
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BT_CAPT_FIFO_ADDR_OFFSET;
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reg_fifo_addr = mmACP_BT_RX_FIFOADDR;
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reg_fifo_size = mmACP_BT_RX_FIFOSIZE;
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rv_writel(I2S_BT_RX_MEM_WINDOW_START,
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rtd->acp3x_base + mmACP_BT_RX_RINGBUFADDR);
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break;
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/* Config audio fifo */
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acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
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(rtd->num_pages * 8) + CAPTURE_FIFO_ADDR_OFFSET;
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rv_writel(acp_fifo_addr, rtd->acp3x_base +
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mmACP_BT_RX_FIFOADDR);
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rv_writel(FIFO_SIZE, rtd->acp3x_base + mmACP_BT_RX_FIFOSIZE);
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case I2S_SP_INSTANCE:
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default:
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reg_ringbuf_size = mmACP_I2S_RX_RINGBUFSIZE;
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reg_dma_size = mmACP_I2S_RX_DMA_SIZE;
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acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
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SP_CAPT_FIFO_ADDR_OFFSET;
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reg_fifo_addr = mmACP_I2S_RX_FIFOADDR;
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reg_fifo_size = mmACP_I2S_RX_FIFOSIZE;
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rv_writel(I2S_SP_RX_MEM_WINDOW_START,
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rtd->acp3x_base + mmACP_I2S_RX_RINGBUFADDR);
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}
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}
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/* Enable watermark/period interrupt to host */
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rv_writel(BIT(BT_TX_THRESHOLD) | BIT(BT_RX_THRESHOLD),
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rtd->acp3x_base + mmACP_EXTERNAL_INTR_CNTL);
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rv_writel(MAX_BUFFER, rtd->acp3x_base + reg_ringbuf_size);
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rv_writel(DMA_SIZE, rtd->acp3x_base + reg_dma_size);
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rv_writel(acp_fifo_addr, rtd->acp3x_base + reg_fifo_addr);
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rv_writel(FIFO_SIZE, rtd->acp3x_base + reg_fifo_size);
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rv_writel(BIT(I2S_RX_THRESHOLD) | BIT(BT_RX_THRESHOLD)
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| BIT(I2S_TX_THRESHOLD) | BIT(BT_TX_THRESHOLD),
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rtd->acp3x_base + mmACP_EXTERNAL_INTR_CNTL);
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}
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static int acp3x_dma_open(struct snd_soc_component *component,
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@ -287,17 +326,21 @@ static int acp3x_dma_open(struct snd_soc_component *component,
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return ret;
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}
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if (!adata->play_stream && !adata->capture_stream)
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if (!adata->play_stream && !adata->capture_stream &&
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adata->i2ssp_play_stream && !adata->i2ssp_capture_stream)
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rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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adata->play_stream = substream;
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else
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adata->i2ssp_play_stream = substream;
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} else {
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adata->capture_stream = substream;
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adata->i2ssp_capture_stream = substream;
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}
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i2s_data->acp3x_base = adata->acp3x_base;
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runtime->private_data = i2s_data;
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return 0;
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return ret;
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}
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@ -305,13 +348,27 @@ static int acp3x_dma_hw_params(struct snd_soc_component *component,
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struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct i2s_stream_instance *rtd;
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struct snd_soc_pcm_runtime *prtd;
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struct snd_soc_card *card;
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struct acp3x_platform_info *pinfo;
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u64 size;
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct i2s_stream_instance *rtd = runtime->private_data;
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prtd = substream->private_data;
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card = prtd->card;
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pinfo = snd_soc_card_get_drvdata(card);
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rtd = substream->runtime->private_data;
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if (!rtd)
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return -EINVAL;
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if (pinfo)
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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rtd->i2s_instance = pinfo->play_i2s_instance;
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else
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rtd->i2s_instance = pinfo->cap_i2s_instance;
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else
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pr_err("pinfo failed\n");
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size = params_buffer_bytes(params);
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rtd->dma_addr = substream->dma_buffer.addr;
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rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
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@ -322,12 +379,25 @@ static int acp3x_dma_hw_params(struct snd_soc_component *component,
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static snd_pcm_uframes_t acp3x_dma_pointer(struct snd_soc_component *component,
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struct snd_pcm_substream *substream)
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{
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struct snd_soc_pcm_runtime *prtd;
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struct snd_soc_card *card;
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struct acp3x_platform_info *pinfo;
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struct i2s_stream_instance *rtd;
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u32 pos;
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u32 buffersize;
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u64 bytescount;
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prtd = substream->private_data;
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card = prtd->card;
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rtd = substream->runtime->private_data;
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pinfo = snd_soc_card_get_drvdata(card);
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if (pinfo) {
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
||||
rtd->i2s_instance = pinfo->play_i2s_instance;
|
||||
else
|
||||
rtd->i2s_instance = pinfo->cap_i2s_instance;
|
||||
}
|
||||
|
||||
buffersize = frames_to_bytes(substream->runtime,
|
||||
substream->runtime->buffer_size);
|
||||
bytescount = acp_get_byte_count(rtd, substream->stream);
|
||||
|
@ -363,15 +433,19 @@ static int acp3x_dma_close(struct snd_soc_component *component,
|
|||
component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);
|
||||
adata = dev_get_drvdata(component->dev);
|
||||
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
||||
adata->play_stream = NULL;
|
||||
else
|
||||
adata->i2ssp_play_stream = NULL;
|
||||
} else {
|
||||
adata->capture_stream = NULL;
|
||||
adata->i2ssp_capture_stream = NULL;
|
||||
}
|
||||
|
||||
/* Disable ACP irq, when the current stream is being closed and
|
||||
* another stream is also not active.
|
||||
*/
|
||||
if (!adata->play_stream && !adata->capture_stream)
|
||||
if (!adata->play_stream && !adata->capture_stream &&
|
||||
!adata->i2ssp_play_stream && !adata->i2ssp_capture_stream)
|
||||
rv_writel(0, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
|
||||
return 0;
|
||||
}
|
||||
|
@ -478,8 +552,10 @@ static int acp3x_resume(struct device *dev)
|
|||
{
|
||||
struct i2s_dev_data *adata;
|
||||
int status;
|
||||
u32 val;
|
||||
u32 val, reg_val, frmt_val;
|
||||
|
||||
reg_val = 0;
|
||||
frmt_val = 0;
|
||||
adata = dev_get_drvdata(dev);
|
||||
status = acp3x_init(adata->acp3x_base);
|
||||
if (status)
|
||||
|
@ -489,32 +565,39 @@ static int acp3x_resume(struct device *dev)
|
|||
struct i2s_stream_instance *rtd =
|
||||
adata->play_stream->runtime->private_data;
|
||||
config_acp3x_dma(rtd, SNDRV_PCM_STREAM_PLAYBACK);
|
||||
rv_writel((rtd->xfer_resolution << 3),
|
||||
rtd->acp3x_base + mmACP_BTTDM_ITER);
|
||||
if (adata->tdm_mode == true) {
|
||||
rv_writel(adata->tdm_fmt, adata->acp3x_base +
|
||||
mmACP_BTTDM_TXFRMT);
|
||||
val = rv_readl(adata->acp3x_base + mmACP_BTTDM_ITER);
|
||||
rv_writel((val | 0x2), adata->acp3x_base +
|
||||
mmACP_BTTDM_ITER);
|
||||
switch (rtd->i2s_instance) {
|
||||
case I2S_BT_INSTANCE:
|
||||
reg_val = mmACP_BTTDM_ITER;
|
||||
frmt_val = mmACP_BTTDM_TXFRMT;
|
||||
break;
|
||||
case I2S_SP_INSTANCE:
|
||||
default:
|
||||
reg_val = mmACP_I2STDM_ITER;
|
||||
frmt_val = mmACP_I2STDM_TXFRMT;
|
||||
}
|
||||
rv_writel((rtd->xfer_resolution << 3), rtd->acp3x_base + reg_val);
|
||||
}
|
||||
|
||||
if (adata->capture_stream && adata->capture_stream->runtime) {
|
||||
struct i2s_stream_instance *rtd =
|
||||
adata->capture_stream->runtime->private_data;
|
||||
config_acp3x_dma(rtd, SNDRV_PCM_STREAM_CAPTURE);
|
||||
rv_writel((rtd->xfer_resolution << 3),
|
||||
rtd->acp3x_base + mmACP_BTTDM_IRER);
|
||||
if (adata->tdm_mode == true) {
|
||||
rv_writel(adata->tdm_fmt, adata->acp3x_base +
|
||||
mmACP_BTTDM_RXFRMT);
|
||||
val = rv_readl(adata->acp3x_base + mmACP_BTTDM_IRER);
|
||||
rv_writel((val | 0x2), adata->acp3x_base +
|
||||
mmACP_BTTDM_IRER);
|
||||
switch (rtd->i2s_instance) {
|
||||
case I2S_BT_INSTANCE:
|
||||
reg_val = mmACP_BTTDM_IRER;
|
||||
frmt_val = mmACP_BTTDM_RXFRMT;
|
||||
break;
|
||||
case I2S_SP_INSTANCE:
|
||||
default:
|
||||
reg_val = mmACP_I2STDM_IRER;
|
||||
frmt_val = mmACP_I2STDM_RXFRMT;
|
||||
}
|
||||
rv_writel((rtd->xfer_resolution << 3), rtd->acp3x_base + reg_val);
|
||||
}
|
||||
if (adata->tdm_mode == TDM_ENABLE) {
|
||||
rv_writel(adata->tdm_fmt, adata->acp3x_base + frmt_val);
|
||||
val = rv_readl(adata->acp3x_base + reg_val);
|
||||
rv_writel(val | 0x2, adata->acp3x_base + reg_val);
|
||||
}
|
||||
|
||||
rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
|
||||
return 0;
|
||||
}
|
||||
|
@ -524,8 +607,8 @@ static int acp3x_pcm_runtime_suspend(struct device *dev)
|
|||
{
|
||||
struct i2s_dev_data *adata;
|
||||
int status;
|
||||
adata = dev_get_drvdata(dev);
|
||||
|
||||
adata = dev_get_drvdata(dev);
|
||||
status = acp3x_deinit(adata->acp3x_base);
|
||||
if (status)
|
||||
dev_err(dev, "ACP de-init failed\n");
|
||||
|
@ -541,8 +624,8 @@ static int acp3x_pcm_runtime_resume(struct device *dev)
|
|||
{
|
||||
struct i2s_dev_data *adata;
|
||||
int status;
|
||||
adata = dev_get_drvdata(dev);
|
||||
|
||||
adata = dev_get_drvdata(dev);
|
||||
status = acp3x_init(adata->acp3x_base);
|
||||
if (status)
|
||||
return -ENODEV;
|
||||
|
|
|
@ -7,6 +7,11 @@
|
|||
|
||||
#include "chip_offset_byte.h"
|
||||
#include <sound/pcm.h>
|
||||
#define I2S_SP_INSTANCE 0x01
|
||||
#define I2S_BT_INSTANCE 0x02
|
||||
|
||||
#define TDM_ENABLE 1
|
||||
#define TDM_DISABLE 0
|
||||
|
||||
#define ACP3x_DEVS 3
|
||||
#define ACP3x_PHY_BASE_ADDRESS 0x1240000
|
||||
|
@ -18,8 +23,11 @@
|
|||
#define ACP3x_BT_TDM_REG_START 0x1242800
|
||||
#define ACP3x_BT_TDM_REG_END 0x1242810
|
||||
#define I2S_MODE 0x04
|
||||
#define I2S_RX_THRESHOLD 27
|
||||
#define I2S_TX_THRESHOLD 28
|
||||
#define BT_TX_THRESHOLD 26
|
||||
#define BT_RX_THRESHOLD 25
|
||||
#define ACP_ERR_INTR_MASK 29
|
||||
#define ACP3x_POWER_ON 0x00
|
||||
#define ACP3x_POWER_ON_IN_PROGRESS 0x01
|
||||
#define ACP3x_POWER_OFF 0x02
|
||||
|
@ -27,19 +35,28 @@
|
|||
#define ACP3x_SOFT_RESET__SoftResetAudDone_MASK 0x00010001
|
||||
|
||||
#define ACP_SRAM_PTE_OFFSET 0x02050000
|
||||
#define ACP_SRAM_SP_PB_PTE_OFFSET 0x0
|
||||
#define ACP_SRAM_SP_CP_PTE_OFFSET 0x100
|
||||
#define ACP_SRAM_BT_PB_PTE_OFFSET 0x200
|
||||
#define ACP_SRAM_BT_CP_PTE_OFFSET 0x300
|
||||
#define PAGE_SIZE_4K_ENABLE 0x2
|
||||
#define MEM_WINDOW_START 0x4000000
|
||||
#define PLAYBACK_FIFO_ADDR_OFFSET 0x400
|
||||
#define CAPTURE_FIFO_ADDR_OFFSET 0x500
|
||||
#define I2S_SP_TX_MEM_WINDOW_START 0x4000000
|
||||
#define I2S_SP_RX_MEM_WINDOW_START 0x4020000
|
||||
#define I2S_BT_TX_MEM_WINDOW_START 0x4040000
|
||||
#define I2S_BT_RX_MEM_WINDOW_START 0x4060000
|
||||
|
||||
#define SP_PB_FIFO_ADDR_OFFSET 0x500
|
||||
#define SP_CAPT_FIFO_ADDR_OFFSET 0x700
|
||||
#define BT_PB_FIFO_ADDR_OFFSET 0x900
|
||||
#define BT_CAPT_FIFO_ADDR_OFFSET 0xB00
|
||||
#define PLAYBACK_MIN_NUM_PERIODS 2
|
||||
#define PLAYBACK_MAX_NUM_PERIODS 8
|
||||
#define PLAYBACK_MAX_PERIOD_SIZE 16384
|
||||
#define PLAYBACK_MIN_PERIOD_SIZE 4096
|
||||
#define PLAYBACK_MAX_PERIOD_SIZE 8192
|
||||
#define PLAYBACK_MIN_PERIOD_SIZE 1024
|
||||
#define CAPTURE_MIN_NUM_PERIODS 2
|
||||
#define CAPTURE_MAX_NUM_PERIODS 8
|
||||
#define CAPTURE_MAX_PERIOD_SIZE 16384
|
||||
#define CAPTURE_MIN_PERIOD_SIZE 4096
|
||||
#define CAPTURE_MAX_PERIOD_SIZE 8192
|
||||
#define CAPTURE_MIN_PERIOD_SIZE 1024
|
||||
|
||||
#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
|
||||
#define MIN_BUFFER MAX_BUFFER
|
||||
|
@ -66,14 +83,20 @@ struct i2s_dev_data {
|
|||
void __iomem *acp3x_base;
|
||||
struct snd_pcm_substream *play_stream;
|
||||
struct snd_pcm_substream *capture_stream;
|
||||
struct snd_pcm_substream *i2ssp_play_stream;
|
||||
struct snd_pcm_substream *i2ssp_capture_stream;
|
||||
};
|
||||
|
||||
struct i2s_stream_instance {
|
||||
u16 num_pages;
|
||||
u16 i2s_instance;
|
||||
u16 capture_channel;
|
||||
u16 direction;
|
||||
u16 channels;
|
||||
u32 xfer_resolution;
|
||||
u64 bytescount;
|
||||
u32 val;
|
||||
dma_addr_t dma_addr;
|
||||
u64 bytescount;
|
||||
void __iomem *acp3x_base;
|
||||
};
|
||||
|
||||
|
@ -93,15 +116,36 @@ static inline u64 acp_get_byte_count(struct i2s_stream_instance *rtd,
|
|||
u64 byte_count;
|
||||
|
||||
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
|
||||
byte_count = rv_readl(rtd->acp3x_base +
|
||||
mmACP_BT_TX_LINEARPOSITIONCNTR_HIGH);
|
||||
byte_count |= rv_readl(rtd->acp3x_base +
|
||||
mmACP_BT_TX_LINEARPOSITIONCNTR_LOW);
|
||||
switch (rtd->i2s_instance) {
|
||||
case I2S_BT_INSTANCE:
|
||||
byte_count = rv_readl(rtd->acp3x_base +
|
||||
mmACP_BT_TX_LINEARPOSITIONCNTR_HIGH);
|
||||
byte_count |= rv_readl(rtd->acp3x_base +
|
||||
mmACP_BT_TX_LINEARPOSITIONCNTR_LOW);
|
||||
break;
|
||||
case I2S_SP_INSTANCE:
|
||||
default:
|
||||
byte_count = rv_readl(rtd->acp3x_base +
|
||||
mmACP_I2S_TX_LINEARPOSITIONCNTR_HIGH);
|
||||
byte_count |= rv_readl(rtd->acp3x_base +
|
||||
mmACP_I2S_TX_LINEARPOSITIONCNTR_LOW);
|
||||
}
|
||||
|
||||
} else {
|
||||
byte_count = rv_readl(rtd->acp3x_base +
|
||||
mmACP_BT_RX_LINEARPOSITIONCNTR_HIGH);
|
||||
byte_count |= rv_readl(rtd->acp3x_base +
|
||||
mmACP_BT_RX_LINEARPOSITIONCNTR_LOW);
|
||||
switch (rtd->i2s_instance) {
|
||||
case I2S_BT_INSTANCE:
|
||||
byte_count = rv_readl(rtd->acp3x_base +
|
||||
mmACP_BT_RX_LINEARPOSITIONCNTR_HIGH);
|
||||
byte_count |= rv_readl(rtd->acp3x_base +
|
||||
mmACP_BT_RX_LINEARPOSITIONCNTR_LOW);
|
||||
break;
|
||||
case I2S_SP_INSTANCE:
|
||||
default:
|
||||
byte_count = rv_readl(rtd->acp3x_base +
|
||||
mmACP_I2S_RX_LINEARPOSITIONCNTR_HIGH);
|
||||
byte_count |= rv_readl(rtd->acp3x_base +
|
||||
mmACP_I2S_RX_LINEARPOSITIONCNTR_LOW);
|
||||
}
|
||||
}
|
||||
return byte_count;
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue