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clk: sunxi-ng: A31: Fix spdif clock register
As the SPDIF was rarely documented on the earlier Allwinner SoCs it was assumed that it had a similar clock register to the one described in the H3 User Manual. However this is not the case and it looks to shares the same setup as the I2S clock registers. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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1 changed files with 2 additions and 2 deletions
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@ -468,8 +468,8 @@ static SUNXI_CCU_MUX_WITH_GATE(daudio0_clk, "daudio0", daudio_parents,
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static SUNXI_CCU_MUX_WITH_GATE(daudio1_clk, "daudio1", daudio_parents,
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0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
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0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
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static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", daudio_parents,
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0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
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static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
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0x0cc, BIT(8), 0);
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