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iommu/exynos: Gating clocks of master H/W
This patch gates clocks of master H/W as well as clocks of System MMU if master clocks are specified. Some Exynos SoCs (i.e. GScalers in Exynos5250) have dependencies in the gating clocks of master H/W and its System MMU. If a H/W is the case, accessing control registers of System MMU is prohibited unless both of the gating clocks of System MMU and its master H/W. CC: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Cho KyongHo <pullip.cho@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
parent
46c16d1e4c
commit
7060587052
1 changed files with 38 additions and 2 deletions
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@ -172,6 +172,7 @@ struct sysmmu_drvdata {
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struct device *dev; /* Owner of system MMU */
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void __iomem *sfrbase;
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struct clk *clk;
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struct clk *clk_master;
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int activations;
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rwlock_t lock;
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struct iommu_domain *domain;
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@ -300,6 +301,8 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
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WARN_ON(!is_sysmmu_active(data));
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if (!IS_ERR(data->clk_master))
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clk_enable(data->clk_master);
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itype = (enum exynos_sysmmu_inttype)
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__ffs(__raw_readl(data->sfrbase + REG_INT_STATUS));
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if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN))))
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@ -326,6 +329,9 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
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if (itype != SYSMMU_FAULT_UNKNOWN)
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sysmmu_unblock(data->sfrbase);
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if (!IS_ERR(data->clk_master))
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clk_disable(data->clk_master);
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read_unlock(&data->lock);
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return IRQ_HANDLED;
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@ -341,9 +347,14 @@ static bool __exynos_sysmmu_disable(struct sysmmu_drvdata *data)
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if (!set_sysmmu_inactive(data))
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goto finish;
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if (!IS_ERR(data->clk_master))
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clk_enable(data->clk_master);
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__raw_writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
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clk_disable(data->clk);
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if (!IS_ERR(data->clk_master))
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clk_disable(data->clk_master);
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disabled = true;
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data->pgtable = 0;
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@ -386,14 +397,19 @@ static int __exynos_sysmmu_enable(struct sysmmu_drvdata *data,
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goto finish;
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}
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clk_enable(data->clk);
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data->pgtable = pgtable;
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if (!IS_ERR(data->clk_master))
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clk_enable(data->clk_master);
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clk_enable(data->clk);
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__sysmmu_set_ptbase(data->sfrbase, pgtable);
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__raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
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if (!IS_ERR(data->clk_master))
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clk_disable(data->clk_master);
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data->domain = domain;
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dev_dbg(data->sysmmu, "Enabled\n");
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@ -450,6 +466,10 @@ static void sysmmu_tlb_invalidate_entry(struct device *dev, unsigned long iova,
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if (is_sysmmu_active(data)) {
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unsigned int maj;
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unsigned int num_inv = 1;
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if (!IS_ERR(data->clk_master))
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clk_enable(data->clk_master);
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maj = __raw_readl(data->sfrbase + REG_MMU_VERSION);
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/*
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* L2TLB invalidation required
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@ -469,6 +489,8 @@ static void sysmmu_tlb_invalidate_entry(struct device *dev, unsigned long iova,
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data->sfrbase, iova, num_inv);
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sysmmu_unblock(data->sfrbase);
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}
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if (!IS_ERR(data->clk_master))
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clk_disable(data->clk_master);
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} else {
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dev_dbg(data->sysmmu, "Disabled. Skipping invalidating TLB.\n");
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}
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@ -484,10 +506,14 @@ void exynos_sysmmu_tlb_invalidate(struct device *dev)
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read_lock_irqsave(&data->lock, flags);
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if (is_sysmmu_active(data)) {
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if (!IS_ERR(data->clk_master))
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clk_enable(data->clk_master);
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if (sysmmu_block(data->sfrbase)) {
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__sysmmu_tlb_invalidate(data->sfrbase);
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sysmmu_unblock(data->sfrbase);
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}
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if (!IS_ERR(data->clk_master))
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clk_disable(data->clk_master);
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} else {
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dev_dbg(data->sysmmu, "Disabled. Skipping invalidating TLB.\n");
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}
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@ -536,6 +562,16 @@ static int exynos_sysmmu_probe(struct platform_device *pdev)
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}
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}
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data->clk_master = devm_clk_get(dev, "master");
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if (!IS_ERR(data->clk_master)) {
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ret = clk_prepare(data->clk_master);
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if (ret) {
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clk_unprepare(data->clk);
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dev_err(dev, "Failed to prepare master's clk\n");
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return ret;
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}
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}
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data->sysmmu = dev;
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rwlock_init(&data->lock);
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INIT_LIST_HEAD(&data->node);
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