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intel-pinctrl for v6.8-1 

* New agnostic driver to support Lunar Lake and newer platforms
 * New driver for Intel Meteor Point-S (PCH for Meteor Lake-S)
 * Update drivers to use new PM helpers
 * Use RAII for locking in a few drivers (Raag, Andy)
 * Reduce locking scope in some functions (Raag)
 * Miscellaneous cleanups (Raag)
 
 The following is an automated git shortlog grouped by driver:
 
 alderlake:
  -  Switch to use Intel pin control PM ops
 
 baytrail:
  -  Simplify code with cleanup helpers
  -  Move default strength assignment to a switch-case
  -  Factor out byt_gpio_force_input_mode()
  -  Fix types of config value in byt_pin_config_set()
 
 broxton:
  -  Switch to use Intel pin control PM ops
 
 cannonlake:
  -  Switch to use Intel pin control PM ops
 
 cedarfork:
  -  Switch to use Intel pin control PM ops
 
 denverton:
  -  Switch to use Intel pin control PM ops
 
 elkhartlake:
  -  Switch to use Intel pin control PM ops
 
 emmitsburg:
  -  Switch to use Intel pin control PM ops
 
 geminilake:
  -  Switch to use Intel pin control PM ops
 
 icelake:
  -  Switch to use Intel pin control PM ops
 
 intel:
  -  Add Intel Meteor Point pin controller and GPIO support
  -  use the correct _PM_OPS() export macro
  -  Add a generic Intel pin control platform driver
  -  Revert "Unexport intel_pinctrl_probe()"
  -  allow independent COMPILE_TEST
  -  Refactor intel_pinctrl_get_soc_data()
  -  Move default strength assignment to a switch-case
  -  Make PM ops functions static
  -  Provide Intel pin control wide PM ops structure
 
 jasperlake:
  -  Switch to use Intel pin control PM ops
 
 lakefield:
  -  Switch to use Intel pin control PM ops
 
 lewisburg:
  -  Switch to use Intel pin control PM ops
 
 lynxpoint:
  -  Simplify code with cleanup helpers
 
 meteorlake:
  -  Switch to use Intel pin control PM ops
 
 sunrisepoint:
  -  Switch to use Intel pin control PM ops
 
 tangier:
  -  simplify locking using cleanup helpers
  -  Move default strength assignment to a switch-case
  -  Enable 910 Ohm bias
 
 tigerlake:
  -  Switch to use Intel pin control PM ops
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Merge tag 'intel-pinctrl-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel

intel-pinctrl for v6.8-1

* New agnostic driver to support Lunar Lake and newer platforms
* New driver for Intel Meteor Point-S (PCH for Meteor Lake-S)
* Update drivers to use new PM helpers
* Use RAII for locking in a few drivers (Raag, Andy)
* Reduce locking scope in some functions (Raag)
* Miscellaneous cleanups (Raag)

The following is an automated git shortlog grouped by driver:

alderlake:
 -  Switch to use Intel pin control PM ops

baytrail:
 -  Simplify code with cleanup helpers
 -  Move default strength assignment to a switch-case
 -  Factor out byt_gpio_force_input_mode()
 -  Fix types of config value in byt_pin_config_set()

broxton:
 -  Switch to use Intel pin control PM ops

cannonlake:
 -  Switch to use Intel pin control PM ops

cedarfork:
 -  Switch to use Intel pin control PM ops

denverton:
 -  Switch to use Intel pin control PM ops

elkhartlake:
 -  Switch to use Intel pin control PM ops

emmitsburg:
 -  Switch to use Intel pin control PM ops

geminilake:
 -  Switch to use Intel pin control PM ops

icelake:
 -  Switch to use Intel pin control PM ops

intel:
 -  Add Intel Meteor Point pin controller and GPIO support
 -  use the correct _PM_OPS() export macro
 -  Add a generic Intel pin control platform driver
 -  Revert "Unexport intel_pinctrl_probe()"
 -  allow independent COMPILE_TEST
 -  Refactor intel_pinctrl_get_soc_data()
 -  Move default strength assignment to a switch-case
 -  Make PM ops functions static
 -  Provide Intel pin control wide PM ops structure

jasperlake:
 -  Switch to use Intel pin control PM ops

lakefield:
 -  Switch to use Intel pin control PM ops

lewisburg:
 -  Switch to use Intel pin control PM ops

lynxpoint:
 -  Simplify code with cleanup helpers

meteorlake:
 -  Switch to use Intel pin control PM ops

sunrisepoint:
 -  Switch to use Intel pin control PM ops

tangier:
 -  simplify locking using cleanup helpers
 -  Move default strength assignment to a switch-case
 -  Enable 910 Ohm bias

tigerlake:
 -  Switch to use Intel pin control PM ops

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij 2023-12-18 23:42:42 +01:00
parent 915fdc94f1 ebe7f33937
commit 7085e4e2ff
24 changed files with 888 additions and 279 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
drivers/pinctrl/intel/Kconfig
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
# Intel pin control drivers
menu "Intel pinctrl drivers"
depends on ACPI && (X86 || COMPILE_TEST)
depends on (ACPI && X86) || COMPILE_TEST
config PINCTRL_BAYTRAIL
bool "Intel Baytrail GPIO pin control"
@ -37,6 +37,16 @@ config PINCTRL_INTEL
select GPIOLIB
select GPIOLIB_IRQCHIP
config PINCTRL_INTEL_PLATFORM
tristate "Intel pinctrl and GPIO platform driver"
depends on ACPI
select PINCTRL_INTEL
help
This pinctrl driver provides an interface that allows configuring
of Intel PCH pins and using them as GPIOs. Currently the following
Intel SoCs / platforms require this to be functional:
- Lunar Lake
config PINCTRL_ALDERLAKE
tristate "Intel Alder Lake pinctrl and GPIO driver"
select PINCTRL_INTEL
@ -128,6 +138,15 @@ config PINCTRL_METEORLAKE
This pinctrl driver provides an interface that allows configuring
of Intel Meteor Lake pins and using them as GPIOs.
config PINCTRL_METEORPOINT
tristate "Intel Meteor Point pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL
help
Meteor Point is the PCH of Intel Meteor Lake. This pinctrl driver
provides an interface that allows configuring of PCH pins and
using them as GPIOs.
config PINCTRL_SUNRISEPOINT
tristate "Intel Sunrisepoint pinctrl and GPIO driver"
select PINCTRL_INTEL

2
drivers/pinctrl/intel/Makefile
View File

@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_TANGIER) += pinctrl-tangier.o
obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o
obj-$(CONFIG_PINCTRL_MOOREFIELD) += pinctrl-moorefield.o
obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o
obj-$(CONFIG_PINCTRL_INTEL_PLATFORM) += pinctrl-intel-platform.o
obj-$(CONFIG_PINCTRL_ALDERLAKE) += pinctrl-alderlake.o
obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o
obj-$(CONFIG_PINCTRL_CANNONLAKE) += pinctrl-cannonlake.o
@ -21,5 +22,6 @@ obj-$(CONFIG_PINCTRL_JASPERLAKE) += pinctrl-jasperlake.o
obj-$(CONFIG_PINCTRL_LAKEFIELD) += pinctrl-lakefield.o
obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o
obj-$(CONFIG_PINCTRL_METEORLAKE) += pinctrl-meteorlake.o
obj-$(CONFIG_PINCTRL_METEORPOINT) += pinctrl-meteorpoint.o
obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o
obj-$(CONFIG_PINCTRL_TIGERLAKE) += pinctrl-tigerlake.o

5
drivers/pinctrl/intel/pinctrl-alderlake.c
View File

@ -9,6 +9,7 @@
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
@ -733,14 +734,12 @@ static const struct acpi_device_id adl_pinctrl_acpi_match[] = {
};
MODULE_DEVICE_TABLE(acpi, adl_pinctrl_acpi_match);
static INTEL_PINCTRL_PM_OPS(adl_pinctrl_pm_ops);
static struct platform_driver adl_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "alderlake-pinctrl",
.acpi_match_table = adl_pinctrl_acpi_match,
.pm = &adl_pinctrl_pm_ops,
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
},
};
module_platform_driver(adl_pinctrl_driver);

229
drivers/pinctrl/intel/pinctrl-baytrail.c
View File

@ -588,10 +588,9 @@ static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
const struct intel_pingroup group,
unsigned int func)
{
unsigned long flags;
int i;
raw_spin_lock_irqsave(&byt_lock, flags);
guard(raw_spinlock_irqsave)(&byt_lock);
for (i = 0; i < group.grp.npins; i++) {
void __iomem *padcfg0;
@ -609,18 +608,15 @@ static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
value |= func;
writel(value, padcfg0);
}
raw_spin_unlock_irqrestore(&byt_lock, flags);
}
static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
const struct intel_pingroup group,
const unsigned int *func)
{
unsigned long flags;
int i;
raw_spin_lock_irqsave(&byt_lock, flags);
guard(raw_spinlock_irqsave)(&byt_lock);
for (i = 0; i < group.grp.npins; i++) {
void __iomem *padcfg0;
@ -638,8 +634,6 @@ static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
value |= func[i];
writel(value, padcfg0);
}
raw_spin_unlock_irqrestore(&byt_lock, flags);
}
static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
@ -677,10 +671,10 @@ static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset)
static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset)
{
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
unsigned long flags;
u32 value;
raw_spin_lock_irqsave(&byt_lock, flags);
guard(raw_spinlock_irqsave)(&byt_lock);
value = readl(reg);
/* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
@ -688,7 +682,6 @@ static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int off
value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
writel(value, reg);
raw_spin_unlock_irqrestore(&byt_lock, flags);
}
static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
@ -698,9 +691,8 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
u32 value, gpio_mux;
unsigned long flags;
raw_spin_lock_irqsave(&byt_lock, flags);
guard(raw_spinlock_irqsave)(&byt_lock);
/*
* In most cases, func pin mux 000 means GPIO function.
@ -713,15 +705,14 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
*/
value = readl(reg) & BYT_PIN_MUX;
gpio_mux = byt_get_gpio_mux(vg, offset);
if (gpio_mux != value) {
value = readl(reg) & ~BYT_PIN_MUX;
value |= gpio_mux;
writel(value, reg);
if (gpio_mux == value)
return 0;
dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset);
}
value = readl(reg) & ~BYT_PIN_MUX;
value |= gpio_mux;
writel(value, reg);
raw_spin_unlock_irqrestore(&byt_lock, flags);
dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset);
return 0;
}
@ -759,10 +750,9 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
{
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
unsigned long flags;
u32 value;
raw_spin_lock_irqsave(&byt_lock, flags);
guard(raw_spinlock_irqsave)(&byt_lock);
value = readl(val_reg);
value &= ~BYT_DIR_MASK;
@ -773,8 +763,6 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
writel(value, val_reg);
raw_spin_unlock_irqrestore(&byt_lock, flags);
return 0;
}
@ -811,6 +799,7 @@ static int byt_set_pull_strength(u32 *reg, u16 strength)
*reg &= ~BYT_PULL_STR_MASK;
switch (strength) {
case 1: /* Set default strength value in case none is given */
case 2000:
*reg |= BYT_PULL_STR_2K;
break;
@ -830,6 +819,24 @@ static int byt_set_pull_strength(u32 *reg, u16 strength)
return 0;
}
static void byt_gpio_force_input_mode(struct intel_pinctrl *vg, unsigned int offset)
{
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
u32 value;
value = readl(reg);
if (!(value & BYT_INPUT_EN))
return;
/*
* Pull assignment is only applicable in input mode. If
* chip is not in input mode, set it and warn about it.
*/
value &= ~BYT_INPUT_EN;
writel(value, reg);
dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
}
static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
unsigned long *config)
{
@ -838,15 +845,15 @@ static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
unsigned long flags;
u32 conf, pull, val, debounce;
u16 arg = 0;
raw_spin_lock_irqsave(&byt_lock, flags);
conf = readl(conf_reg);
scoped_guard(raw_spinlock_irqsave, &byt_lock) {
conf = readl(conf_reg);
val = readl(val_reg);
}
pull = conf & BYT_PULL_ASSIGN_MASK;
val = readl(val_reg);
raw_spin_unlock_irqrestore(&byt_lock, flags);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
@ -873,9 +880,8 @@ static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
if (!(conf & BYT_DEBOUNCE_EN))
return -EINVAL;
raw_spin_lock_irqsave(&byt_lock, flags);
debounce = readl(db_reg);
raw_spin_unlock_irqrestore(&byt_lock, flags);
scoped_guard(raw_spinlock_irqsave, &byt_lock)
debounce = readl(db_reg);
switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
case BYT_DEBOUNCE_PULSE_375US:
@ -919,18 +925,16 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
unsigned int num_configs)
{
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
unsigned int param, arg;
void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
u32 conf, val, db_pulse, debounce;
unsigned long flags;
int i, ret = 0;
u32 conf, db_pulse, debounce;
enum pin_config_param param;
int i, ret;
u32 arg;
raw_spin_lock_irqsave(&byt_lock, flags);
guard(raw_spinlock_irqsave)(&byt_lock);
conf = readl(conf_reg);
val = readl(val_reg);
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
@ -941,59 +945,30 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
conf &= ~BYT_PULL_ASSIGN_MASK;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
/* Set default strength value in case none is given */
if (arg == 1)
arg = 2000;
/*
* Pull assignment is only applicable in input mode. If
* chip is not in input mode, set it and warn about it.
*/
if (val & BYT_INPUT_EN) {
val &= ~BYT_INPUT_EN;
writel(val, val_reg);
dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
}
byt_gpio_force_input_mode(vg, offset);
conf &= ~BYT_PULL_ASSIGN_MASK;
conf |= BYT_PULL_ASSIGN_DOWN;
ret = byt_set_pull_strength(&conf, arg);
if (ret)
return ret;
break;
case PIN_CONFIG_BIAS_PULL_UP:
/* Set default strength value in case none is given */
if (arg == 1)
arg = 2000;
/*
* Pull assignment is only applicable in input mode. If
* chip is not in input mode, set it and warn about it.
*/
if (val & BYT_INPUT_EN) {
val &= ~BYT_INPUT_EN;
writel(val, val_reg);
dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
}
byt_gpio_force_input_mode(vg, offset);
conf &= ~BYT_PULL_ASSIGN_MASK;
conf |= BYT_PULL_ASSIGN_UP;
ret = byt_set_pull_strength(&conf, arg);
if (ret)
return ret;
break;
case PIN_CONFIG_INPUT_DEBOUNCE:
if (arg) {
conf |= BYT_DEBOUNCE_EN;
} else {
conf &= ~BYT_DEBOUNCE_EN;
/*
* No need to update the pulse value.
* Debounce is going to be disabled.
*/
break;
}
switch (arg) {
case 0:
db_pulse = 0;
break;
case 375:
db_pulse = BYT_DEBOUNCE_PULSE_375US;
break;
@ -1016,33 +991,28 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
db_pulse = BYT_DEBOUNCE_PULSE_24MS;
break;
default:
if (arg)
ret = -EINVAL;
break;
return -EINVAL;
}
if (ret)
break;
if (db_pulse) {
debounce = readl(db_reg);
debounce = (debounce & ~BYT_DEBOUNCE_PULSE_MASK) | db_pulse;
writel(debounce, db_reg);
debounce = readl(db_reg);
debounce = (debounce & ~BYT_DEBOUNCE_PULSE_MASK) | db_pulse;
writel(debounce, db_reg);
conf |= BYT_DEBOUNCE_EN;
} else {
conf &= ~BYT_DEBOUNCE_EN;
}
break;
default:
ret = -ENOTSUPP;
return -ENOTSUPP;
}
if (ret)
break;
}
if (!ret)
writel(conf, conf_reg);
writel(conf, conf_reg);
raw_spin_unlock_irqrestore(&byt_lock, flags);
return ret;
return 0;
}
static const struct pinconf_ops byt_pinconf_ops = {
@ -1062,12 +1032,10 @@ static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct intel_pinctrl *vg = gpiochip_get_data(chip);
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
unsigned long flags;
u32 val;
raw_spin_lock_irqsave(&byt_lock, flags);
val = readl(reg);
raw_spin_unlock_irqrestore(&byt_lock, flags);
scoped_guard(raw_spinlock_irqsave, &byt_lock)
val = readl(reg);
return !!(val & BYT_LEVEL);
}
@ -1075,35 +1043,34 @@ static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
{
struct intel_pinctrl *vg = gpiochip_get_data(chip);
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
unsigned long flags;
void __iomem *reg;
u32 old_val;
reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
if (!reg)
return;
raw_spin_lock_irqsave(&byt_lock, flags);
guard(raw_spinlock_irqsave)(&byt_lock);
old_val = readl(reg);
if (value)
writel(old_val | BYT_LEVEL, reg);
else
writel(old_val & ~BYT_LEVEL, reg);
raw_spin_unlock_irqrestore(&byt_lock, flags);
}
static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct intel_pinctrl *vg = gpiochip_get_data(chip);
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
unsigned long flags;
void __iomem *reg;
u32 value;
reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
if (!reg)
return -EINVAL;
raw_spin_lock_irqsave(&byt_lock, flags);
value = readl(reg);
raw_spin_unlock_irqrestore(&byt_lock, flags);
scoped_guard(raw_spinlock_irqsave, &byt_lock)
value = readl(reg);
if (!(value & BYT_OUTPUT_EN))
return GPIO_LINE_DIRECTION_OUT;
@ -1117,17 +1084,15 @@ static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
struct intel_pinctrl *vg = gpiochip_get_data(chip);
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
unsigned long flags;
u32 reg;
raw_spin_lock_irqsave(&byt_lock, flags);
guard(raw_spinlock_irqsave)(&byt_lock);
reg = readl(val_reg);
reg &= ~BYT_DIR_MASK;
reg |= BYT_OUTPUT_EN;
writel(reg, val_reg);
raw_spin_unlock_irqrestore(&byt_lock, flags);
return 0;
}
@ -1142,10 +1107,9 @@ static int byt_gpio_direction_output(struct gpio_chip *chip,
{
struct intel_pinctrl *vg = gpiochip_get_data(chip);
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
unsigned long flags;
u32 reg;
raw_spin_lock_irqsave(&byt_lock, flags);
guard(raw_spinlock_irqsave)(&byt_lock);
byt_gpio_direct_irq_check(vg, offset);
@ -1158,7 +1122,6 @@ static int byt_gpio_direction_output(struct gpio_chip *chip,
writel(reg, val_reg);
raw_spin_unlock_irqrestore(&byt_lock, flags);
return 0;
}
@ -1173,7 +1136,6 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
void __iomem *conf_reg, *val_reg;
const char *pull_str = NULL;
const char *pull = NULL;
unsigned long flags;
unsigned int pin;
pin = vg->soc->pins[i].number;
@ -1190,10 +1152,10 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
continue;
}
raw_spin_lock_irqsave(&byt_lock, flags);
conf0 = readl(conf_reg);
val = readl(val_reg);
raw_spin_unlock_irqrestore(&byt_lock, flags);
scoped_guard(raw_spinlock_irqsave, &byt_lock) {
conf0 = readl(conf_reg);
val = readl(val_reg);
}
comm = intel_get_community(vg, pin);
if (!comm) {
@ -1278,9 +1240,9 @@ static void byt_irq_ack(struct irq_data *d)
if (!reg)
return;
raw_spin_lock(&byt_lock);
guard(raw_spinlock)(&byt_lock);
writel(BIT(hwirq % 32), reg);
raw_spin_unlock(&byt_lock);
}
static void byt_irq_mask(struct irq_data *d)
@ -1298,7 +1260,6 @@ static void byt_irq_unmask(struct irq_data *d)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *vg = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
unsigned long flags;
void __iomem *reg;
u32 value;
@ -1308,7 +1269,8 @@ static void byt_irq_unmask(struct irq_data *d)
if (!reg)
return;
raw_spin_lock_irqsave(&byt_lock, flags);
guard(raw_spinlock_irqsave)(&byt_lock);
value = readl(reg);
switch (irqd_get_trigger_type(d)) {
@ -1330,23 +1292,21 @@ static void byt_irq_unmask(struct irq_data *d)
}
writel(value, reg);
raw_spin_unlock_irqrestore(&byt_lock, flags);
}
static int byt_irq_type(struct irq_data *d, unsigned int type)
{
struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
irq_hw_number_t hwirq = irqd_to_hwirq(d);
u32 value;
unsigned long flags;
void __iomem *reg;
u32 value;
reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);
if (!reg)
return -EINVAL;
raw_spin_lock_irqsave(&byt_lock, flags);
guard(raw_spinlock_irqsave)(&byt_lock);
value = readl(reg);
WARN(value & BYT_DIRECT_IRQ_EN,
@ -1368,8 +1328,6 @@ static int byt_irq_type(struct irq_data *d, unsigned int type)
else if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(d, handle_level_irq);
raw_spin_unlock_irqrestore(&byt_lock, flags);
return 0;
}
@ -1401,9 +1359,8 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
continue;
}
raw_spin_lock(&byt_lock);
pending = readl(reg);
raw_spin_unlock(&byt_lock);
scoped_guard(raw_spinlock, &byt_lock)
pending = readl(reg);
for_each_set_bit(pin, &pending, 32)
generic_handle_domain_irq(vg->chip.irq.domain, base + pin);
}
@ -1666,10 +1623,9 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
static int byt_gpio_suspend(struct device *dev)
{
struct intel_pinctrl *vg = dev_get_drvdata(dev);
unsigned long flags;
int i;
raw_spin_lock_irqsave(&byt_lock, flags);
guard(raw_spinlock_irqsave)(&byt_lock);
for (i = 0; i < vg->soc->npins; i++) {
void __iomem *reg;
@ -1693,17 +1649,15 @@ static int byt_gpio_suspend(struct device *dev)
vg->context.pads[i].val = value;
}
raw_spin_unlock_irqrestore(&byt_lock, flags);
return 0;
}
static int byt_gpio_resume(struct device *dev)
{
struct intel_pinctrl *vg = dev_get_drvdata(dev);
unsigned long flags;
int i;
raw_spin_lock_irqsave(&byt_lock, flags);
guard(raw_spinlock_irqsave)(&byt_lock);
for (i = 0; i < vg->soc->npins; i++) {
void __iomem *reg;
@ -1743,7 +1697,6 @@ static int byt_gpio_resume(struct device *dev)
}
}
raw_spin_unlock_irqrestore(&byt_lock, flags);
return 0;
}

5
drivers/pinctrl/intel/pinctrl-broxton.c
View File

@ -9,6 +9,7 @@
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
@ -1000,14 +1001,12 @@ static const struct platform_device_id bxt_pinctrl_platform_ids[] = {
};
MODULE_DEVICE_TABLE(platform, bxt_pinctrl_platform_ids);
static INTEL_PINCTRL_PM_OPS(bxt_pinctrl_pm_ops);
static struct platform_driver bxt_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_uid,
.driver = {
.name = "broxton-pinctrl",
.acpi_match_table = bxt_pinctrl_acpi_match,
.pm = &bxt_pinctrl_pm_ops,
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
},
.id_table = bxt_pinctrl_platform_ids,
};

5
drivers/pinctrl/intel/pinctrl-cannonlake.c
View File

@ -10,6 +10,7 @@
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
@ -824,14 +825,12 @@ static const struct acpi_device_id cnl_pinctrl_acpi_match[] = {
};
MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match);
static INTEL_PINCTRL_PM_OPS(cnl_pinctrl_pm_ops);
static struct platform_driver cnl_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "cannonlake-pinctrl",
.acpi_match_table = cnl_pinctrl_acpi_match,
.pm = &cnl_pinctrl_pm_ops,
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
},
};
module_platform_driver(cnl_pinctrl_driver);

5
drivers/pinctrl/intel/pinctrl-cedarfork.c
View File

@ -9,6 +9,7 @@
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
@ -319,8 +320,6 @@ static const struct intel_pinctrl_soc_data cdf_soc_data = {
.ncommunities = ARRAY_SIZE(cdf_communities),
};
static INTEL_PINCTRL_PM_OPS(cdf_pinctrl_pm_ops);
static const struct acpi_device_id cdf_pinctrl_acpi_match[] = {
{ "INTC3001", (kernel_ulong_t)&cdf_soc_data },
{ }
@ -332,7 +331,7 @@ static struct platform_driver cdf_pinctrl_driver = {
.driver = {
.name = "cedarfork-pinctrl",
.acpi_match_table = cdf_pinctrl_acpi_match,
.pm = &cdf_pinctrl_pm_ops,
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
},
};

5
drivers/pinctrl/intel/pinctrl-denverton.c
View File

@ -9,6 +9,7 @@
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
@ -249,8 +250,6 @@ static const struct intel_pinctrl_soc_data dnv_soc_data = {
.ncommunities = ARRAY_SIZE(dnv_communities),
};
static INTEL_PINCTRL_PM_OPS(dnv_pinctrl_pm_ops);
static const struct acpi_device_id dnv_pinctrl_acpi_match[] = {
{ "INTC3000", (kernel_ulong_t)&dnv_soc_data },
{ }
@ -268,7 +267,7 @@ static struct platform_driver dnv_pinctrl_driver = {
.driver = {
.name = "denverton-pinctrl",
.acpi_match_table = dnv_pinctrl_acpi_match,
.pm = &dnv_pinctrl_pm_ops,
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
},
.id_table = dnv_pinctrl_platform_ids,
};

5
drivers/pinctrl/intel/pinctrl-elkhartlake.c
View File

@ -9,6 +9,7 @@
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
@ -485,14 +486,12 @@ static const struct acpi_device_id ehl_pinctrl_acpi_match[] = {
};
MODULE_DEVICE_TABLE(acpi, ehl_pinctrl_acpi_match);
static INTEL_PINCTRL_PM_OPS(ehl_pinctrl_pm_ops);
static struct platform_driver ehl_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_uid,
.driver = {
.name = "elkhartlake-pinctrl",
.acpi_match_table = ehl_pinctrl_acpi_match,
.pm = &ehl_pinctrl_pm_ops,
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
},
};
module_platform_driver(ehl_pinctrl_driver);

5
drivers/pinctrl/intel/pinctrl-emmitsburg.c
View File

@ -9,6 +9,7 @@
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
@ -358,14 +359,12 @@ static const struct acpi_device_id ebg_pinctrl_acpi_match[] = {
};
MODULE_DEVICE_TABLE(acpi, ebg_pinctrl_acpi_match);
static INTEL_PINCTRL_PM_OPS(ebg_pinctrl_pm_ops);
static struct platform_driver ebg_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "emmitsburg-pinctrl",
.acpi_match_table = ebg_pinctrl_acpi_match,
.pm = &ebg_pinctrl_pm_ops,
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
},
};
module_platform_driver(ebg_pinctrl_driver);

5
drivers/pinctrl/intel/pinctrl-geminilake.c
View File

@ -9,6 +9,7 @@
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
@ -447,14 +448,12 @@ static const struct acpi_device_id glk_pinctrl_acpi_match[] = {
};
MODULE_DEVICE_TABLE(acpi, glk_pinctrl_acpi_match);
static INTEL_PINCTRL_PM_OPS(glk_pinctrl_pm_ops);
static struct platform_driver glk_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_uid,
.driver = {
.name = "geminilake-pinctrl",
.acpi_match_table = glk_pinctrl_acpi_match,
.pm = &glk_pinctrl_pm_ops,
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
},
};

5
drivers/pinctrl/intel/pinctrl-icelake.c
View File

@ -10,6 +10,7 @@
#include <linux/acpi.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
@ -668,8 +669,6 @@ static const struct intel_pinctrl_soc_data icln_soc_data = {
.ncommunities = ARRAY_SIZE(icln_communities),
};
static INTEL_PINCTRL_PM_OPS(icl_pinctrl_pm_ops);
static const struct acpi_device_id icl_pinctrl_acpi_match[] = {
{ "INT3455", (kernel_ulong_t)&icllp_soc_data },
{ "INT34C3", (kernel_ulong_t)&icln_soc_data },
@ -682,7 +681,7 @@ static struct platform_driver icl_pinctrl_driver = {
.driver = {
.name = "icelake-pinctrl",
.acpi_match_table = icl_pinctrl_acpi_match,
.pm = &icl_pinctrl_pm_ops,
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
},
};
module_platform_driver(icl_pinctrl_driver);

225
drivers/pinctrl/intel/pinctrl-intel-platform.c Normal file
View File

@ -0,0 +1,225 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Intel PCH pinctrl/GPIO driver
*
* Copyright (C) 2021-2023, Intel Corporation
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/property.h>
#include <linux/string_helpers.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h"
struct intel_platform_pins {
struct pinctrl_pin_desc *pins;
size_t npins;
};
static int intel_platform_pinctrl_prepare_pins(struct device *dev, size_t base,
const char *name, u32 size,
struct intel_platform_pins *pins)
{
struct pinctrl_pin_desc *descs;
char **pin_names;
unsigned int i;
pin_names = devm_kasprintf_strarray(dev, name, size);
if (IS_ERR(pin_names))
return PTR_ERR(pin_names);
descs = devm_krealloc_array(dev, pins->pins, base + size, sizeof(*descs), GFP_KERNEL);
if (!descs)
return -ENOMEM;
for (i = 0; i < size; i++) {
unsigned int pin_number = base + i;
char *pin_name = pin_names[i];
struct pinctrl_pin_desc *desc;
/* Unify delimiter for pin name */
strreplace(pin_name, '-', '_');
desc = &descs[pin_number];
desc->number = pin_number;
desc->name = pin_name;
}
pins->pins = descs;
pins->npins = base + size;
return 0;
}
static int intel_platform_pinctrl_prepare_group(struct device *dev,
struct fwnode_handle *child,
struct intel_padgroup *gpp,
struct intel_platform_pins *pins)
{
size_t base = pins->npins;
const char *name;
u32 size;
int ret;
ret = fwnode_property_read_string(child, "intc-gpio-group-name", &name);
if (ret)
return ret;
ret = fwnode_property_read_u32(child, "intc-gpio-pad-count", &size);
if (ret)
return ret;
ret = intel_platform_pinctrl_prepare_pins(dev, base, name, size, pins);
if (ret)
return ret;
gpp->base = base;
gpp->size = size;
gpp->gpio_base = INTEL_GPIO_BASE_MATCH;
return 0;
}
static int intel_platform_pinctrl_prepare_community(struct device *dev,
struct intel_community *community,
struct intel_platform_pins *pins)
{
struct fwnode_handle *child;
struct intel_padgroup *gpps;
unsigned int group;
size_t ngpps;
u32 offset;
int ret;
ret = device_property_read_u32(dev, "intc-gpio-pad-ownership-offset", &offset);
if (ret)
return ret;
community->padown_offset = offset;
ret = device_property_read_u32(dev, "intc-gpio-pad-configuration-lock-offset", &offset);
if (ret)
return ret;
community->padcfglock_offset = offset;
ret = device_property_read_u32(dev, "intc-gpio-host-software-pad-ownership-offset", &offset);
if (ret)
return ret;
community->hostown_offset = offset;
ret = device_property_read_u32(dev, "intc-gpio-gpi-interrupt-status-offset", &offset);
if (ret)
return ret;
community->is_offset = offset;
ret = device_property_read_u32(dev, "intc-gpio-gpi-interrupt-enable-offset", &offset);
if (ret)
return ret;
community->ie_offset = offset;
ngpps = device_get_child_node_count(dev);
if (!ngpps)
return -ENODEV;
gpps = devm_kcalloc(dev, ngpps, sizeof(*gpps), GFP_KERNEL);
if (!gpps)
return -ENOMEM;
group = 0;
device_for_each_child_node(dev, child) {
struct intel_padgroup *gpp = &gpps[group];
gpp->reg_num = group;
ret = intel_platform_pinctrl_prepare_group(dev, child, gpp, pins);
if (ret)
return ret;
group++;
}
community->ngpps = ngpps;
community->gpps = gpps;
return 0;
}
static int intel_platform_pinctrl_prepare_soc_data(struct device *dev,
struct intel_pinctrl_soc_data *data)
{
struct intel_platform_pins pins = {};
struct intel_community *communities;
size_t ncommunities;
unsigned int i;
int ret;
/* Version 1.0 of the specification assumes only a single community per device node */
ncommunities = 1,
communities = devm_kcalloc(dev, ncommunities, sizeof(*communities), GFP_KERNEL);
if (!communities)
return -ENOMEM;
for (i = 0; i < ncommunities; i++) {
struct intel_community *community = &communities[i];
community->barno = i;
community->pin_base = pins.npins;
ret = intel_platform_pinctrl_prepare_community(dev, community, &pins);
if (ret)
return ret;
community->npins = pins.npins - community->pin_base;
}
data->ncommunities = ncommunities;
data->communities = communities;
data->npins = pins.npins;
data->pins = pins.pins;
return 0;
}
static int intel_platform_pinctrl_probe(struct platform_device *pdev)
{
struct intel_pinctrl_soc_data *data;
struct device *dev = &pdev->dev;
int ret;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
ret = intel_platform_pinctrl_prepare_soc_data(dev, data);
if (ret)
return ret;
return intel_pinctrl_probe(pdev, data);
}
static const struct acpi_device_id intel_platform_pinctrl_acpi_match[] = {
{ "INTC105F" },
{ }
};
MODULE_DEVICE_TABLE(acpi, intel_platform_pinctrl_acpi_match);
static struct platform_driver intel_platform_pinctrl_driver = {
.probe = intel_platform_pinctrl_probe,
.driver = {
.name = "intel-pinctrl",
.acpi_match_table = intel_platform_pinctrl_acpi_match,
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
},
};
module_platform_driver(intel_platform_pinctrl_driver);
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
MODULE_DESCRIPTION("Intel PCH pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(PINCTRL_INTEL);

32
drivers/pinctrl/intel/pinctrl-intel.c
View File

@ -677,10 +677,6 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
u32 term = 0, up = 0, value;
void __iomem *padcfg1;
/* Set default strength value in case none is given */
if (arg == 1)
arg = 5000;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
break;
@ -690,6 +686,7 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
case 20000:
term = PADCFG1_TERM_20K;
break;
case 1: /* Set default strength value in case none is given */
case 5000:
term = PADCFG1_TERM_5K;
break;
@ -716,6 +713,7 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
case 20000:
term = PADCFG1_TERM_20K;
break;
case 1: /* Set default strength value in case none is given */
case 5000:
term = PADCFG1_TERM_5K;
break;
@ -899,7 +897,7 @@ static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
*
* Return: a GPIO offset, or negative error code if translation can't be done.
*/
static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
static int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
{
const struct intel_community *community;
const struct intel_padgroup *padgrp;
@ -1506,8 +1504,8 @@ static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl,
return PTR_ERR_OR_ZERO(pwm);
}
static int intel_pinctrl_probe(struct platform_device *pdev,
const struct intel_pinctrl_soc_data *soc_data)
int intel_pinctrl_probe(struct platform_device *pdev,
const struct intel_pinctrl_soc_data *soc_data)
{
struct device *dev = &pdev->dev;
struct intel_pinctrl *pctrl;
@ -1625,6 +1623,7 @@ static int intel_pinctrl_probe(struct platform_device *pdev,
return 0;
}
EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe, PINCTRL_INTEL);
int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
{
@ -1653,7 +1652,7 @@ EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_uid, PINCTRL_INTEL);
const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev)
{
const struct intel_pinctrl_soc_data * const *table;
const struct intel_pinctrl_soc_data *data = NULL;
const struct intel_pinctrl_soc_data *data;
struct device *dev = &pdev->dev;
table = device_get_match_data(dev);
@ -1662,11 +1661,10 @@ const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_
unsigned int i;
for (i = 0; table[i]; i++) {
if (acpi_dev_uid_match(adev, table[i]->uid)) {
data = table[i];
if (acpi_dev_uid_match(adev, table[i]->uid))
break;
}
}
data = table[i];
} else {
const struct platform_device_id *id;
@ -1682,7 +1680,6 @@ const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_
}
EXPORT_SYMBOL_NS_GPL(intel_pinctrl_get_soc_data, PINCTRL_INTEL);
#ifdef CONFIG_PM_SLEEP
static bool __intel_gpio_is_direct_irq(u32 value)
{
return (value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) &&
@ -1728,7 +1725,7 @@ static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int
return false;
}
int intel_pinctrl_suspend_noirq(struct device *dev)
static int intel_pinctrl_suspend_noirq(struct device *dev)
{
struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
struct intel_community_context *communities;
@ -1771,7 +1768,6 @@ int intel_pinctrl_suspend_noirq(struct device *dev)
return 0;
}
EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
{
@ -1838,7 +1834,7 @@ static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin,
dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg));
}
int intel_pinctrl_resume_noirq(struct device *dev)
static int intel_pinctrl_resume_noirq(struct device *dev)
{
struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
const struct intel_community_context *communities;
@ -1882,8 +1878,10 @@ int intel_pinctrl_resume_noirq(struct device *dev)
return 0;
}
EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq);
#endif
EXPORT_NS_GPL_DEV_SLEEP_PM_OPS(intel_pinctrl_pm_ops, PINCTRL_INTEL) = {
NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq, intel_pinctrl_resume_noirq)
};
MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");

14
drivers/pinctrl/intel/pinctrl-intel.h
View File

@ -252,19 +252,13 @@ struct intel_pinctrl {
int irq;
};
int intel_pinctrl_probe(struct platform_device *pdev,
const struct intel_pinctrl_soc_data *soc_data);
int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
#ifdef CONFIG_PM_SLEEP
int intel_pinctrl_suspend_noirq(struct device *dev);
int intel_pinctrl_resume_noirq(struct device *dev);
#endif
#define INTEL_PINCTRL_PM_OPS(_name) \
const struct dev_pm_ops _name = { \
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq, \
intel_pinctrl_resume_noirq) \
}
extern const struct dev_pm_ops intel_pinctrl_pm_ops;
struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, unsigned int pin);

5
drivers/pinctrl/intel/pinctrl-jasperlake.c
View File

@ -9,6 +9,7 @@
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
@ -326,14 +327,12 @@ static const struct acpi_device_id jsl_pinctrl_acpi_match[] = {
};
MODULE_DEVICE_TABLE(acpi, jsl_pinctrl_acpi_match);
static INTEL_PINCTRL_PM_OPS(jsl_pinctrl_pm_ops);
static struct platform_driver jsl_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "jasperlake-pinctrl",
.acpi_match_table = jsl_pinctrl_acpi_match,
.pm = &jsl_pinctrl_pm_ops,
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
},
};
module_platform_driver(jsl_pinctrl_driver);

5
drivers/pinctrl/intel/pinctrl-lakefield.c
View File

@ -9,6 +9,7 @@
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
@ -347,14 +348,12 @@ static const struct acpi_device_id lkf_pinctrl_acpi_match[] = {
};
MODULE_DEVICE_TABLE(acpi, lkf_pinctrl_acpi_match);
static INTEL_PINCTRL_PM_OPS(lkf_pinctrl_pm_ops);
static struct platform_driver lkf_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "lakefield-pinctrl",
.acpi_match_table = lkf_pinctrl_acpi_match,
.pm = &lkf_pinctrl_pm_ops,
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
},
};
module_platform_driver(lkf_pinctrl_driver);

5
drivers/pinctrl/intel/pinctrl-lewisburg.c
View File

@ -9,6 +9,7 @@
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
@ -301,8 +302,6 @@ static const struct intel_pinctrl_soc_data lbg_soc_data = {
.ncommunities = ARRAY_SIZE(lbg_communities),
};
static INTEL_PINCTRL_PM_OPS(lbg_pinctrl_pm_ops);
static const struct acpi_device_id lbg_pinctrl_acpi_match[] = {
{ "INT3536", (kernel_ulong_t)&lbg_soc_data },
{ }
@ -314,7 +313,7 @@ static struct platform_driver lbg_pinctrl_driver = {
.driver = {
.name = "lewisburg-pinctrl",
.acpi_match_table = lbg_pinctrl_acpi_match,
.pm = &lbg_pinctrl_pm_ops,
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
},
};
module_platform_driver(lbg_pinctrl_driver);

72
drivers/pinctrl/intel/pinctrl-lynxpoint.c
View File

@ -10,6 +10,7 @@
#include <linux/acpi.h>
#include <linux/array_size.h>
#include <linux/bitops.h>
#include <linux/cleanup.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/io.h>
@ -291,10 +292,9 @@ static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev,
{
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
const struct intel_pingroup *grp = &lg->soc->groups[group];
unsigned long flags;
int i;
raw_spin_lock_irqsave(&lg->lock, flags);
guard(raw_spinlock_irqsave)(&lg->lock);
/* Now enable the mux setting for each pin in the group */
for (i = 0; i < grp->grp.npins; i++) {
@ -312,8 +312,6 @@ static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev,
iowrite32(value, reg);
}
raw_spin_unlock_irqrestore(&lg->lock, flags);
return 0;
}
@ -334,10 +332,9 @@ static int lp_gpio_request_enable(struct pinctrl_dev *pctldev,
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
unsigned long flags;
u32 value;
raw_spin_lock_irqsave(&lg->lock, flags);
guard(raw_spinlock_irqsave)(&lg->lock);
/*
* Reconfigure pin to GPIO mode if needed and issue a warning,
@ -352,8 +349,6 @@ static int lp_gpio_request_enable(struct pinctrl_dev *pctldev,
/* Enable input sensing */
lp_gpio_enable_input(conf2);
raw_spin_unlock_irqrestore(&lg->lock, flags);
return 0;
}
@ -363,14 +358,11 @@ static void lp_gpio_disable_free(struct pinctrl_dev *pctldev,
{
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
unsigned long flags;
raw_spin_lock_irqsave(&lg->lock, flags);
guard(raw_spinlock_irqsave)(&lg->lock);
/* Disable input sensing */
lp_gpio_disable_input(conf2);
raw_spin_unlock_irqrestore(&lg->lock, flags);
}
static int lp_gpio_set_direction(struct pinctrl_dev *pctldev,
@ -379,10 +371,9 @@ static int lp_gpio_set_direction(struct pinctrl_dev *pctldev,
{
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
unsigned long flags;
u32 value;
raw_spin_lock_irqsave(&lg->lock, flags);
guard(raw_spinlock_irqsave)(&lg->lock);
value = ioread32(reg);
value &= ~DIR_BIT;
@ -400,8 +391,6 @@ static int lp_gpio_set_direction(struct pinctrl_dev *pctldev,
}
iowrite32(value, reg);
raw_spin_unlock_irqrestore(&lg->lock, flags);
return 0;
}
@ -421,13 +410,11 @@ static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
enum pin_config_param param = pinconf_to_config_param(*config);
unsigned long flags;
u32 value, pull;
u16 arg;
raw_spin_lock_irqsave(&lg->lock, flags);
value = ioread32(conf2);
raw_spin_unlock_irqrestore(&lg->lock, flags);
scoped_guard(raw_spinlock_irqsave, &lg->lock)
value = ioread32(conf2);
pull = value & GPIWP_MASK;
@ -464,11 +451,10 @@ static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
enum pin_config_param param;
unsigned long flags;
int i, ret = 0;
unsigned int i;
u32 value;
raw_spin_lock_irqsave(&lg->lock, flags);
guard(raw_spinlock_irqsave)(&lg->lock);
value = ioread32(conf2);
@ -489,19 +475,13 @@ static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
value |= GPIWP_UP;
break;
default:
ret = -ENOTSUPP;
return -ENOTSUPP;
}
if (ret)
break;
}
if (!ret)
iowrite32(value, conf2);
iowrite32(value, conf2);
raw_spin_unlock_irqrestore(&lg->lock, flags);
return ret;
return 0;
}
static const struct pinconf_ops lptlp_pinconf_ops = {
@ -527,16 +507,13 @@ static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
{
struct intel_pinctrl *lg = gpiochip_get_data(chip);
void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
unsigned long flags;
raw_spin_lock_irqsave(&lg->lock, flags);
guard(raw_spinlock_irqsave)(&lg->lock);
if (value)
iowrite32(ioread32(reg) | OUT_LVL_BIT, reg);
else
iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg);
raw_spin_unlock_irqrestore(&lg->lock, flags);
}
static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
@ -592,11 +569,10 @@ static void lp_irq_ack(struct irq_data *d)
struct intel_pinctrl *lg = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT);
unsigned long flags;
raw_spin_lock_irqsave(&lg->lock, flags);
guard(raw_spinlock_irqsave)(&lg->lock);
iowrite32(BIT(hwirq % 32), reg);
raw_spin_unlock_irqrestore(&lg->lock, flags);
}
static void lp_irq_unmask(struct irq_data *d)
@ -613,13 +589,11 @@ static void lp_irq_enable(struct irq_data *d)
struct intel_pinctrl *lg = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
unsigned long flags;
gpiochip_enable_irq(gc, hwirq);
raw_spin_lock_irqsave(&lg->lock, flags);
iowrite32(ioread32(reg) | BIT(hwirq % 32), reg);
raw_spin_unlock_irqrestore(&lg->lock, flags);
scoped_guard(raw_spinlock_irqsave, &lg->lock)
iowrite32(ioread32(reg) | BIT(hwirq % 32), reg);
}
static void lp_irq_disable(struct irq_data *d)
@ -628,11 +602,9 @@ static void lp_irq_disable(struct irq_data *d)
struct intel_pinctrl *lg = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
unsigned long flags;
raw_spin_lock_irqsave(&lg->lock, flags);
iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg);
raw_spin_unlock_irqrestore(&lg->lock, flags);
scoped_guard(raw_spinlock_irqsave, &lg->lock)
iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg);
gpiochip_disable_irq(gc, hwirq);
}
@ -642,7 +614,6 @@ static int lp_irq_set_type(struct irq_data *d, unsigned int type)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *lg = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
unsigned long flags;
void __iomem *reg;
u32 value;
@ -656,7 +627,8 @@ static int lp_irq_set_type(struct irq_data *d, unsigned int type)
return -EBUSY;
}
raw_spin_lock_irqsave(&lg->lock, flags);
guard(raw_spinlock_irqsave)(&lg->lock);
value = ioread32(reg);
/* set both TRIG_SEL and INV bits to 0 for rising edge */
@ -682,8 +654,6 @@ static int lp_irq_set_type(struct irq_data *d, unsigned int type)
else if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(d, handle_level_irq);
raw_spin_unlock_irqrestore(&lg->lock, flags);
return 0;
}

5
drivers/pinctrl/intel/pinctrl-meteorlake.c
View File

@ -9,6 +9,7 @@
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
@ -589,14 +590,12 @@ static const struct acpi_device_id mtl_pinctrl_acpi_match[] = {
};
MODULE_DEVICE_TABLE(acpi, mtl_pinctrl_acpi_match);
static INTEL_PINCTRL_PM_OPS(mtl_pinctrl_pm_ops);
static struct platform_driver mtl_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "meteorlake-pinctrl",
.acpi_match_table = mtl_pinctrl_acpi_match,
.pm = &mtl_pinctrl_pm_ops,
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
},
};
module_platform_driver(mtl_pinctrl_driver);

465
drivers/pinctrl/intel/pinctrl-meteorpoint.c Normal file
View File

@ -0,0 +1,465 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Meteor Point PCH pinctrl/GPIO driver
*
* Copyright (C) 2022-2023, Intel Corporation
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h"
#define MTP_PAD_OWN 0x0b0
#define MTP_PADCFGLOCK 0x110
#define MTP_HOSTSW_OWN 0x150
#define MTP_GPI_IS 0x200
#define MTP_GPI_IE 0x220
#define MTP_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define MTP_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, MTP)
/* Meteor Point-S */
static const struct pinctrl_pin_desc mtps_pins[] = {
/* GPP_D */
PINCTRL_PIN(0, "GPP_D_0"),
PINCTRL_PIN(1, "GPP_D_1"),
PINCTRL_PIN(2, "GPP_D_2"),
PINCTRL_PIN(3, "GPP_D_3"),
PINCTRL_PIN(4, "GPP_D_4"),
PINCTRL_PIN(5, "CNV_RF_RESET_B"),
PINCTRL_PIN(6, "CRF_CLKREQ"),
PINCTRL_PIN(7, "GPP_D_7"),
PINCTRL_PIN(8, "GPP_D_8"),
PINCTRL_PIN(9, "SML0CLK"),
PINCTRL_PIN(10, "SML0DATA"),
PINCTRL_PIN(11, "GPP_D_11"),
PINCTRL_PIN(12, "GPP_D_12"),
PINCTRL_PIN(13, "GPP_D_13"),
PINCTRL_PIN(14, "GPP_D_14"),
PINCTRL_PIN(15, "GPP_D_15"),
PINCTRL_PIN(16, "GPP_D_16"),
PINCTRL_PIN(17, "GPP_D_17"),
PINCTRL_PIN(18, "GPP_D_18"),
PINCTRL_PIN(19, "GPP_D_19"),
PINCTRL_PIN(20, "GPP_D_20"),
PINCTRL_PIN(21, "GPP_D_21"),
PINCTRL_PIN(22, "GPP_D_22"),
PINCTRL_PIN(23, "GPP_D_23"),
PINCTRL_PIN(24, "GSPI3_CLK_LOOPBK"),
/* GPP_R */
PINCTRL_PIN(25, "HDA_BCLK"),
PINCTRL_PIN(26, "HDA_SYNC"),
PINCTRL_PIN(27, "HDA_SDO"),
PINCTRL_PIN(28, "HDA_SDI_0"),
PINCTRL_PIN(29, "HDA_RSTB"),
PINCTRL_PIN(30, "GPP_R_5"),
PINCTRL_PIN(31, "GPP_R_6"),
PINCTRL_PIN(32, "GPP_R_7"),
PINCTRL_PIN(33, "GPP_R_8"),
PINCTRL_PIN(34, "GPP_R_9"),
PINCTRL_PIN(35, "GPP_R_10"),
PINCTRL_PIN(36, "GPP_R_11"),
PINCTRL_PIN(37, "GPP_R_12"),
PINCTRL_PIN(38, "GSPI2_CLK_LOOPBK"),
/* GPP_J */
PINCTRL_PIN(39, "GPP_J_0"),
PINCTRL_PIN(40, "CNV_BRI_DT"),
PINCTRL_PIN(41, "CNV_BRI_RSP"),
PINCTRL_PIN(42, "CNV_RGI_DT"),
PINCTRL_PIN(43, "CNV_RGI_RSP"),
PINCTRL_PIN(44, "GPP_J_5"),
PINCTRL_PIN(45, "GPP_J_6"),
PINCTRL_PIN(46, "BOOTHALT_B"),
PINCTRL_PIN(47, "RTCCLKOUT"),
PINCTRL_PIN(48, "BPKI3C_SDA"),
PINCTRL_PIN(49, "BPKI3C_SCL"),
PINCTRL_PIN(50, "DAM"),
PINCTRL_PIN(51, "HDACPU_SDI"),
PINCTRL_PIN(52, "HDACPU_SDO"),
PINCTRL_PIN(53, "HDACPU_BCLK"),
PINCTRL_PIN(54, "AUX_PWRGD"),
PINCTRL_PIN(55, "GLB_RST_WARN_B"),
PINCTRL_PIN(56, "RESET_SYNCB"),
/* vGPIO */
PINCTRL_PIN(57, "CNV_BTEN"),
PINCTRL_PIN(58, "CNV_BT_HOST_WAKEB"),
PINCTRL_PIN(59, "CNV_BT_IF_SELECT"),
PINCTRL_PIN(60, "vCNV_BT_UART_TXD"),
PINCTRL_PIN(61, "vCNV_BT_UART_RXD"),
PINCTRL_PIN(62, "vCNV_BT_UART_CTS_B"),
PINCTRL_PIN(63, "vCNV_BT_UART_RTS_B"),
PINCTRL_PIN(64, "vCNV_MFUART1_TXD"),
PINCTRL_PIN(65, "vCNV_MFUART1_RXD"),
PINCTRL_PIN(66, "vCNV_MFUART1_CTS_B"),
PINCTRL_PIN(67, "vCNV_MFUART1_RTS_B"),
PINCTRL_PIN(68, "vUART0_TXD"),
PINCTRL_PIN(69, "vUART0_RXD"),
PINCTRL_PIN(70, "vUART0_CTS_B"),
PINCTRL_PIN(71, "vUART0_RTS_B"),
PINCTRL_PIN(72, "vISH_UART0_TXD"),
PINCTRL_PIN(73, "vISH_UART0_RXD"),
PINCTRL_PIN(74, "vISH_UART0_CTS_B"),
PINCTRL_PIN(75, "vISH_UART0_RTS_B"),
PINCTRL_PIN(76, "vCNV_BT_I2S_BCLK"),
PINCTRL_PIN(77, "vCNV_BT_I2S_WS_SYNC"),
PINCTRL_PIN(78, "vCNV_BT_I2S_SDO"),
PINCTRL_PIN(79, "vCNV_BT_I2S_SDI"),
PINCTRL_PIN(80, "vI2S2_SCLK"),
PINCTRL_PIN(81, "vI2S2_SFRM"),
PINCTRL_PIN(82, "vI2S2_TXD"),
PINCTRL_PIN(83, "vI2S2_RXD"),
PINCTRL_PIN(84, "THC0_WOT_INT"),
PINCTRL_PIN(85, "THC1_WOT_INT"),
PINCTRL_PIN(86, "THC0_WHC_INT"),
PINCTRL_PIN(87, "THC1_WHC_INT"),
/* GPP_A */
PINCTRL_PIN(88, "ESPI_IO_0"),
PINCTRL_PIN(89, "ESPI_IO_1"),
PINCTRL_PIN(90, "ESPI_IO_2"),
PINCTRL_PIN(91, "ESPI_IO_3"),
PINCTRL_PIN(92, "ESPI_CS0B"),
PINCTRL_PIN(93, "ESPI_CLK"),
PINCTRL_PIN(94, "ESPI_RESETB"),
PINCTRL_PIN(95, "ESPI_CS1B"),
PINCTRL_PIN(96, "ESPI_CS2B"),
PINCTRL_PIN(97, "ESPI_CS3B"),
PINCTRL_PIN(98, "ESPI_ALERT0B"),
PINCTRL_PIN(99, "ESPI_ALERT1B"),
PINCTRL_PIN(100, "ESPI_ALERT2B"),
PINCTRL_PIN(101, "ESPI_ALERT3B"),
PINCTRL_PIN(102, "ESPI_CLK_LOOPBK"),
/* DIR_ESPI */
PINCTRL_PIN(103, "PWRBTNB_OUT"),
PINCTRL_PIN(104, "DMI_PERSTB"),
PINCTRL_PIN(105, "DMI_CLKREQB"),
PINCTRL_PIN(106, "DIR_ESPI_IO_0"),
PINCTRL_PIN(107, "DIR_ESPI_IO_1"),
PINCTRL_PIN(108, "DIR_ESPI_IO_2"),
PINCTRL_PIN(109, "DIR_ESPI_IO_3"),
PINCTRL_PIN(110, "DIR_ESPI_CSB"),
PINCTRL_PIN(111, "DIR_ESPI_RESETB"),
PINCTRL_PIN(112, "DIR_ESPI_CLK"),
PINCTRL_PIN(113, "DIR_ESPI_RCLK"),
PINCTRL_PIN(114, "DIR_ESPI_ALERTB"),
/* GPP_B */
PINCTRL_PIN(115, "GPP_B_0"),
PINCTRL_PIN(116, "GPP_B_1"),
PINCTRL_PIN(117, "GPP_B_2"),
PINCTRL_PIN(118, "GPP_B_3"),
PINCTRL_PIN(119, "GPP_B_4"),
PINCTRL_PIN(120, "GPP_B_5"),
PINCTRL_PIN(121, "CLKOUT_48"),
PINCTRL_PIN(122, "GPP_B_7"),
PINCTRL_PIN(123, "GPP_B_8"),
PINCTRL_PIN(124, "GPP_B_9"),
PINCTRL_PIN(125, "GPP_B_10"),
PINCTRL_PIN(126, "GPP_B_11"),
PINCTRL_PIN(127, "SLP_S0B"),
PINCTRL_PIN(128, "PLTRSTB"),
PINCTRL_PIN(129, "GPP_B_14"),
PINCTRL_PIN(130, "GPP_B_15"),
PINCTRL_PIN(131, "GPP_B_16"),
PINCTRL_PIN(132, "GPP_B_17"),
PINCTRL_PIN(133, "GPP_B_18"),
PINCTRL_PIN(134, "FUSA_DIAGTEST_EN"),
PINCTRL_PIN(135, "FUSA_DIAGTEST_MODE"),
PINCTRL_PIN(136, "GPP_B_21"),
/* SPI0 */
PINCTRL_PIN(137, "SPI0_IO_2"),
PINCTRL_PIN(138, "SPI0_IO_3"),
PINCTRL_PIN(139, "SPI0_MOSI_IO_0"),
PINCTRL_PIN(140, "SPI0_MISO_IO_1"),
PINCTRL_PIN(141, "SPI0_TPM_CSB"),
PINCTRL_PIN(142, "SPI0_FLASH_0_CSB"),
PINCTRL_PIN(143, "SPI0_FLASH_1_CSB"),
PINCTRL_PIN(144, "SPI0_CLK"),
PINCTRL_PIN(145, "SPI0_CLK_LOOPBK"),
/* GPP_C */
PINCTRL_PIN(146, "SMBCLK"),
PINCTRL_PIN(147, "SMBDATA"),
PINCTRL_PIN(148, "SMBALERTB"),
PINCTRL_PIN(149, "GPP_C_3"),
PINCTRL_PIN(150, "GPP_C_4"),
PINCTRL_PIN(151, "GPP_C_5"),
PINCTRL_PIN(152, "GPP_C_6"),
PINCTRL_PIN(153, "GPP_C_7"),
PINCTRL_PIN(154, "GPP_C_8"),
PINCTRL_PIN(155, "GPP_C_9"),
PINCTRL_PIN(156, "GPP_C_10"),
PINCTRL_PIN(157, "GPP_C_11"),
PINCTRL_PIN(158, "GPP_C_12"),
PINCTRL_PIN(159, "GPP_C_13"),
PINCTRL_PIN(160, "GPP_C_14"),
PINCTRL_PIN(161, "GPP_C_15"),
PINCTRL_PIN(162, "GPP_C_16"),
PINCTRL_PIN(163, "GPP_C_17"),
PINCTRL_PIN(164, "GPP_C_18"),
PINCTRL_PIN(165, "GPP_C_19"),
PINCTRL_PIN(166, "GPP_C_20"),
PINCTRL_PIN(167, "GPP_C_21"),
PINCTRL_PIN(168, "GPP_C_22"),
PINCTRL_PIN(169, "GPP_C_23"),
/* GPP_H */
PINCTRL_PIN(170, "GPP_H_0"),
PINCTRL_PIN(171, "GPP_H_1"),
PINCTRL_PIN(172, "GPP_H_2"),
PINCTRL_PIN(173, "GPP_H_3"),
PINCTRL_PIN(174, "GPP_H_4"),
PINCTRL_PIN(175, "GPP_H_5"),
PINCTRL_PIN(176, "GPP_H_6"),
PINCTRL_PIN(177, "GPP_H_7"),
PINCTRL_PIN(178, "GPP_H_8"),
PINCTRL_PIN(179, "GPP_H_9"),
PINCTRL_PIN(180, "GPP_H_10"),
PINCTRL_PIN(181, "GPP_H_11"),
PINCTRL_PIN(182, "GPP_H_12"),
PINCTRL_PIN(183, "GPP_H_13"),
PINCTRL_PIN(184, "GPP_H_14"),
PINCTRL_PIN(185, "GPP_H_15"),
PINCTRL_PIN(186, "GPP_H_16"),
PINCTRL_PIN(187, "GPP_H_17"),
PINCTRL_PIN(188, "GPP_H_18"),
PINCTRL_PIN(189, "GPP_H_19"),
/* vGPIO_3 */
PINCTRL_PIN(190, "CPU_PCIE_LNK_DN_0"),
PINCTRL_PIN(191, "CPU_PCIE_LNK_DN_1"),
PINCTRL_PIN(192, "CPU_PCIE_LNK_DN_2"),
PINCTRL_PIN(193, "CPU_PCIE_LNK_DN_3"),
/* vGPIO_0 */
PINCTRL_PIN(194, "ESPI_USB_OCB_0"),
PINCTRL_PIN(195, "ESPI_USB_OCB_1"),
PINCTRL_PIN(196, "ESPI_USB_OCB_2"),
PINCTRL_PIN(197, "ESPI_USB_OCB_3"),
PINCTRL_PIN(198, "USB_CPU_OCB_0"),
PINCTRL_PIN(199, "USB_CPU_OCB_1"),
PINCTRL_PIN(200, "USB_CPU_OCB_2"),
PINCTRL_PIN(201, "USB_CPU_OCB_3"),
/* vGPIO_4 */
PINCTRL_PIN(202, "ESPI_ISCLK_XTAL_CLKREQ"),
PINCTRL_PIN(203, "ISCLK_ESPI_XTAL_CLKACK"),
PINCTRL_PIN(204, "ME_SLPC_FTPM_ENABLE"),
PINCTRL_PIN(205, "GP_SLPC_DTFUS_CORE_SPITPM_DIS"),
PINCTRL_PIN(206, "GP_SLPC_SPI_STRAP_TOS"),
PINCTRL_PIN(207, "GP_SLPC_DTFUS_CORE_SPITPM_DIS_L01"),
PINCTRL_PIN(208, "GP_SLPC_SPI_STRAP_TOS_L01"),
PINCTRL_PIN(209, "LPC_PRR_TS_OVR"),
PINCTRL_PIN(210, "ITSS_KU1_SHTDWN"),
PINCTRL_PIN(211, "vGPIO_SPARE_0"),
PINCTRL_PIN(212, "vGPIO_SPARE_1"),
PINCTRL_PIN(213, "vGPIO_SPARE_2"),
PINCTRL_PIN(214, "vGPIO_SPARE_3"),
PINCTRL_PIN(215, "vGPIO_SPARE_4"),
PINCTRL_PIN(216, "vGPIO_SPARE_5"),
PINCTRL_PIN(217, "vGPIO_SPARE_6"),
PINCTRL_PIN(218, "vGPIO_SPARE_7"),
PINCTRL_PIN(219, "vGPIO_SPARE_8"),
PINCTRL_PIN(220, "vGPIO_SPARE_9"),
PINCTRL_PIN(221, "vGPIO_SPARE_10"),
PINCTRL_PIN(222, "vGPIO_SPARE_11"),
PINCTRL_PIN(223, "vGPIO_SPARE_12"),
PINCTRL_PIN(224, "vGPIO_SPARE_13"),
PINCTRL_PIN(225, "vGPIO_SPARE_14"),
PINCTRL_PIN(226, "vGPIO_SPARE_15"),
PINCTRL_PIN(227, "vGPIO_SPARE_16"),
PINCTRL_PIN(228, "vGPIO_SPARE_17"),
PINCTRL_PIN(229, "vGPIO_SPARE_18"),
PINCTRL_PIN(230, "vGPIO_SPARE_19"),
PINCTRL_PIN(231, "vGPIO_SPARE_20"),
PINCTRL_PIN(232, "vGPIO_SPARE_21"),
/* GPP_S */
PINCTRL_PIN(233, "GPP_S_0"),
PINCTRL_PIN(234, "GPP_S_1"),
PINCTRL_PIN(235, "GPP_S_2"),
PINCTRL_PIN(236, "GPP_S_3"),
PINCTRL_PIN(237, "GPP_S_4"),
PINCTRL_PIN(238, "GPP_S_5"),
PINCTRL_PIN(239, "GPP_S_6"),
PINCTRL_PIN(240, "GPP_S_7"),
/* GPP_E */
PINCTRL_PIN(241, "GPP_E_0"),
PINCTRL_PIN(242, "GPP_E_1"),
PINCTRL_PIN(243, "GPP_E_2"),
PINCTRL_PIN(244, "GPP_E_3"),
PINCTRL_PIN(245, "GPP_E_4"),
PINCTRL_PIN(246, "GPP_E_5"),
PINCTRL_PIN(247, "GPP_E_6"),
PINCTRL_PIN(248, "GPP_E_7"),
PINCTRL_PIN(249, "GPP_E_8"),
PINCTRL_PIN(250, "GPP_E_9"),
PINCTRL_PIN(251, "GPP_E_10"),
PINCTRL_PIN(252, "GPP_E_11"),
PINCTRL_PIN(253, "GPP_E_12"),
PINCTRL_PIN(254, "GPP_E_13"),
PINCTRL_PIN(255, "GPP_E_14"),
PINCTRL_PIN(256, "GPP_E_15"),
PINCTRL_PIN(257, "GPP_E_16"),
PINCTRL_PIN(258, "GPP_E_17"),
PINCTRL_PIN(259, "GPP_E_18"),
PINCTRL_PIN(260, "GPP_E_19"),
PINCTRL_PIN(261, "GPP_E_20"),
PINCTRL_PIN(262, "GPP_E_21"),
PINCTRL_PIN(263, "SPI1_CLK_LOOPBK"),
/* GPP_K */
PINCTRL_PIN(264, "GPP_K_0"),
PINCTRL_PIN(265, "GPP_K_1"),
PINCTRL_PIN(266, "GPP_K_2"),
PINCTRL_PIN(267, "GPP_K_3"),
PINCTRL_PIN(268, "GPP_K_4"),
PINCTRL_PIN(269, "GPP_K_5"),
PINCTRL_PIN(270, "FUSE_SORT_BUMP_0"),
PINCTRL_PIN(271, "FUSE_SORT_BUMP_1"),
PINCTRL_PIN(272, "CORE_VID_0"),
PINCTRL_PIN(273, "CORE_VID_1"),
PINCTRL_PIN(274, "FUSE_SORT_BUMP_2"),
PINCTRL_PIN(275, "MISC_SPARE"),
PINCTRL_PIN(276, "SYS_RESETB"),
PINCTRL_PIN(277, "MLK_RSTB"),
/* GPP_F */
PINCTRL_PIN(278, "SATAXPCIE_3"),
PINCTRL_PIN(279, "SATAXPCIE_4"),
PINCTRL_PIN(280, "SATAXPCIE_5"),
PINCTRL_PIN(281, "SATAXPCIE_6"),
PINCTRL_PIN(282, "SATAXPCIE_7"),
PINCTRL_PIN(283, "SATA_DEVSLP_3"),
PINCTRL_PIN(284, "SATA_DEVSLP_4"),
PINCTRL_PIN(285, "SATA_DEVSLP_5"),
PINCTRL_PIN(286, "SATA_DEVSLP_6"),
PINCTRL_PIN(287, "GPP_F_9"),
PINCTRL_PIN(288, "GPP_F_10"),
PINCTRL_PIN(289, "GPP_F_11"),
PINCTRL_PIN(290, "GPP_F_12"),
PINCTRL_PIN(291, "GPP_F_13"),
PINCTRL_PIN(292, "GPP_F_14"),
PINCTRL_PIN(293, "GPP_F_15"),
PINCTRL_PIN(294, "GPP_F_16"),
PINCTRL_PIN(295, "GPP_F_17"),
PINCTRL_PIN(296, "GPP_F_18"),
PINCTRL_PIN(297, "DNX_FORCE_RELOAD"),
PINCTRL_PIN(298, "GPP_F_20"),
PINCTRL_PIN(299, "GPP_F_21"),
PINCTRL_PIN(300, "GPP_F_22"),
PINCTRL_PIN(301, "GPP_F_23"),
/* GPP_I */
PINCTRL_PIN(302, "GPP_I_0"),
PINCTRL_PIN(303, "GPP_I_1"),
PINCTRL_PIN(304, "GPP_I_2"),
PINCTRL_PIN(305, "GPP_I_3"),
PINCTRL_PIN(306, "GPP_I_4"),
PINCTRL_PIN(307, "GPP_I_5"),
PINCTRL_PIN(308, "GPP_I_6"),
PINCTRL_PIN(309, "GPP_I_7"),
PINCTRL_PIN(310, "GPP_I_8"),
PINCTRL_PIN(311, "GPP_I_9"),
PINCTRL_PIN(312, "GPP_I_10"),
PINCTRL_PIN(313, "GPP_I_11"),
PINCTRL_PIN(314, "GPP_I_12"),
PINCTRL_PIN(315, "GPP_I_13"),
PINCTRL_PIN(316, "GPP_I_14"),
PINCTRL_PIN(317, "GPP_I_15"),
PINCTRL_PIN(318, "GPP_I_16"),
PINCTRL_PIN(319, "GSPI0_CLK_LOOPBK"),
PINCTRL_PIN(320, "GSPI1_CLK_LOOPBK"),
PINCTRL_PIN(321, "ISH_I3C0_CLK_LOOPBK"),
PINCTRL_PIN(322, "I3C0_CLK_LOOPBK"),
/* JTAG_CPU */
PINCTRL_PIN(323, "JTAG_TDO"),
PINCTRL_PIN(324, "JTAGX"),
PINCTRL_PIN(325, "PRDYB"),
PINCTRL_PIN(326, "PREQB"),
PINCTRL_PIN(327, "JTAG_TDI"),
PINCTRL_PIN(328, "JTAG_TMS"),
PINCTRL_PIN(329, "JTAG_TCK"),
PINCTRL_PIN(330, "DBG_PMODE"),
PINCTRL_PIN(331, "CPU_TRSTB"),
PINCTRL_PIN(332, "CPUPWRGD"),
PINCTRL_PIN(333, "PM_SPARE0"),
PINCTRL_PIN(334, "PM_SPARE1"),
PINCTRL_PIN(335, "CRASHLOG_TRIG_N"),
PINCTRL_PIN(336, "TRIGGER_IN"),
PINCTRL_PIN(337, "TRIGGER_OUT"),
PINCTRL_PIN(338, "FBRK_OUT_N"),
};
static const struct intel_padgroup mtps_community0_gpps[] = {
MTP_GPP(0, 0, 24, 0), /* GPP_D */
MTP_GPP(1, 25, 38, 32), /* GPP_R */
MTP_GPP(2, 39, 56, 64), /* GPP_J */
MTP_GPP(3, 57, 87, 96), /* vGPIO */
};
static const struct intel_padgroup mtps_community1_gpps[] = {
MTP_GPP(0, 88, 102, 128), /* GPP_A */
MTP_GPP(1, 103, 114, 160), /* DIR_ESPI */
MTP_GPP(2, 115, 136, 192), /* GPP_B */
};
static const struct intel_padgroup mtps_community3_gpps[] = {
MTP_GPP(0, 137, 145, 224), /* SPI0 */
MTP_GPP(1, 146, 169, 256), /* GPP_C */
MTP_GPP(2, 170, 189, 288), /* GPP_H */
MTP_GPP(3, 190, 193, 320), /* vGPIO_3 */
MTP_GPP(4, 194, 201, 352), /* vGPIO_0 */
MTP_GPP(5, 202, 232, 384), /* vGPIO_4 */
};
static const struct intel_padgroup mtps_community4_gpps[] = {
MTP_GPP(0, 233, 240, 416), /* GPP_S */
MTP_GPP(1, 241, 263, 448), /* GPP_E */
MTP_GPP(2, 264, 277, 480), /* GPP_K */
MTP_GPP(3, 278, 301, 512), /* GPP_F */
};
static const struct intel_padgroup mtps_community5_gpps[] = {
MTP_GPP(0, 302, 322, 544), /* GPP_I */
MTP_GPP(1, 323, 338, 576), /* JTAG_CPU */
};
static const struct intel_community mtps_communities[] = {
MTP_COMMUNITY(0, 0, 87, mtps_community0_gpps),
MTP_COMMUNITY(1, 88, 136, mtps_community1_gpps),
MTP_COMMUNITY(2, 137, 232, mtps_community3_gpps),
MTP_COMMUNITY(3, 233, 301, mtps_community4_gpps),
MTP_COMMUNITY(4, 302, 338, mtps_community5_gpps),
};
static const struct intel_pinctrl_soc_data mtps_soc_data = {
.pins = mtps_pins,
.npins = ARRAY_SIZE(mtps_pins),
.communities = mtps_communities,
.ncommunities = ARRAY_SIZE(mtps_communities),
};
static const struct acpi_device_id mtp_pinctrl_acpi_match[] = {
{ "INTC1084", (kernel_ulong_t)&mtps_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, mtp_pinctrl_acpi_match);
static struct platform_driver mtp_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "meteorpoint-pinctrl",
.acpi_match_table = mtp_pinctrl_acpi_match,
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
},
};
module_platform_driver(mtp_pinctrl_driver);
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
MODULE_DESCRIPTION("Intel Meteor Point PCH pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(PINCTRL_INTEL);

5
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
View File

@ -10,6 +10,7 @@
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
@ -579,14 +580,12 @@ static const struct acpi_device_id spt_pinctrl_acpi_match[] = {
};
MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match);
static INTEL_PINCTRL_PM_OPS(spt_pinctrl_pm_ops);
static struct platform_driver spt_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "sunrisepoint-pinctrl",
.acpi_match_table = spt_pinctrl_acpi_match,
.pm = &spt_pinctrl_pm_ops,
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
},
};

32
drivers/pinctrl/intel/pinctrl-tangier.c
View File

@ -9,6 +9,7 @@
*/
#include <linux/bits.h>
#include <linux/cleanup.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/errno.h>
@ -220,7 +221,6 @@ static int tng_pinmux_set_mux(struct pinctrl_dev *pctldev,
const struct intel_pingroup *grp = &tp->groups[group];
u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT;
u32 mask = BUFCFG_PINMODE_MASK;
unsigned long flags;
unsigned int i;
/*
@ -232,11 +232,11 @@ static int tng_pinmux_set_mux(struct pinctrl_dev *pctldev,
return -EBUSY;
}
guard(raw_spinlock_irqsave)(&tp->lock);
/* Now enable the mux setting for each pin in the group */
raw_spin_lock_irqsave(&tp->lock, flags);
for (i = 0; i < grp->grp.npins; i++)
tng_update_bufcfg(tp, grp->grp.pins[i], bits, mask);
raw_spin_unlock_irqrestore(&tp->lock, flags);
return 0;
}
@ -248,14 +248,13 @@ static int tng_gpio_request_enable(struct pinctrl_dev *pctldev,
struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT;
u32 mask = BUFCFG_PINMODE_MASK;
unsigned long flags;
if (!tng_buf_available(tp, pin))
return -EBUSY;
raw_spin_lock_irqsave(&tp->lock, flags);
guard(raw_spinlock_irqsave)(&tp->lock);
tng_update_bufcfg(tp, pin, bits, mask);
raw_spin_unlock_irqrestore(&tp->lock, flags);
return 0;
}
@ -360,7 +359,6 @@ static int tng_config_set_pin(struct tng_pinctrl *tp, unsigned int pin,
unsigned int param = pinconf_to_config_param(config);
unsigned int arg = pinconf_to_config_argument(config);
u32 mask, term, value = 0;
unsigned long flags;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
@ -368,20 +366,20 @@ static int tng_config_set_pin(struct tng_pinctrl *tp, unsigned int pin,
break;
case PIN_CONFIG_BIAS_PULL_UP:
/* Set default strength value in case none is given */
if (arg == 1)
arg = 20000;
switch (arg) {
case 50000:
term = BUFCFG_PUPD_VAL_50K;
break;
case 1: /* Set default strength value in case none is given */
case 20000:
term = BUFCFG_PUPD_VAL_20K;
break;
case 2000:
term = BUFCFG_PUPD_VAL_2K;
break;
case 910:
term = BUFCFG_PUPD_VAL_910;
break;
default:
return -EINVAL;
}
@ -391,20 +389,20 @@ static int tng_config_set_pin(struct tng_pinctrl *tp, unsigned int pin,
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
/* Set default strength value in case none is given */
if (arg == 1)
arg = 20000;
switch (arg) {
case 50000:
term = BUFCFG_PUPD_VAL_50K;
break;
case 1: /* Set default strength value in case none is given */
case 20000:
term = BUFCFG_PUPD_VAL_20K;
break;
case 2000:
term = BUFCFG_PUPD_VAL_2K;
break;
case 910:
term = BUFCFG_PUPD_VAL_910;
break;
default:
return -EINVAL;
}
@ -432,9 +430,9 @@ static int tng_config_set_pin(struct tng_pinctrl *tp, unsigned int pin,
return -EINVAL;
}
raw_spin_lock_irqsave(&tp->lock, flags);
guard(raw_spinlock_irqsave)(&tp->lock);
tng_update_bufcfg(tp, pin, value, mask);
raw_spin_unlock_irqrestore(&tp->lock, flags);
return 0;
}

5
drivers/pinctrl/intel/pinctrl-tigerlake.c
View File

@ -10,6 +10,7 @@
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
@ -743,14 +744,12 @@ static const struct acpi_device_id tgl_pinctrl_acpi_match[] = {
};
MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match);
static INTEL_PINCTRL_PM_OPS(tgl_pinctrl_pm_ops);
static struct platform_driver tgl_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "tigerlake-pinctrl",
.acpi_match_table = tgl_pinctrl_acpi_match,
.pm = &tgl_pinctrl_pm_ops,
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
},
};
module_platform_driver(tgl_pinctrl_driver);