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Renesas ARM Based SoC DT Fixes for v3.14
Revert the addition of SSI clocks to DT for the r8a7790 (R-Car H2) and r8a7791 (R-Car M2) SoCs. Unfortunately these patches prevent booting the r8a7790-based Lager board and r8a7791-based Koelsch board to the point where a serial output is available. A solution to this problem is being sought but has not yet been finalised so in the mean time revert the changes. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJSy1+EAAoJENfPZGlqN0++jeQP/2iOdEyu6u7MW0Sz/4qy8Ak/ 7jPl1czO9zsaB2nKmWTyqDvXeBIUONkvNs01vKAcc0/62xQ1AhKllkoBXsWkM9DP gdQCsIj/FJYpLY3+H/Nndd+lMFv+HKHxh6QJp+R5EI4e8h2LOhYvW18pfRTnNOfK MDattpOgnu0PyK9mPLXGupxxMxlMku1+5XwCBrycule66Bm8vsG4IQK65jKnZA7w ND+8rd2k5ARM1hOxtRCHo6rJ4u1C6WSWSt2p8R9pvDQTPZPbX+FYz1GZ3YkvQxf7 pud4AuJHnhIccapaEHXP2/e8xryP13UDBj3PuLedbfiaoiji34QcHbwHyQQVhWrY rzezzAOFhbT3fhLbp3urcECPlXC0BuJgTzXcZrX8LjIPm9GGqSe9QyKTVCl3CJcp 9+nvtNUtzcC2RtGvt4fnYAxgIr+lETsR3EGyeC4lk4gVY5EnCmxUxn0Ku74qJr80 BweuVLlkCJ7L+5ul4NcQlXnOh3DKQMLp2X+xQBzoNUv9VheafUqs5e7glVOlbALZ 353LSp92Ru6sMTB8jcsQqTFWMeOMz0z4Zwi9TNzRpxn1g93CroM8p6dLdMpLFwuQ EApzBGutQuoLYepEz0U1J022xsJMJ8tuHxMfxU/vqpVmSGRD3aFdgywihv9hzvrq 8s+xeBLTFrJa90R7HZU9 =pTPp -----END PGP SIGNATURE----- Merge tag 'renesas-dt-fixes-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt From Simon Horman: Renesas ARM Based SoC DT Fixes for v3.14 Revert the addition of SSI clocks to DT for the r8a7790 (R-Car H2) and r8a7791 (R-Car M2) SoCs. Unfortunately these patches prevent booting the r8a7790-based Lager board and r8a7791-based Koelsch board to the point where a serial output is available. A solution to this problem is being sought but has not yet been finalised so in the mean time revert the changes. * tag 'renesas-dt-fixes-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: Revert "ARM: shmobile: r8a7791: Add SSI clocks in device tree" Revert "ARM: shmobile: r8a7790: Add SSI clocks in device tree" Signed-off-by: Olof Johansson <olof@lixom.net>
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commit
708d2aa14d
4 changed files with 0 additions and 66 deletions
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@ -626,25 +626,5 @@ R8A7790_CLK_I2C0
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clock-output-names =
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"rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";
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};
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mstp10_clks: mstp10_clks@e6150998 {
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compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
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clocks = <&p_clk>, <&mstp10_clks R8A7790_CLK_SSI>,
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<&mstp10_clks R8A7790_CLK_SSI>, <&mstp10_clks R8A7790_CLK_SSI>,
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<&mstp10_clks R8A7790_CLK_SSI>, <&mstp10_clks R8A7790_CLK_SSI>,
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<&mstp10_clks R8A7790_CLK_SSI>, <&mstp10_clks R8A7790_CLK_SSI>,
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<&mstp10_clks R8A7790_CLK_SSI>, <&mstp10_clks R8A7790_CLK_SSI>,
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<&mstp10_clks R8A7790_CLK_SSI>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7790_CLK_SSI R8A7790_CLK_SSI9 R8A7790_CLK_SSI8
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R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
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R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2
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R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
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>;
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clock-output-names =
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"ssi", "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
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"ssi4", "ssi3", "ssi2", "ssi1", "ssi0";
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};
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};
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};
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@ -495,26 +495,6 @@ R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
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"rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3",
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"i2c2", "i2c1", "i2c0";
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};
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mstp10_clks: mstp10_clks@e6150998 {
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compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
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clocks = <&p_clk>, <&mstp10_clks R8A7791_CLK_SSI>,
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<&mstp10_clks R8A7791_CLK_SSI>, <&mstp10_clks R8A7791_CLK_SSI>,
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<&mstp10_clks R8A7791_CLK_SSI>, <&mstp10_clks R8A7791_CLK_SSI>,
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<&mstp10_clks R8A7791_CLK_SSI>, <&mstp10_clks R8A7791_CLK_SSI>,
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<&mstp10_clks R8A7791_CLK_SSI>, <&mstp10_clks R8A7791_CLK_SSI>,
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<&mstp10_clks R8A7791_CLK_SSI>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7791_CLK_SSI R8A7791_CLK_SSI9 R8A7791_CLK_SSI8
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R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
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R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2
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R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
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>;
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clock-output-names =
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"ssi", "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
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"ssi4", "ssi3", "ssi2", "ssi1", "ssi0";
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};
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mstp11_clks: mstp11_clks@e615099c {
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compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
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@ -104,17 +104,4 @@
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#define R8A7790_CLK_I2C1 30
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#define R8A7790_CLK_I2C0 31
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/* MSTP10 */
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#define R8A7790_CLK_SSI 5
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#define R8A7790_CLK_SSI9 6
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#define R8A7790_CLK_SSI8 7
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#define R8A7790_CLK_SSI7 8
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#define R8A7790_CLK_SSI6 9
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#define R8A7790_CLK_SSI5 10
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#define R8A7790_CLK_SSI4 11
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#define R8A7790_CLK_SSI3 12
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#define R8A7790_CLK_SSI2 13
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#define R8A7790_CLK_SSI1 14
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#define R8A7790_CLK_SSI0 15
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#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
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@ -103,19 +103,6 @@
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#define R8A7791_CLK_I2C1 30
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#define R8A7791_CLK_I2C0 31
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/* MSTP10 */
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#define R8A7791_CLK_SSI 5
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#define R8A7791_CLK_SSI9 6
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#define R8A7791_CLK_SSI8 7
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#define R8A7791_CLK_SSI7 8
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#define R8A7791_CLK_SSI6 9
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#define R8A7791_CLK_SSI5 10
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#define R8A7791_CLK_SSI4 11
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#define R8A7791_CLK_SSI3 12
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#define R8A7791_CLK_SSI2 13
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#define R8A7791_CLK_SSI1 14
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#define R8A7791_CLK_SSI0 15
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/* MSTP11 */
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#define R8A7791_CLK_SCIFA3 6
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#define R8A7791_CLK_SCIFA4 7
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