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drm/amdgpu: drop soc15_set_ip_blocks()
No longer used since IP enumeration is now driven by amdgpu IP discovery code. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
0f3d2b6804
commit
7092432e3c
2 changed files with 0 additions and 180 deletions
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@ -780,185 +780,6 @@ void soc15_set_virt_ops(struct amdgpu_device *adev)
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soc15_reg_base_init(adev);
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}
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int soc15_set_ip_blocks(struct amdgpu_device *adev)
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{
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/* for bare metal case */
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if (!amdgpu_sriov_vf(adev))
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soc15_reg_base_init(adev);
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if (adev->flags & AMD_IS_APU) {
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adev->nbio.funcs = &nbio_v7_0_funcs;
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adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
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} else if (adev->asic_type == CHIP_VEGA20 ||
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adev->asic_type == CHIP_ARCTURUS ||
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adev->asic_type == CHIP_ALDEBARAN) {
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adev->nbio.funcs = &nbio_v7_4_funcs;
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adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
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} else {
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adev->nbio.funcs = &nbio_v6_1_funcs;
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adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
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}
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adev->hdp.funcs = &hdp_v4_0_funcs;
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if (adev->asic_type == CHIP_VEGA20 ||
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adev->asic_type == CHIP_ARCTURUS ||
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adev->asic_type == CHIP_ALDEBARAN)
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adev->df.funcs = &df_v3_6_funcs;
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else
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adev->df.funcs = &df_v1_7_funcs;
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if (adev->asic_type == CHIP_VEGA20 ||
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adev->asic_type == CHIP_ARCTURUS)
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adev->smuio.funcs = &smuio_v11_0_funcs;
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else if (adev->asic_type == CHIP_ALDEBARAN)
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adev->smuio.funcs = &smuio_v13_0_funcs;
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else
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adev->smuio.funcs = &smuio_v9_0_funcs;
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adev->rev_id = soc15_get_rev_id(adev);
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switch (adev->asic_type) {
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case CHIP_VEGA10:
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case CHIP_VEGA12:
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case CHIP_VEGA20:
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amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
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amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
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/* For Vega10 SR-IOV, PSP need to be initialized before IH */
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if (amdgpu_sriov_vf(adev)) {
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if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
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if (adev->asic_type == CHIP_VEGA20)
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amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
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else
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amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
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}
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if (adev->asic_type == CHIP_VEGA20)
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amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
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else
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amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
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} else {
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if (adev->asic_type == CHIP_VEGA20)
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amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
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else
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amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
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if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
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if (adev->asic_type == CHIP_VEGA20)
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amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
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else
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amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
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}
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}
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amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
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amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
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if (is_support_sw_smu(adev)) {
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if (!amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
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} else {
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amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
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}
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if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
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#if defined(CONFIG_DRM_AMD_DC)
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else if (amdgpu_device_has_dc_support(adev))
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amdgpu_device_ip_block_add(adev, &dm_ip_block);
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#endif
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if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
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amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
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amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
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}
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break;
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case CHIP_RAVEN:
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amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
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amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
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amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
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if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
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amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
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amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
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amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
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amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
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if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
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#if defined(CONFIG_DRM_AMD_DC)
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else if (amdgpu_device_has_dc_support(adev))
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amdgpu_device_ip_block_add(adev, &dm_ip_block);
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#endif
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amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
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break;
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case CHIP_ARCTURUS:
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amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
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amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
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if (amdgpu_sriov_vf(adev)) {
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if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
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amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
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amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
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} else {
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amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
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if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
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amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
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}
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if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
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amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
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amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
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amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
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if (amdgpu_sriov_vf(adev)) {
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if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
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amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
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} else {
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amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
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}
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if (!amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
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break;
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case CHIP_RENOIR:
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amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
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amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
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amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
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if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
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amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
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amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
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amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
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amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
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if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
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#if defined(CONFIG_DRM_AMD_DC)
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else if (amdgpu_device_has_dc_support(adev))
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amdgpu_device_ip_block_add(adev, &dm_ip_block);
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#endif
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amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
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amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
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break;
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case CHIP_ALDEBARAN:
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amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
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amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
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if (amdgpu_sriov_vf(adev)) {
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if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
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amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
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amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
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} else {
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amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
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if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
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amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
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}
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amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
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amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
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amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
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amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
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amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static bool soc15_need_full_reset(struct amdgpu_device *adev)
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{
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/* change this when we implement soft reset */
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@ -102,7 +102,6 @@ struct soc15_ras_field_entry {
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void soc15_grbm_select(struct amdgpu_device *adev,
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u32 me, u32 pipe, u32 queue, u32 vmid);
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void soc15_set_virt_ops(struct amdgpu_device *adev);
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int soc15_set_ip_blocks(struct amdgpu_device *adev);
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void soc15_program_register_sequence(struct amdgpu_device *adev,
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const struct soc15_reg_golden *registers,
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