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[ARM] 4498/1: ARMv7: Remove the L2 cache configuration via the aux ctrl register
The auxiliary control and the L2 auxiliary control registers are Cortex-A8 specific. They need to be removed from the generic ARMv7 support code. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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2 changed files with 0 additions and 16 deletions
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@ -612,12 +612,6 @@ config CPU_CACHE_ROUND_ROBIN
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Say Y here to use the predictable round-robin cache replacement
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policy. Unless you specifically require this or are unsure, say N.
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config CPU_L2CACHE_DISABLE
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bool "Disable level 2 cache"
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depends on CPU_V7
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help
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Say Y here to disable the level 2 cache. If unsure, say N.
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config CPU_BPREDICT_DISABLE
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bool "Disable branch prediction"
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depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
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@ -176,16 +176,6 @@ __v7_setup:
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mcr p15, 0, r4, c2, c0, 1 @ load TTB1
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mov r10, #0x1f @ domains 0, 1 = manager
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mcr p15, 0, r10, c3, c0, 0 @ load domain access register
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#ifndef CONFIG_CPU_L2CACHE_DISABLE
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@ L2 cache configuration in the L2 aux control register
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mrc p15, 1, r10, c9, c0, 2
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bic r10, r10, #(1 << 16) @ L2 outer cache
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mcr p15, 1, r10, c9, c0, 2
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@ L2 cache is enabled in the aux control register
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mrc p15, 0, r10, c1, c0, 1
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orr r10, r10, #2
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mcr p15, 0, r10, c1, c0, 1
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#endif
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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ldr r10, cr1_clear @ get mask for bits to clear
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bic r0, r0, r10 @ clear bits them
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