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synced 2024-08-23 09:19:51 +00:00
OMAP3: cpuidle: Add valid field into C-state parameter passing
Different boards benefit differently from the available seven C-states for cpu idle. In most cases, only few, properly spaced (in terms of consumption and latency) C-states are required to make the power management optimal. Hence we need a possibility to pass which C-states are actually used for each board. So added the valid field to cpuidle_params and added support to 3430sdp, which uses the paramenter passing. Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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bb4de3df69
commit
709731bb36
3 changed files with 31 additions and 21 deletions
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@ -61,19 +61,19 @@
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/* FIXME: These values need to be updated based on more profiling on 3430sdp*/
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/* FIXME: These values need to be updated based on more profiling on 3430sdp*/
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static struct cpuidle_params omap3_cpuidle_params_table[] = {
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static struct cpuidle_params omap3_cpuidle_params_table[] = {
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/* C1 */
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/* C1 */
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{2, 2, 5},
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{1, 2, 2, 5},
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/* C2 */
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/* C2 */
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{10, 10, 30},
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{1, 10, 10, 30},
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/* C3 */
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/* C3 */
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{50, 50, 300},
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{1, 50, 50, 300},
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/* C4 */
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/* C4 */
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{1500, 1800, 4000},
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{1, 1500, 1800, 4000},
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/* C5 */
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/* C5 */
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{2500, 7500, 12000},
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{1, 2500, 7500, 12000},
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/* C6 */
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/* C6 */
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{3000, 8500, 15000},
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{1, 3000, 8500, 15000},
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/* C7 */
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/* C7 */
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{10000, 30000, 300000},
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{1, 10000, 30000, 300000},
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};
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};
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static int board_keymap[] = {
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static int board_keymap[] = {
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@ -71,19 +71,19 @@ struct powerdomain *mpu_pd, *core_pd;
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*/
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*/
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static struct cpuidle_params cpuidle_params_table[] = {
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static struct cpuidle_params cpuidle_params_table[] = {
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/* C1 */
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/* C1 */
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{2, 2, 5},
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{1, 2, 2, 5},
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/* C2 */
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/* C2 */
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{10, 10, 30},
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{1, 10, 10, 30},
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/* C3 */
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/* C3 */
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{50, 50, 300},
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{1, 50, 50, 300},
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/* C4 */
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/* C4 */
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{1500, 1800, 4000},
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{1, 1500, 1800, 4000},
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/* C5 */
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/* C5 */
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{2500, 7500, 12000},
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{1, 2500, 7500, 12000},
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/* C6 */
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/* C6 */
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{3000, 8500, 15000},
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{1, 3000, 8500, 15000},
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/* C7 */
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/* C7 */
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{10000, 30000, 300000},
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{1, 10000, 30000, 300000},
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};
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};
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static int omap3_idle_bm_check(void)
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static int omap3_idle_bm_check(void)
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@ -277,6 +277,8 @@ void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
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return;
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return;
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for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
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for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
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cpuidle_params_table[i].valid =
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cpuidle_board_params[i].valid;
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cpuidle_params_table[i].sleep_latency =
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cpuidle_params_table[i].sleep_latency =
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cpuidle_board_params[i].sleep_latency;
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cpuidle_board_params[i].sleep_latency;
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cpuidle_params_table[i].wake_latency =
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cpuidle_params_table[i].wake_latency =
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@ -301,7 +303,8 @@ void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
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void omap_init_power_states(void)
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void omap_init_power_states(void)
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{
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{
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/* C1 . MPU WFI + Core active */
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/* C1 . MPU WFI + Core active */
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omap3_power_states[OMAP3_STATE_C1].valid = 1;
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omap3_power_states[OMAP3_STATE_C1].valid =
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cpuidle_params_table[OMAP3_STATE_C1].valid;
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omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
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omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
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omap3_power_states[OMAP3_STATE_C1].sleep_latency =
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omap3_power_states[OMAP3_STATE_C1].sleep_latency =
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cpuidle_params_table[OMAP3_STATE_C1].sleep_latency;
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cpuidle_params_table[OMAP3_STATE_C1].sleep_latency;
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@ -314,7 +317,8 @@ void omap_init_power_states(void)
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omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
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omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
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/* C2 . MPU WFI + Core inactive */
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/* C2 . MPU WFI + Core inactive */
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omap3_power_states[OMAP3_STATE_C2].valid = 1;
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omap3_power_states[OMAP3_STATE_C2].valid =
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cpuidle_params_table[OMAP3_STATE_C2].valid;
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omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
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omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
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omap3_power_states[OMAP3_STATE_C2].sleep_latency =
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omap3_power_states[OMAP3_STATE_C2].sleep_latency =
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cpuidle_params_table[OMAP3_STATE_C2].sleep_latency;
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cpuidle_params_table[OMAP3_STATE_C2].sleep_latency;
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@ -327,7 +331,8 @@ void omap_init_power_states(void)
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omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;
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omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;
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/* C3 . MPU CSWR + Core inactive */
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/* C3 . MPU CSWR + Core inactive */
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omap3_power_states[OMAP3_STATE_C3].valid = 1;
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omap3_power_states[OMAP3_STATE_C3].valid =
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cpuidle_params_table[OMAP3_STATE_C3].valid;
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omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
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omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
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omap3_power_states[OMAP3_STATE_C3].sleep_latency =
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omap3_power_states[OMAP3_STATE_C3].sleep_latency =
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cpuidle_params_table[OMAP3_STATE_C3].sleep_latency;
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cpuidle_params_table[OMAP3_STATE_C3].sleep_latency;
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@ -341,7 +346,8 @@ void omap_init_power_states(void)
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CPUIDLE_FLAG_CHECK_BM;
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CPUIDLE_FLAG_CHECK_BM;
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/* C4 . MPU OFF + Core inactive */
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/* C4 . MPU OFF + Core inactive */
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omap3_power_states[OMAP3_STATE_C4].valid = 1;
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omap3_power_states[OMAP3_STATE_C4].valid =
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cpuidle_params_table[OMAP3_STATE_C4].valid;
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omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
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omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
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omap3_power_states[OMAP3_STATE_C4].sleep_latency =
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omap3_power_states[OMAP3_STATE_C4].sleep_latency =
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cpuidle_params_table[OMAP3_STATE_C4].sleep_latency;
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cpuidle_params_table[OMAP3_STATE_C4].sleep_latency;
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@ -355,7 +361,8 @@ void omap_init_power_states(void)
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CPUIDLE_FLAG_CHECK_BM;
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CPUIDLE_FLAG_CHECK_BM;
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/* C5 . MPU CSWR + Core CSWR*/
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/* C5 . MPU CSWR + Core CSWR*/
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omap3_power_states[OMAP3_STATE_C5].valid = 1;
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omap3_power_states[OMAP3_STATE_C5].valid =
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cpuidle_params_table[OMAP3_STATE_C5].valid;
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omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
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omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
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omap3_power_states[OMAP3_STATE_C5].sleep_latency =
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omap3_power_states[OMAP3_STATE_C5].sleep_latency =
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cpuidle_params_table[OMAP3_STATE_C5].sleep_latency;
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cpuidle_params_table[OMAP3_STATE_C5].sleep_latency;
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@ -369,7 +376,8 @@ void omap_init_power_states(void)
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CPUIDLE_FLAG_CHECK_BM;
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CPUIDLE_FLAG_CHECK_BM;
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/* C6 . MPU OFF + Core CSWR */
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/* C6 . MPU OFF + Core CSWR */
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omap3_power_states[OMAP3_STATE_C6].valid = 1;
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omap3_power_states[OMAP3_STATE_C6].valid =
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cpuidle_params_table[OMAP3_STATE_C6].valid;
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omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
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omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
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omap3_power_states[OMAP3_STATE_C6].sleep_latency =
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omap3_power_states[OMAP3_STATE_C6].sleep_latency =
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cpuidle_params_table[OMAP3_STATE_C6].sleep_latency;
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cpuidle_params_table[OMAP3_STATE_C6].sleep_latency;
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@ -383,7 +391,8 @@ void omap_init_power_states(void)
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CPUIDLE_FLAG_CHECK_BM;
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CPUIDLE_FLAG_CHECK_BM;
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/* C7 . MPU OFF + Core OFF */
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/* C7 . MPU OFF + Core OFF */
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omap3_power_states[OMAP3_STATE_C7].valid = 1;
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omap3_power_states[OMAP3_STATE_C7].valid =
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cpuidle_params_table[OMAP3_STATE_C7].valid;
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omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7;
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omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7;
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omap3_power_states[OMAP3_STATE_C7].sleep_latency =
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omap3_power_states[OMAP3_STATE_C7].sleep_latency =
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cpuidle_params_table[OMAP3_STATE_C7].sleep_latency;
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cpuidle_params_table[OMAP3_STATE_C7].sleep_latency;
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@ -24,6 +24,7 @@ extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
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extern int omap3_idle_init(void);
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extern int omap3_idle_init(void);
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struct cpuidle_params {
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struct cpuidle_params {
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u8 valid;
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u32 sleep_latency;
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u32 sleep_latency;
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u32 wake_latency;
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u32 wake_latency;
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u32 threshold;
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u32 threshold;
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