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pinctrl: rockchip: convert to raw spinlock
This lock is used from rockchip_irq_set_type() which is part of the irq_chip implementation and thus must use raw_spinlock_t as documented in Documentation/gpio/driver.txt. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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parent
f07bedc37f
commit
70b7aa7a87
1 changed files with 13 additions and 13 deletions
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@ -163,7 +163,7 @@ struct rockchip_pin_bank {
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struct irq_domain *domain;
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struct gpio_chip gpio_chip;
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struct pinctrl_gpio_range grange;
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spinlock_t slock;
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raw_spinlock_t slock;
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u32 toggle_edge_mode;
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};
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@ -1498,7 +1498,7 @@ static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
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return ret;
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clk_enable(bank->clk);
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spin_lock_irqsave(&bank->slock, flags);
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raw_spin_lock_irqsave(&bank->slock, flags);
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data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
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/* set bit to 1 for output, 0 for input */
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@ -1508,7 +1508,7 @@ static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
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data &= ~BIT(pin);
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writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
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spin_unlock_irqrestore(&bank->slock, flags);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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clk_disable(bank->clk);
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return 0;
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@ -1958,7 +1958,7 @@ static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
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u32 data;
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clk_enable(bank->clk);
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spin_lock_irqsave(&bank->slock, flags);
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raw_spin_lock_irqsave(&bank->slock, flags);
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data = readl(reg);
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data &= ~BIT(offset);
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@ -1966,7 +1966,7 @@ static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
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data |= BIT(offset);
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writel(data, reg);
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spin_unlock_irqrestore(&bank->slock, flags);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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clk_disable(bank->clk);
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}
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@ -2078,7 +2078,7 @@ static void rockchip_irq_demux(struct irq_desc *desc)
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data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
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do {
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spin_lock_irqsave(&bank->slock, flags);
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raw_spin_lock_irqsave(&bank->slock, flags);
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polarity = readl_relaxed(bank->reg_base +
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GPIO_INT_POLARITY);
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@ -2089,7 +2089,7 @@ static void rockchip_irq_demux(struct irq_desc *desc)
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writel(polarity,
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bank->reg_base + GPIO_INT_POLARITY);
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spin_unlock_irqrestore(&bank->slock, flags);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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data_old = data;
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data = readl_relaxed(bank->reg_base +
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@ -2120,20 +2120,20 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
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return ret;
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clk_enable(bank->clk);
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spin_lock_irqsave(&bank->slock, flags);
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raw_spin_lock_irqsave(&bank->slock, flags);
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data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
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data &= ~mask;
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writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
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spin_unlock_irqrestore(&bank->slock, flags);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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if (type & IRQ_TYPE_EDGE_BOTH)
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irq_set_handler_locked(d, handle_edge_irq);
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else
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irq_set_handler_locked(d, handle_level_irq);
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spin_lock_irqsave(&bank->slock, flags);
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raw_spin_lock_irqsave(&bank->slock, flags);
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irq_gc_lock(gc);
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level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
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@ -2176,7 +2176,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
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break;
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default:
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irq_gc_unlock(gc);
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spin_unlock_irqrestore(&bank->slock, flags);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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clk_disable(bank->clk);
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return -EINVAL;
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}
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@ -2185,7 +2185,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
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writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
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irq_gc_unlock(gc);
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spin_unlock_irqrestore(&bank->slock, flags);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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clk_disable(bank->clk);
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return 0;
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@ -2468,7 +2468,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
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for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
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int bank_pins = 0;
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spin_lock_init(&bank->slock);
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raw_spin_lock_init(&bank->slock);
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bank->drvdata = d;
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bank->pin_base = ctrl->nr_pins;
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ctrl->nr_pins += bank->nr_pins;
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