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arm: Xilinx Zynq dt patches for v3.16
- Cleanup GIC mode - Cleanup node names - Add regulators -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iEYEABECAAYFAlN7YLEACgkQykllyylKDCHD9wCfTb/wGtIAB/Gc4Kj/vp4wMPR5 ChAAnRn07YxdT5Si5uq0WRbnSFXL3JfN =WXYP -----END PGP SIGNATURE----- Merge tag 'zynq-dt-for-3.16' of git://git.xilinx.com/linux-xlnx into next/dt Merge "arm: Xilinx Zynq dt patches for v3.16" from Michal Simek: - Cleanup GIC mode - Cleanup node names - Add regulators * tag 'zynq-dt-for-3.16' of git://git.xilinx.com/linux-xlnx: ARM: zynq: dt: Add a fixed regulator for CPU voltage ARM: zynq: dt: Clean up device tree ARM: dts: zynq: drop address cells from GIC node Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
70bc6bb3f2
1 changed files with 25 additions and 15 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2011 Xilinx
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* Copyright (C) 2011 - 2014 Xilinx
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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@ -25,6 +25,7 @@ cpu@0 {
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reg = <0>;
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clocks = <&clkc 3>;
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clock-latency = <1000>;
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cpu0-supply = <®ulator_vccpint>;
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operating-points = <
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/* kHz uV */
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666667 1000000
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@ -48,6 +49,15 @@ pmu {
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reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
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};
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regulator_vccpint: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "VCCPINT";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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@ -55,7 +65,7 @@ amba {
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interrupt-parent = <&intc>;
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ranges;
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i2c0: zynq-i2c@e0004000 {
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i2c0: i2c@e0004000 {
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compatible = "cdns,i2c-r1p10";
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status = "disabled";
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clocks = <&clkc 38>;
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@ -66,7 +76,7 @@ i2c0: zynq-i2c@e0004000 {
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#size-cells = <0>;
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};
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i2c1: zynq-i2c@e0005000 {
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i2c1: i2c@e0005000 {
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compatible = "cdns,i2c-r1p10";
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status = "disabled";
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clocks = <&clkc 39>;
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@ -80,7 +90,6 @@ i2c1: zynq-i2c@e0005000 {
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intc: interrupt-controller@f8f01000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0xF8F01000 0x1000>,
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<0xF8F00100 0x100>;
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@ -95,7 +104,7 @@ L2: cache-controller {
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cache-level = <2>;
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};
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uart0: uart@e0000000 {
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uart0: serial@e0000000 {
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compatible = "xlnx,xuartps";
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status = "disabled";
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clocks = <&clkc 23>, <&clkc 40>;
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@ -104,7 +113,7 @@ uart0: uart@e0000000 {
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interrupts = <0 27 4>;
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};
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uart1: uart@e0001000 {
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uart1: serial@e0001000 {
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compatible = "xlnx,xuartps";
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status = "disabled";
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clocks = <&clkc 24>, <&clkc 41>;
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@ -131,7 +140,7 @@ gem1: ethernet@e000c000 {
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clock-names = "pclk", "hclk", "tx_clk";
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};
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sdhci0: ps7-sdhci@e0100000 {
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sdhci0: sdhci@e0100000 {
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compatible = "arasan,sdhci-8.9a";
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status = "disabled";
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clock-names = "clk_xin", "clk_ahb";
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@ -141,7 +150,7 @@ sdhci0: ps7-sdhci@e0100000 {
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reg = <0xe0100000 0x1000>;
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} ;
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sdhci1: ps7-sdhci@e0101000 {
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sdhci1: sdhci@e0101000 {
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compatible = "arasan,sdhci-8.9a";
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status = "disabled";
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clock-names = "clk_xin", "clk_ahb";
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@ -185,26 +194,27 @@ global_timer: timer@f8f00200 {
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clocks = <&clkc 4>;
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};
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ttc0: ttc0@f8001000 {
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ttc0: timer@f8001000 {
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interrupt-parent = <&intc>;
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interrupts = < 0 10 4 0 11 4 0 12 4 >;
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interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
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compatible = "cdns,ttc";
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clocks = <&clkc 6>;
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reg = <0xF8001000 0x1000>;
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};
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ttc1: ttc1@f8002000 {
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ttc1: timer@f8002000 {
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interrupt-parent = <&intc>;
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interrupts = < 0 37 4 0 38 4 0 39 4 >;
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interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
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compatible = "cdns,ttc";
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clocks = <&clkc 6>;
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reg = <0xF8002000 0x1000>;
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};
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scutimer: scutimer@f8f00600 {
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scutimer: timer@f8f00600 {
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interrupt-parent = <&intc>;
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interrupts = < 1 13 0x301 >;
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interrupts = <1 13 0x301>;
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compatible = "arm,cortex-a9-twd-timer";
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reg = < 0xf8f00600 0x20 >;
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reg = <0xf8f00600 0x20>;
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clocks = <&clkc 4>;
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} ;
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};
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