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PCI/MSI: Use msi_add_msi_desc()
Simplify the allocation of MSI descriptors by using msi_add_msi_desc() which moves the storage handling to core code and prepares for dynamic extension of the MSI-X vector space. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Michael Kelley <mikelley@microsoft.com> Tested-by: Nishanth Menon <nm@ti.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20211206210748.035348646@linutronix.de
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parent
5512c5eaf5
commit
71020a3c0d
1 changed files with 50 additions and 60 deletions
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@ -376,40 +376,41 @@ static int pci_setup_msi_context(struct pci_dev *dev)
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return ret;
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}
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static struct msi_desc *
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msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity_desc *masks)
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static int msi_setup_msi_desc(struct pci_dev *dev, int nvec,
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struct irq_affinity_desc *masks)
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{
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struct msi_desc *entry;
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struct msi_desc desc;
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u16 control;
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/* MSI Entry Initialization */
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entry = alloc_msi_entry(&dev->dev, nvec, masks);
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if (!entry)
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return NULL;
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memset(&desc, 0, sizeof(desc));
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pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
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/* Lies, damned lies, and MSIs */
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if (dev->dev_flags & PCI_DEV_FLAGS_HAS_MSI_MASKING)
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control |= PCI_MSI_FLAGS_MASKBIT;
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/* Respect XEN's mask disabling */
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if (pci_msi_ignore_mask)
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control &= ~PCI_MSI_FLAGS_MASKBIT;
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entry->pci.msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
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entry->pci.msi_attrib.can_mask = !pci_msi_ignore_mask &&
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!!(control & PCI_MSI_FLAGS_MASKBIT);
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entry->pci.msi_attrib.default_irq = dev->irq;
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entry->pci.msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
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entry->pci.msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
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desc.nvec_used = nvec;
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desc.pci.msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
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desc.pci.msi_attrib.can_mask = !!(control & PCI_MSI_FLAGS_MASKBIT);
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desc.pci.msi_attrib.default_irq = dev->irq;
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desc.pci.msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
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desc.pci.msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
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desc.affinity = masks;
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if (control & PCI_MSI_FLAGS_64BIT)
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entry->pci.mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
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desc.pci.mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
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else
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entry->pci.mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
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desc.pci.mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
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/* Save the initial mask status */
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if (entry->pci.msi_attrib.can_mask)
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pci_read_config_dword(dev, entry->pci.mask_pos, &entry->pci.msi_mask);
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if (desc.pci.msi_attrib.can_mask)
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pci_read_config_dword(dev, desc.pci.mask_pos, &desc.pci.msi_mask);
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return entry;
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return msi_add_msi_desc(&dev->dev, &desc);
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}
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static int msi_verify_entries(struct pci_dev *dev)
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@ -459,17 +460,14 @@ static int msi_capability_init(struct pci_dev *dev, int nvec,
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masks = irq_create_affinity_masks(nvec, affd);
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msi_lock_descs(&dev->dev);
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entry = msi_setup_entry(dev, nvec, masks);
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if (!entry) {
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ret = -ENOMEM;
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ret = msi_setup_msi_desc(dev, nvec, masks);
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if (ret)
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goto fail;
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}
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/* All MSIs are unmasked by default; mask them all */
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entry = first_pci_msi_entry(dev);
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pci_msi_mask(entry, msi_multi_mask(entry));
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list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
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/* Configure MSI capability structure */
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ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
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if (ret)
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@ -519,48 +517,40 @@ static void __iomem *msix_map_region(struct pci_dev *dev,
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return ioremap(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
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}
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static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
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struct msix_entry *entries, int nvec,
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struct irq_affinity_desc *masks)
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static int msix_setup_msi_descs(struct pci_dev *dev, void __iomem *base,
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struct msix_entry *entries, int nvec,
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struct irq_affinity_desc *masks)
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{
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int i, vec_count = pci_msix_vec_count(dev);
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int ret = 0, i, vec_count = pci_msix_vec_count(dev);
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struct irq_affinity_desc *curmsk;
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struct msi_desc *entry;
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struct msi_desc desc;
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void __iomem *addr;
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for (i = 0, curmsk = masks; i < nvec; i++) {
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entry = alloc_msi_entry(&dev->dev, 1, curmsk);
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if (!entry) {
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/* No enough memory. Don't try again */
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return -ENOMEM;
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memset(&desc, 0, sizeof(desc));
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desc.nvec_used = 1;
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desc.pci.msi_attrib.is_msix = 1;
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desc.pci.msi_attrib.is_64 = 1;
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desc.pci.msi_attrib.default_irq = dev->irq;
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desc.pci.mask_base = base;
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for (i = 0, curmsk = masks; i < nvec; i++, curmsk++) {
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desc.msi_index = entries ? entries[i].entry : i;
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desc.affinity = masks ? curmsk : NULL;
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desc.pci.msi_attrib.is_virtual = desc.msi_index >= vec_count;
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desc.pci.msi_attrib.can_mask = !pci_msi_ignore_mask &&
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!desc.pci.msi_attrib.is_virtual;
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if (!desc.pci.msi_attrib.can_mask) {
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addr = pci_msix_desc_addr(&desc);
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desc.pci.msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
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}
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entry->pci.msi_attrib.is_msix = 1;
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entry->pci.msi_attrib.is_64 = 1;
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if (entries)
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entry->msi_index = entries[i].entry;
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else
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entry->msi_index = i;
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entry->pci.msi_attrib.is_virtual = entry->msi_index >= vec_count;
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entry->pci.msi_attrib.can_mask = !pci_msi_ignore_mask &&
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!entry->pci.msi_attrib.is_virtual;
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entry->pci.msi_attrib.default_irq = dev->irq;
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entry->pci.mask_base = base;
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if (entry->pci.msi_attrib.can_mask) {
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addr = pci_msix_desc_addr(entry);
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entry->pci.msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
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}
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list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
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if (masks)
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curmsk++;
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ret = msi_add_msi_desc(&dev->dev, &desc);
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if (ret)
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break;
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}
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return 0;
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return ret;
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}
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static void msix_update_entries(struct pci_dev *dev, struct msix_entry *entries)
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@ -598,7 +588,7 @@ static int msix_setup_interrupts(struct pci_dev *dev, void __iomem *base,
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masks = irq_create_affinity_masks(nvec, affd);
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msi_lock_descs(&dev->dev);
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ret = msix_setup_entries(dev, base, entries, nvec, masks);
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ret = msix_setup_msi_descs(dev, base, entries, nvec, masks);
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if (ret)
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goto out_free;
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