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drm/radeon/audio: write audio/video latency info for DCE4/5
Needed by the hda driver to properly set up synchronization on the audio side. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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2 changed files with 75 additions and 0 deletions
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@ -58,6 +58,42 @@ static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t cloc
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WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
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}
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static void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
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struct drm_display_mode *mode)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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struct drm_connector *connector;
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struct radeon_connector *radeon_connector = NULL;
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u32 tmp = 0;
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list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
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if (connector->encoder == encoder) {
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radeon_connector = to_radeon_connector(connector);
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break;
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}
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}
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if (!radeon_connector) {
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DRM_ERROR("Couldn't find encoder's connector\n");
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return;
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}
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if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
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if (connector->latency_present[1])
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tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
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AUDIO_LIPSYNC(connector->audio_latency[1]);
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else
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tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
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} else {
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if (connector->latency_present[0])
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tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
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AUDIO_LIPSYNC(connector->audio_latency[0]);
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else
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tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
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}
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WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
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}
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static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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@ -327,6 +363,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
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dce6_afmt_write_sad_regs(encoder);
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} else {
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evergreen_hdmi_write_sad_regs(encoder);
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dce4_afmt_write_latency_fields(encoder, mode);
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}
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err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
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@ -750,6 +750,44 @@
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* bit6 = 192 kHz
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*/
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#define AZ_CHANNEL_COUNT_CONTROL 0x5fe4
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# define HBR_CHANNEL_COUNT(x) (((x) & 0x7) << 0)
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# define COMPRESSED_CHANNEL_COUNT(x) (((x) & 0x7) << 4)
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/* HBR_CHANNEL_COUNT, COMPRESSED_CHANNEL_COUNT
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* 0 = use stream header
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* 1-7 = channel count - 1
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*/
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#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC 0x5fe8
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# define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0)
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# define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8)
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/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
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* 0 = invalid
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* x = legal delay value
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* 255 = sync not supported
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*/
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#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR 0x5fec
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# define HBR_CAPABLE (1 << 0) /* enabled by default */
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#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0 0x5ff4
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# define DISPLAY0_TYPE(x) (((x) & 0x3) << 0)
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# define DISPLAY_TYPE_NONE 0
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# define DISPLAY_TYPE_HDMI 1
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# define DISPLAY_TYPE_DP 2
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# define DISPLAY0_ID(x) (((x) & 0x3f) << 2)
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# define DISPLAY1_TYPE(x) (((x) & 0x3) << 8)
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# define DISPLAY1_ID(x) (((x) & 0x3f) << 10)
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# define DISPLAY2_TYPE(x) (((x) & 0x3) << 16)
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# define DISPLAY2_ID(x) (((x) & 0x3f) << 18)
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# define DISPLAY3_TYPE(x) (((x) & 0x3) << 24)
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# define DISPLAY3_ID(x) (((x) & 0x3f) << 26)
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#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1 0x5ff8
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# define DISPLAY4_TYPE(x) (((x) & 0x3) << 0)
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# define DISPLAY4_ID(x) (((x) & 0x3f) << 2)
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# define DISPLAY5_TYPE(x) (((x) & 0x3) << 8)
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# define DISPLAY5_ID(x) (((x) & 0x3f) << 10)
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#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_NUMBER 0x5ffc
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# define NUMBER_OF_DISPLAY_ID(x) (((x) & 0x7) << 0)
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#define AZ_HOT_PLUG_CONTROL 0x5e78
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# define AZ_FORCE_CODEC_WAKE (1 << 0)
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# define PIN0_JACK_DETECTION_ENABLE (1 << 4)
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