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clk: tegra: Fix Tegra210 PLLU initialization
- Added necessary delays in PLLU enable sequence during initialization - Applied PLLU lock to all secondary gates (PLLU_48M and PLLU_60M were missing). Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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71422dbb89
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1 changed files with 4 additions and 2 deletions
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@ -2554,6 +2554,7 @@ static int tegra210_enable_pllu(void)
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reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);
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reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);
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reg &= ~BIT(pllu.params->iddq_bit_idx);
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reg &= ~BIT(pllu.params->iddq_bit_idx);
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writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);
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writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);
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udelay(5);
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reg = readl_relaxed(clk_base + PLLU_BASE);
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reg = readl_relaxed(clk_base + PLLU_BASE);
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reg &= ~GENMASK(20, 0);
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reg &= ~GENMASK(20, 0);
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@ -2561,6 +2562,7 @@ static int tegra210_enable_pllu(void)
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reg |= fentry->n << 8;
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reg |= fentry->n << 8;
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reg |= fentry->p << 16;
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reg |= fentry->p << 16;
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writel(reg, clk_base + PLLU_BASE);
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writel(reg, clk_base + PLLU_BASE);
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udelay(1);
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reg |= PLL_ENABLE;
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reg |= PLL_ENABLE;
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writel(reg, clk_base + PLLU_BASE);
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writel(reg, clk_base + PLLU_BASE);
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@ -2800,14 +2802,14 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
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/* PLLU_60M */
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/* PLLU_60M */
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clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2",
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clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2",
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CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
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CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
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23, 0, NULL);
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23, 0, &pll_u_lock);
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clk_register_clkdev(clk, "pll_u_60M", NULL);
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clk_register_clkdev(clk, "pll_u_60M", NULL);
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clks[TEGRA210_CLK_PLL_U_60M] = clk;
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clks[TEGRA210_CLK_PLL_U_60M] = clk;
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/* PLLU_48M */
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/* PLLU_48M */
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clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1",
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clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1",
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CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
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CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
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25, 0, NULL);
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25, 0, &pll_u_lock);
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clk_register_clkdev(clk, "pll_u_48M", NULL);
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clk_register_clkdev(clk, "pll_u_48M", NULL);
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clks[TEGRA210_CLK_PLL_U_48M] = clk;
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clks[TEGRA210_CLK_PLL_U_48M] = clk;
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