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sfc: support VI strides other than 8k
Medford2 can also have 16k or 64k VI stride. This is reported by MCDI in GET_CAPABILITIES, which fortunately is called before the driver does anything sensitive to the VI stride (such as accessing or even allocating VIs past the zeroth). Signed-off-by: Edward Cree <ecree@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
03714bbb22
commit
7182744301
5 changed files with 70 additions and 27 deletions
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@ -233,7 +233,7 @@ static int efx_ef10_get_vf_index(struct efx_nic *efx)
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static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
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{
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MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V2_OUT_LEN);
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MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V3_OUT_LEN);
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struct efx_ef10_nic_data *nic_data = efx->nic_data;
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size_t outlen;
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int rc;
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@ -277,6 +277,35 @@ static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
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return -ENODEV;
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}
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if (outlen >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
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u8 vi_window_mode = MCDI_BYTE(outbuf,
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GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
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switch (vi_window_mode) {
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case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
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efx->vi_stride = 8192;
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break;
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case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
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efx->vi_stride = 16384;
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break;
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case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
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efx->vi_stride = 65536;
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break;
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default:
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netif_err(efx, probe, efx->net_dev,
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"Unrecognised VI window mode %d\n",
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vi_window_mode);
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return -EIO;
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}
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netif_dbg(efx, probe, efx->net_dev, "vi_stride = %u\n",
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efx->vi_stride);
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} else {
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/* keep default VI stride */
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netif_dbg(efx, probe, efx->net_dev,
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"firmware did not report VI window mode, assuming vi_stride = %u\n",
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efx->vi_stride);
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}
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return 0;
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}
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@ -609,17 +638,6 @@ static int efx_ef10_probe(struct efx_nic *efx)
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struct efx_ef10_nic_data *nic_data;
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int i, rc;
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/* We can have one VI for each 8K region. However, until we
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* use TX option descriptors we need two TX queues per channel.
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*/
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efx->max_channels = min_t(unsigned int,
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EFX_MAX_CHANNELS,
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efx_ef10_mem_map_size(efx) /
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(EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
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efx->max_tx_channels = efx->max_channels;
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if (WARN_ON(efx->max_channels == 0))
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return -EIO;
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nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
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if (!nic_data)
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return -ENOMEM;
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@ -691,6 +709,20 @@ static int efx_ef10_probe(struct efx_nic *efx)
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if (rc < 0)
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goto fail5;
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/* We can have one VI for each vi_stride-byte region.
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* However, until we use TX option descriptors we need two TX queues
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* per channel.
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*/
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efx->max_channels = min_t(unsigned int,
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EFX_MAX_CHANNELS,
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efx_ef10_mem_map_size(efx) /
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(efx->vi_stride * EFX_TXQ_TYPES));
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efx->max_tx_channels = efx->max_channels;
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if (WARN_ON(efx->max_channels == 0)) {
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rc = -EIO;
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goto fail5;
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}
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efx->rx_packet_len_offset =
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ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
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@ -927,7 +959,7 @@ static int efx_ef10_link_piobufs(struct efx_nic *efx)
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} else {
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tx_queue->piobuf =
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nic_data->pio_write_base +
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index * EFX_VI_PAGE_SIZE + offset;
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index * efx->vi_stride + offset;
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tx_queue->piobuf_offset = offset;
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netif_dbg(efx, probe, efx->net_dev,
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"linked VI %u to PIO buffer %u offset %x addr %p\n",
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@ -1273,19 +1305,19 @@ static int efx_ef10_dimension_resources(struct efx_nic *efx)
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* for writing PIO buffers through.
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*
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* The UC mapping contains (channel_vis - 1) complete VIs and the
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* first half of the next VI. Then the WC mapping begins with
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* the second half of this last VI.
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* first 4K of the next VI. Then the WC mapping begins with
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* the remainder of this last VI.
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*/
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uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
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uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * efx->vi_stride +
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ER_DZ_TX_PIOBUF);
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if (nic_data->n_piobufs) {
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/* pio_write_vi_base rounds down to give the number of complete
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* VIs inside the UC mapping.
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*/
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pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
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pio_write_vi_base = uc_mem_map_size / efx->vi_stride;
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wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
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nic_data->n_piobufs) *
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EFX_VI_PAGE_SIZE) -
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efx->vi_stride) -
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uc_mem_map_size);
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max_vis = pio_write_vi_base + nic_data->n_piobufs;
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} else {
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@ -1357,7 +1389,7 @@ static int efx_ef10_dimension_resources(struct efx_nic *efx)
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nic_data->pio_write_vi_base = pio_write_vi_base;
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nic_data->pio_write_base =
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nic_data->wc_membase +
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(pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
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(pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF -
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uc_mem_map_size);
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rc = efx_ef10_link_piobufs(efx);
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@ -27,6 +27,7 @@
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#include <net/udp_tunnel.h>
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#include "efx.h"
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#include "nic.h"
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#include "io.h"
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#include "selftest.h"
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#include "sriov.h"
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@ -2977,6 +2978,7 @@ static int efx_init_struct(struct efx_nic *efx,
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efx->rx_packet_ts_offset =
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efx->type->rx_ts_offset - efx->type->rx_prefix_size;
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spin_lock_init(&efx->stats_lock);
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efx->vi_stride = EFX_DEFAULT_VI_STRIDE;
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mutex_init(&efx->mac_lock);
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efx->phy_op = &efx_dummy_phy_operations;
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efx->mdio.dev = net_dev;
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@ -222,18 +222,21 @@ static inline void efx_reado_table(struct efx_nic *efx, efx_oword_t *value,
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efx_reado(efx, value, reg + index * sizeof(efx_oword_t));
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}
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/* Page size used as step between per-VI registers */
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#define EFX_VI_PAGE_SIZE 0x2000
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/* default VI stride (step between per-VI registers) is 8K */
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#define EFX_DEFAULT_VI_STRIDE 0x2000
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/* Calculate offset to page-mapped register */
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#define EFX_PAGED_REG(page, reg) \
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((page) * EFX_VI_PAGE_SIZE + (reg))
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static inline unsigned int efx_paged_reg(struct efx_nic *efx, unsigned int page,
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unsigned int reg)
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{
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return page * efx->vi_stride + reg;
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}
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/* Write the whole of RX_DESC_UPD or TX_DESC_UPD */
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static inline void _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value,
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unsigned int reg, unsigned int page)
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{
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reg = EFX_PAGED_REG(page, reg);
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reg = efx_paged_reg(efx, page, reg);
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netif_vdbg(efx, hw, efx->net_dev,
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"writing register %x with " EFX_OWORD_FMT "\n", reg,
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@ -262,7 +265,7 @@ static inline void
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_efx_writed_page(struct efx_nic *efx, const efx_dword_t *value,
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unsigned int reg, unsigned int page)
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{
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efx_writed(efx, value, EFX_PAGED_REG(page, reg));
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efx_writed(efx, value, efx_paged_reg(efx, page, reg));
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}
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#define efx_writed_page(efx, value, reg, page) \
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_efx_writed_page(efx, value, \
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@ -288,10 +291,10 @@ static inline void _efx_writed_page_locked(struct efx_nic *efx,
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if (page == 0) {
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spin_lock_irqsave(&efx->biu_lock, flags);
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efx_writed(efx, value, EFX_PAGED_REG(page, reg));
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efx_writed(efx, value, efx_paged_reg(efx, page, reg));
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spin_unlock_irqrestore(&efx->biu_lock, flags);
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} else {
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efx_writed(efx, value, EFX_PAGED_REG(page, reg));
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efx_writed(efx, value, efx_paged_reg(efx, page, reg));
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}
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}
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#define efx_writed_page_locked(efx, value, reg, page) \
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@ -208,6 +208,9 @@ void efx_mcdi_sensor_event(struct efx_nic *efx, efx_qword_t *ev);
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#define _MCDI_DWORD(_buf, _field) \
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((_buf) + (_MCDI_CHECK_ALIGN(MC_CMD_ ## _field ## _OFST, 4) >> 2))
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#define MCDI_BYTE(_buf, _field) \
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((void)BUILD_BUG_ON_ZERO(MC_CMD_ ## _field ## _LEN != 1), \
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*MCDI_PTR(_buf, _field))
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#define MCDI_WORD(_buf, _field) \
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((u16)BUILD_BUG_ON_ZERO(MC_CMD_ ## _field ## _LEN != 2) + \
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le16_to_cpu(*(__force const __le16 *)MCDI_PTR(_buf, _field)))
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@ -708,6 +708,7 @@ struct vfdi_status;
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* @reset_work: Scheduled reset workitem
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* @membase_phys: Memory BAR value as physical address
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* @membase: Memory BAR value
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* @vi_stride: step between per-VI registers / memory regions
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* @interrupt_mode: Interrupt mode
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* @timer_quantum_ns: Interrupt timer quantum, in nanoseconds
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* @timer_max_ns: Interrupt timer maximum value, in nanoseconds
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@ -842,6 +843,8 @@ struct efx_nic {
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resource_size_t membase_phys;
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void __iomem *membase;
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unsigned int vi_stride;
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enum efx_int_mode interrupt_mode;
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unsigned int timer_quantum_ns;
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unsigned int timer_max_ns;
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