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drm/amd/display: Update DP link configuration.
[Why & How] - Update application of training settings for links whose encoders are assigned dynamically. - Add functionality useful for DP link configuration to public interface. Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jimmy Kizito
Alex Deucher
parent
68d9821ff4
commit
7211b60514
2 changed files with 83 additions and 25 deletions
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@ -206,11 +206,12 @@ static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *li
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return DP_TRAINING_PATTERN_SEQUENCE_2;
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}
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static void dpcd_set_link_settings(
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enum dc_status dpcd_set_link_settings(
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struct dc_link *link,
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const struct link_training_settings *lt_settings)
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{
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uint8_t rate;
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enum dc_status status;
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union down_spread_ctrl downspread = { {0} };
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union lane_count_set lane_count_set = { {0} };
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@ -225,15 +226,16 @@ static void dpcd_set_link_settings(
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lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
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if (lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
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if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
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lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
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lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
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link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
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}
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core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
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status = core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
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&downspread.raw, sizeof(downspread));
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core_link_write_dpcd(link, DP_LANE_COUNT_SET,
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status = core_link_write_dpcd(link, DP_LANE_COUNT_SET,
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&lane_count_set.raw, 1);
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if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
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@ -249,12 +251,12 @@ static void dpcd_set_link_settings(
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core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
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supported_link_rates, sizeof(supported_link_rates));
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}
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core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
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core_link_write_dpcd(link, DP_LINK_RATE_SET,
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status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
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status = core_link_write_dpcd(link, DP_LINK_RATE_SET,
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<_settings->link_settings.link_rate_set, 1);
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} else {
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rate = (uint8_t) (lt_settings->link_settings.link_rate);
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core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
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status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
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}
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if (rate) {
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@ -278,6 +280,8 @@ static void dpcd_set_link_settings(
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DP_DOWNSPREAD_CTRL,
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lt_settings->link_settings.link_spread);
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}
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return status;
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}
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static uint8_t dc_dp_initialize_scrambling_data_symbols(
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@ -1329,7 +1333,7 @@ static inline void decide_8b_10b_training_settings(
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lt_settings->enhanced_framing = 1;
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}
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static void decide_training_settings(
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void dp_decide_training_settings(
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struct dc_link *link,
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const struct dc_link_settings *link_settings,
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const struct dc_link_training_overrides *overrides,
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@ -1365,18 +1369,18 @@ uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count)
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return 0; // invalid value
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}
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static void configure_lttpr_mode_transparent(struct dc_link *link)
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enum dc_status configure_lttpr_mode_transparent(struct dc_link *link)
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{
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uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
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DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
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core_link_write_dpcd(link,
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return core_link_write_dpcd(link,
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DP_PHY_REPEATER_MODE,
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(uint8_t *)&repeater_mode,
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sizeof(repeater_mode));
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}
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static void configure_lttpr_mode_non_transparent(
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enum dc_status configure_lttpr_mode_non_transparent(
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struct dc_link *link,
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const struct link_training_settings *lt_settings)
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{
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@ -1431,6 +1435,8 @@ static void configure_lttpr_mode_non_transparent(
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}
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}
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}
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return result;
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}
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static void repeater_training_done(struct dc_link *link, uint32_t offset)
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@ -1564,7 +1570,7 @@ bool dc_link_dp_perform_link_training_skip_aux(
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{
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struct link_training_settings lt_settings;
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decide_training_settings(
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dp_decide_training_settings(
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link,
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link_setting,
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&link->preferred_training_settings,
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@ -1602,6 +1608,19 @@ bool dc_link_dp_perform_link_training_skip_aux(
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return true;
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}
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enum dc_status dpcd_configure_lttpr_mode(struct dc_link *link, struct link_training_settings *lt_settings)
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{
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enum dc_status status = DC_OK;
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if (lt_settings->lttpr_mode == LTTPR_MODE_TRANSPARENT)
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status = configure_lttpr_mode_transparent(link);
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else if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
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status = configure_lttpr_mode_non_transparent(link, lt_settings);
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return status;
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}
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enum link_training_result dc_link_dp_perform_link_training(
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struct dc_link *link,
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const struct dc_link_settings *link_setting,
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@ -1614,7 +1633,7 @@ enum link_training_result dc_link_dp_perform_link_training(
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uint8_t repeater_cnt;
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uint8_t repeater_id;
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decide_training_settings(
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dp_decide_training_settings(
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link,
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link_setting,
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&link->preferred_training_settings,
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@ -1899,7 +1918,7 @@ enum link_training_result dc_link_dp_sync_lt_attempt(
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enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
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bool fec_enable = false;
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decide_training_settings(
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dp_decide_training_settings(
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link,
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link_settings,
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lt_overrides,
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@ -4606,50 +4625,74 @@ enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
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return DP_PANEL_MODE_DEFAULT;
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}
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void dp_set_fec_ready(struct dc_link *link, bool ready)
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enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready)
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{
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/* FEC has to be "set ready" before the link training.
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* The policy is to always train with FEC
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* if the sink supports it and leave it enabled on link.
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* If FEC is not supported, disable it.
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*/
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struct link_encoder *link_enc = link->link_enc;
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struct link_encoder *link_enc = NULL;
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enum dc_status status = DC_OK;
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uint8_t fec_config = 0;
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/* Access link encoder based on whether it is statically
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* or dynamically assigned to a link.
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*/
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if (link->is_dig_mapping_flexible &&
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link->dc->res_pool->funcs->link_encs_assign)
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link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
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else
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link_enc = link->link_enc;
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ASSERT(link_enc);
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if (!dc_link_should_enable_fec(link))
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return;
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return status;
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if (link_enc->funcs->fec_set_ready &&
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link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
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if (ready) {
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fec_config = 1;
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if (core_link_write_dpcd(link,
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status = core_link_write_dpcd(link,
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DP_FEC_CONFIGURATION,
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&fec_config,
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sizeof(fec_config)) == DC_OK) {
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sizeof(fec_config));
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if (status == DC_OK) {
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link_enc->funcs->fec_set_ready(link_enc, true);
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link->fec_state = dc_link_fec_ready;
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} else {
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link->link_enc->funcs->fec_set_ready(link->link_enc, false);
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link_enc->funcs->fec_set_ready(link->link_enc, false);
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link->fec_state = dc_link_fec_not_ready;
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dm_error("dpcd write failed to set fec_ready");
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}
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} else if (link->fec_state == dc_link_fec_ready) {
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fec_config = 0;
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core_link_write_dpcd(link,
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status = core_link_write_dpcd(link,
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DP_FEC_CONFIGURATION,
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&fec_config,
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sizeof(fec_config));
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link->link_enc->funcs->fec_set_ready(
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link->link_enc, false);
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link_enc->funcs->fec_set_ready(link_enc, false);
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link->fec_state = dc_link_fec_not_ready;
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}
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}
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return status;
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}
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void dp_set_fec_enable(struct dc_link *link, bool enable)
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{
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struct link_encoder *link_enc = link->link_enc;
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struct link_encoder *link_enc = NULL;
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/* Access link encoder based on whether it is statically
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* or dynamically assigned to a link.
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*/
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if (link->is_dig_mapping_flexible &&
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link->dc->res_pool->funcs->link_encs_assign)
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link_enc = link_enc_cfg_get_link_enc_used_by_link(
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link->dc->current_state, link);
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else
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link_enc = link->link_enc;
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ASSERT(link_enc);
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if (!dc_link_should_enable_fec(link))
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return;
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@ -92,8 +92,12 @@ void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);
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bool dp_overwrite_extended_receiver_cap(struct dc_link *link);
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void dpcd_set_source_specific_data(struct dc_link *link);
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/* Write DPCD link configuration data. */
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enum dc_status dpcd_set_link_settings(
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struct dc_link *link,
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const struct link_training_settings *lt_settings);
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void dp_set_fec_ready(struct dc_link *link, bool ready);
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enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready);
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void dp_set_fec_enable(struct dc_link *link, bool enable);
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bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
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bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);
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@ -101,6 +105,13 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
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bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
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bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable);
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/* Initialize output parameter lt_settings. */
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void dp_decide_training_settings(
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struct dc_link *link,
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const struct dc_link_settings *link_setting,
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const struct dc_link_training_overrides *overrides,
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struct link_training_settings *lt_settings);
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/* Convert PHY repeater count read from DPCD uint8_t. */
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uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count);
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@ -109,5 +120,9 @@ enum link_training_result dp_check_link_loss_status(
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struct dc_link *link,
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const struct link_training_settings *link_training_setting);
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enum dc_status dpcd_configure_lttpr_mode(
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struct dc_link *link,
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struct link_training_settings *lt_settings);
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enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings);
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#endif /* __DC_LINK_DP_H__ */
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