pwm: dwc: split pci out of core driver
Moving towards adding non-pci support for the driver, move the pci parts out of the core into their own module. This is partly due to the module_driver() code only being allowed once in a module and also to avoid a number of #ifdef if we build a single file in a system without pci support. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230907161242.67190-2-ben.dooks@codethink.co.uk Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This commit is contained in:
Ben Dooks
Thierry Reding
parent
6dbf23f5cf
commit
721ee18848
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@ -186,9 +186,19 @@ config PWM_CROS_EC
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PWM driver for exposing a PWM attached to the ChromeOS Embedded
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Controller.
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config PWM_DWC_CORE
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tristate
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depends on HAS_IOMEM
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help
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PWM driver for Synopsys DWC PWM Controller.
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To compile this driver as a module, build the dependecies as
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modules, this will be called pwm-dwc-core.
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config PWM_DWC
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tristate "DesignWare PWM Controller"
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depends on PCI
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tristate "DesignWare PWM Controller (PCI bus)"
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depends on HAS_IOMEM && PCI
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select PWM_DWC_CORE
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help
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PWM driver for Synopsys DWC PWM Controller attached to a PCI bus.
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@ -15,6 +15,7 @@ obj-$(CONFIG_PWM_CLK) += pwm-clk.o
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obj-$(CONFIG_PWM_CLPS711X) += pwm-clps711x.o
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obj-$(CONFIG_PWM_CRC) += pwm-crc.o
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obj-$(CONFIG_PWM_CROS_EC) += pwm-cros-ec.o
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obj-$(CONFIG_PWM_DWC_CORE) += pwm-dwc-core.o
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obj-$(CONFIG_PWM_DWC) += pwm-dwc.o
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obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o
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obj-$(CONFIG_PWM_FSL_FTM) += pwm-fsl-ftm.o
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@ -0,0 +1,175 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* DesignWare PWM Controller driver core
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*
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* Copyright (C) 2018-2020 Intel Corporation
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*
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* Author: Felipe Balbi (Intel)
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* Author: Jarkko Nikula <jarkko.nikula@linux.intel.com>
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* Author: Raymond Tan <raymond.tan@intel.com>
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*/
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#define DEFAULT_SYMBOL_NAMESPACE dwc_pwm
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#include <linux/bitops.h>
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/pm_runtime.h>
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#include <linux/pwm.h>
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#include "pwm-dwc.h"
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static void __dwc_pwm_set_enable(struct dwc_pwm *dwc, int pwm, int enabled)
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{
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u32 reg;
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reg = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm));
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if (enabled)
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reg |= DWC_TIM_CTRL_EN;
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else
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reg &= ~DWC_TIM_CTRL_EN;
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dwc_pwm_writel(dwc, reg, DWC_TIM_CTRL(pwm));
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}
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static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc,
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struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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u64 tmp;
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u32 ctrl;
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u32 high;
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u32 low;
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/*
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* Calculate width of low and high period in terms of input clock
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* periods and check are the result within HW limits between 1 and
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* 2^32 periods.
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*/
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tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, DWC_CLK_PERIOD_NS);
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if (tmp < 1 || tmp > (1ULL << 32))
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return -ERANGE;
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low = tmp - 1;
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tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle,
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DWC_CLK_PERIOD_NS);
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if (tmp < 1 || tmp > (1ULL << 32))
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return -ERANGE;
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high = tmp - 1;
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/*
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* Specification says timer usage flow is to disable timer, then
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* program it followed by enable. It also says Load Count is loaded
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* into timer after it is enabled - either after a disable or
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* a reset. Based on measurements it happens also without disable
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* whenever Load Count is updated. But follow the specification.
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*/
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__dwc_pwm_set_enable(dwc, pwm->hwpwm, false);
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/*
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* Write Load Count and Load Count 2 registers. Former defines the
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* width of low period and latter the width of high period in terms
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* multiple of input clock periods:
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* Width = ((Count + 1) * input clock period).
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*/
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dwc_pwm_writel(dwc, low, DWC_TIM_LD_CNT(pwm->hwpwm));
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dwc_pwm_writel(dwc, high, DWC_TIM_LD_CNT2(pwm->hwpwm));
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/*
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* Set user-defined mode, timer reloads from Load Count registers
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* when it counts down to 0.
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* Set PWM mode, it makes output to toggle and width of low and high
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* periods are set by Load Count registers.
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*/
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ctrl = DWC_TIM_CTRL_MODE_USER | DWC_TIM_CTRL_PWM;
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dwc_pwm_writel(dwc, ctrl, DWC_TIM_CTRL(pwm->hwpwm));
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/*
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* Enable timer. Output starts from low period.
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*/
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__dwc_pwm_set_enable(dwc, pwm->hwpwm, state->enabled);
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return 0;
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}
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static int dwc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct dwc_pwm *dwc = to_dwc_pwm(chip);
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if (state->polarity != PWM_POLARITY_INVERSED)
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return -EINVAL;
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if (state->enabled) {
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if (!pwm->state.enabled)
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pm_runtime_get_sync(chip->dev);
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return __dwc_pwm_configure_timer(dwc, pwm, state);
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} else {
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if (pwm->state.enabled) {
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__dwc_pwm_set_enable(dwc, pwm->hwpwm, false);
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pm_runtime_put_sync(chip->dev);
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}
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}
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return 0;
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}
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static int dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct dwc_pwm *dwc = to_dwc_pwm(chip);
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u64 duty, period;
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pm_runtime_get_sync(chip->dev);
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state->enabled = !!(dwc_pwm_readl(dwc,
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DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN);
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duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm));
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duty += 1;
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duty *= DWC_CLK_PERIOD_NS;
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state->duty_cycle = duty;
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period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm));
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period += 1;
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period *= DWC_CLK_PERIOD_NS;
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period += duty;
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state->period = period;
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state->polarity = PWM_POLARITY_INVERSED;
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pm_runtime_put_sync(chip->dev);
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return 0;
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}
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static const struct pwm_ops dwc_pwm_ops = {
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.apply = dwc_pwm_apply,
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.get_state = dwc_pwm_get_state,
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};
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struct dwc_pwm *dwc_pwm_alloc(struct device *dev)
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{
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struct dwc_pwm *dwc;
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dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
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if (!dwc)
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return NULL;
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dwc->chip.dev = dev;
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dwc->chip.ops = &dwc_pwm_ops;
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dwc->chip.npwm = DWC_TIMERS_TOTAL;
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dev_set_drvdata(dev, dwc);
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return dwc;
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}
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EXPORT_SYMBOL_GPL(dwc_pwm_alloc);
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MODULE_AUTHOR("Felipe Balbi (Intel)");
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MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
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MODULE_AUTHOR("Raymond Tan <raymond.tan@intel.com>");
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MODULE_DESCRIPTION("DesignWare PWM Controller");
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MODULE_LICENSE("GPL");
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* DesignWare PWM Controller driver
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* DesignWare PWM Controller driver (PCI part)
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*
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* Copyright (C) 2018-2020 Intel Corporation
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*
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@ -13,6 +13,8 @@
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* periods are one or more input clock periods long.
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*/
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#define DEFAULT_MOUDLE_NAMESPACE dwc_pwm
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#include <linux/bitops.h>
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#include <linux/export.h>
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#include <linux/kernel.h>
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@ -21,197 +23,7 @@
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#include <linux/pm_runtime.h>
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#include <linux/pwm.h>
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#define DWC_TIM_LD_CNT(n) ((n) * 0x14)
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#define DWC_TIM_LD_CNT2(n) (((n) * 4) + 0xb0)
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#define DWC_TIM_CUR_VAL(n) (((n) * 0x14) + 0x04)
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#define DWC_TIM_CTRL(n) (((n) * 0x14) + 0x08)
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#define DWC_TIM_EOI(n) (((n) * 0x14) + 0x0c)
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#define DWC_TIM_INT_STS(n) (((n) * 0x14) + 0x10)
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#define DWC_TIMERS_INT_STS 0xa0
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#define DWC_TIMERS_EOI 0xa4
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#define DWC_TIMERS_RAW_INT_STS 0xa8
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#define DWC_TIMERS_COMP_VERSION 0xac
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#define DWC_TIMERS_TOTAL 8
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#define DWC_CLK_PERIOD_NS 10
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/* Timer Control Register */
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#define DWC_TIM_CTRL_EN BIT(0)
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#define DWC_TIM_CTRL_MODE BIT(1)
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#define DWC_TIM_CTRL_MODE_FREE (0 << 1)
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#define DWC_TIM_CTRL_MODE_USER (1 << 1)
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#define DWC_TIM_CTRL_INT_MASK BIT(2)
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#define DWC_TIM_CTRL_PWM BIT(3)
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struct dwc_pwm_ctx {
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u32 cnt;
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u32 cnt2;
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u32 ctrl;
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};
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struct dwc_pwm {
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struct pwm_chip chip;
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void __iomem *base;
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struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL];
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};
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#define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip))
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static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset)
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{
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return readl(dwc->base + offset);
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}
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static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offset)
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{
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writel(value, dwc->base + offset);
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}
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static void __dwc_pwm_set_enable(struct dwc_pwm *dwc, int pwm, int enabled)
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{
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u32 reg;
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reg = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm));
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if (enabled)
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reg |= DWC_TIM_CTRL_EN;
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else
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reg &= ~DWC_TIM_CTRL_EN;
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dwc_pwm_writel(dwc, reg, DWC_TIM_CTRL(pwm));
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}
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static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc,
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struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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u64 tmp;
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u32 ctrl;
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u32 high;
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u32 low;
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/*
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* Calculate width of low and high period in terms of input clock
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* periods and check are the result within HW limits between 1 and
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* 2^32 periods.
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*/
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tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, DWC_CLK_PERIOD_NS);
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if (tmp < 1 || tmp > (1ULL << 32))
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return -ERANGE;
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low = tmp - 1;
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tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle,
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DWC_CLK_PERIOD_NS);
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if (tmp < 1 || tmp > (1ULL << 32))
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return -ERANGE;
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high = tmp - 1;
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/*
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* Specification says timer usage flow is to disable timer, then
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* program it followed by enable. It also says Load Count is loaded
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* into timer after it is enabled - either after a disable or
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* a reset. Based on measurements it happens also without disable
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* whenever Load Count is updated. But follow the specification.
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*/
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__dwc_pwm_set_enable(dwc, pwm->hwpwm, false);
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/*
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* Write Load Count and Load Count 2 registers. Former defines the
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* width of low period and latter the width of high period in terms
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* multiple of input clock periods:
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* Width = ((Count + 1) * input clock period).
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*/
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dwc_pwm_writel(dwc, low, DWC_TIM_LD_CNT(pwm->hwpwm));
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dwc_pwm_writel(dwc, high, DWC_TIM_LD_CNT2(pwm->hwpwm));
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/*
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* Set user-defined mode, timer reloads from Load Count registers
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* when it counts down to 0.
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* Set PWM mode, it makes output to toggle and width of low and high
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* periods are set by Load Count registers.
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*/
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ctrl = DWC_TIM_CTRL_MODE_USER | DWC_TIM_CTRL_PWM;
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dwc_pwm_writel(dwc, ctrl, DWC_TIM_CTRL(pwm->hwpwm));
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/*
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* Enable timer. Output starts from low period.
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*/
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__dwc_pwm_set_enable(dwc, pwm->hwpwm, state->enabled);
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return 0;
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}
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static int dwc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct dwc_pwm *dwc = to_dwc_pwm(chip);
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if (state->polarity != PWM_POLARITY_INVERSED)
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return -EINVAL;
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if (state->enabled) {
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if (!pwm->state.enabled)
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pm_runtime_get_sync(chip->dev);
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return __dwc_pwm_configure_timer(dwc, pwm, state);
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} else {
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if (pwm->state.enabled) {
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__dwc_pwm_set_enable(dwc, pwm->hwpwm, false);
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pm_runtime_put_sync(chip->dev);
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}
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}
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return 0;
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}
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static int dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct dwc_pwm *dwc = to_dwc_pwm(chip);
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u64 duty, period;
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pm_runtime_get_sync(chip->dev);
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state->enabled = !!(dwc_pwm_readl(dwc,
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DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN);
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duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm));
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duty += 1;
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duty *= DWC_CLK_PERIOD_NS;
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state->duty_cycle = duty;
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period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm));
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period += 1;
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period *= DWC_CLK_PERIOD_NS;
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period += duty;
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state->period = period;
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state->polarity = PWM_POLARITY_INVERSED;
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pm_runtime_put_sync(chip->dev);
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return 0;
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}
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static const struct pwm_ops dwc_pwm_ops = {
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.apply = dwc_pwm_apply,
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.get_state = dwc_pwm_get_state,
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};
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static struct dwc_pwm *dwc_pwm_alloc(struct device *dev)
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{
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struct dwc_pwm *dwc;
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dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
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if (!dwc)
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return NULL;
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dwc->chip.dev = dev;
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dwc->chip.ops = &dwc_pwm_ops;
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dwc->chip.npwm = DWC_TIMERS_TOTAL;
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dev_set_drvdata(dev, dwc);
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return dwc;
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}
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#include "pwm-dwc.h"
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static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id)
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{
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@ -0,0 +1,60 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* DesignWare PWM Controller driver
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*
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||||
* Copyright (C) 2018-2020 Intel Corporation
|
||||
*
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* Author: Felipe Balbi (Intel)
|
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* Author: Jarkko Nikula <jarkko.nikula@linux.intel.com>
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* Author: Raymond Tan <raymond.tan@intel.com>
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*/
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MODULE_IMPORT_NS(dwc_pwm);
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#define DWC_TIM_LD_CNT(n) ((n) * 0x14)
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#define DWC_TIM_LD_CNT2(n) (((n) * 4) + 0xb0)
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#define DWC_TIM_CUR_VAL(n) (((n) * 0x14) + 0x04)
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#define DWC_TIM_CTRL(n) (((n) * 0x14) + 0x08)
|
||||
#define DWC_TIM_EOI(n) (((n) * 0x14) + 0x0c)
|
||||
#define DWC_TIM_INT_STS(n) (((n) * 0x14) + 0x10)
|
||||
|
||||
#define DWC_TIMERS_INT_STS 0xa0
|
||||
#define DWC_TIMERS_EOI 0xa4
|
||||
#define DWC_TIMERS_RAW_INT_STS 0xa8
|
||||
#define DWC_TIMERS_COMP_VERSION 0xac
|
||||
|
||||
#define DWC_TIMERS_TOTAL 8
|
||||
#define DWC_CLK_PERIOD_NS 10
|
||||
|
||||
/* Timer Control Register */
|
||||
#define DWC_TIM_CTRL_EN BIT(0)
|
||||
#define DWC_TIM_CTRL_MODE BIT(1)
|
||||
#define DWC_TIM_CTRL_MODE_FREE (0 << 1)
|
||||
#define DWC_TIM_CTRL_MODE_USER (1 << 1)
|
||||
#define DWC_TIM_CTRL_INT_MASK BIT(2)
|
||||
#define DWC_TIM_CTRL_PWM BIT(3)
|
||||
|
||||
struct dwc_pwm_ctx {
|
||||
u32 cnt;
|
||||
u32 cnt2;
|
||||
u32 ctrl;
|
||||
};
|
||||
|
||||
struct dwc_pwm {
|
||||
struct pwm_chip chip;
|
||||
void __iomem *base;
|
||||
struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL];
|
||||
};
|
||||
#define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip))
|
||||
|
||||
static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset)
|
||||
{
|
||||
return readl(dwc->base + offset);
|
||||
}
|
||||
|
||||
static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offset)
|
||||
{
|
||||
writel(value, dwc->base + offset);
|
||||
}
|
||||
|
||||
extern struct dwc_pwm *dwc_pwm_alloc(struct device *dev);
|
||||
Loading…
Reference in New Issue