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drm/amdgpu: enter rlc safe mode before set cgpg
Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 3 additions and 4 deletions
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@ -3394,8 +3394,7 @@ static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
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static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
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static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
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bool enable)
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bool enable)
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{
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{
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/* TODO: double check if we need to perform under safe mdoe */
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gfx_v9_0_enter_rlc_safe_mode(adev);
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/* gfx_v9_0_enter_rlc_safe_mode(adev); */
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if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
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if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
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gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
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gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
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@ -3406,7 +3405,7 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
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gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
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gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
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}
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}
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/* gfx_v9_0_exit_rlc_safe_mode(adev); */
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gfx_v9_0_exit_rlc_safe_mode(adev);
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}
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}
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static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
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static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
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@ -3797,7 +3796,7 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
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}
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}
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amdgpu_ring_write(ring, header);
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amdgpu_ring_write(ring, header);
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BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
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BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
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amdgpu_ring_write(ring,
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amdgpu_ring_write(ring,
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#ifdef __BIG_ENDIAN
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#ifdef __BIG_ENDIAN
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(2 << 0) |
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(2 << 0) |
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