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MIPS: OCTEON: Core-15169 Workaround and general CVMSEG cleanup.
Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8943/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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2 changed files with 17 additions and 6 deletions
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@ -579,12 +579,10 @@ void octeon_user_io_init(void)
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/* R/W If set, CVMSEG is available for loads/stores in user
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* mode. */
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cvmmemctl.s.cvmsegenau = 0;
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/* R/W Size of local memory in cache blocks, 54 (6912 bytes)
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* is max legal value. */
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cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE;
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write_c0_cvmmemctl(cvmmemctl.u64);
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/* Setup of CVMSEG is done in kernel-entry-init.h */
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if (smp_processor_id() == 0)
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pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
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CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
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@ -8,11 +8,10 @@
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#ifndef __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
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#define __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
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#define CP0_CYCLE_COUNTER $9, 6
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#define CP0_CVMCTL_REG $9, 7
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#define CP0_CVMMEMCTL_REG $11,7
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#define CP0_PRID_REG $15, 0
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#define CP0_DCACHE_ERR_REG $27, 1
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#define CP0_PRID_OCTEON_PASS1 0x000d0000
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#define CP0_PRID_OCTEON_CN30XX 0x000d0200
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@ -60,7 +59,7 @@
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skip:
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# First clear off CvmCtl[IPPCI] bit and move the performance
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# counters interrupt to IRQ 6
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li v1, ~(7 << 7)
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dli v1, ~(7 << 7)
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and v0, v0, v1
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ori v0, v0, (6 << 7)
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@ -90,6 +89,20 @@
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sync
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# Flush dcache after config change
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cache 9, 0($0)
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# Zero all of CVMSEG to make sure parity is correct
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dli v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
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dsll v0, 7
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beqz v0, 2f
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1: dsubu v0, 8
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sd $0, -32768(v0)
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bnez v0, 1b
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2:
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mfc0 v0, CP0_PRID_REG
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bbit0 v0, 15, 1f
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# OCTEON II or better have bit 15 set. Clear the error bits.
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dli v0, 0x27
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dmtc0 v0, CP0_DCACHE_ERR_REG
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1:
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# Get my core id
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rdhwr v0, $0
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# Jump the master to kernel_entry
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