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[PARISC] remove remnants of parisc-specific softirq code
Kyle, This patch removes remnants of softirq support that we no longer need. I suspect this was just overlooked when willy convert parisc to generic IRQ support. Tested on c3600 32-bit UP. Signed-off-by: Grant Grundler <grundler@parisc-linux.org> [and tested on a c8000 64-bit SMP --kyle] Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
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1 changed files with 1 additions and 34 deletions
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@ -954,21 +954,6 @@ intr_return:
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/* NOTE: Need to enable interrupts incase we schedule. */
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ssm PSW_SM_I, %r0
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/* Check for software interrupts */
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.import irq_stat,data
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load32 irq_stat,%r19
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#ifdef CONFIG_SMP
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mfctl %cr30,%r1
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ldw TI_CPU(%r1),%r1 /* get cpu # - int */
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/* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) amount
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** irq_stat[] is defined using ____cacheline_aligned.
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*/
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SHLREG %r1,L1_CACHE_SHIFT,%r20
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add %r19,%r20,%r19 /* now have &irq_stat[smp_processor_id()] */
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#endif /* CONFIG_SMP */
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intr_check_resched:
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/* check for reschedule */
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@ -2055,24 +2040,6 @@ ENTRY(syscall_exit)
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*/
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loadgp
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syscall_check_bh:
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/* Check for software interrupts */
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.import irq_stat,data
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load32 irq_stat,%r19
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#ifdef CONFIG_SMP
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/* sched.h: int processor */
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/* %r26 is used as scratch register to index into irq_stat[] */
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ldw TI_CPU-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26 /* cpu # */
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/* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) bits */
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SHLREG %r26,L1_CACHE_SHIFT,%r20
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add %r19,%r20,%r19 /* now have &irq_stat[smp_processor_id()] */
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#endif /* CONFIG_SMP */
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syscall_check_resched:
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/* check for reschedule */
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@ -2244,7 +2211,7 @@ syscall_do_resched:
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#else
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nop
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#endif
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b syscall_check_bh /* if resched, we start over again */
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b syscall_check_resched /* if resched, we start over again */
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nop
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ENDPROC(syscall_exit)
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