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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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crypto: chcr - Fix txq ids.
The patch fixes a critical issue to map txqid with flows on the hardware appropriately, if tx queues created are more than flows configured then txqid shall map within the range of hardware flows configured. This ensure that un-mapped txqid does not remain un-handled. The patch also segregated the rxqid and txqid for clarity. Signed-off-by: Atul Gupta <atul.gupta@chelsio.com> Reviewed-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
parent
0a7bd30c1b
commit
72a56ca97d
6 changed files with 44 additions and 21 deletions
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@ -522,7 +522,7 @@ static inline void create_wreq(struct chcr_context *ctx,
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{
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{
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struct uld_ctx *u_ctx = ULD_CTX(ctx);
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struct uld_ctx *u_ctx = ULD_CTX(ctx);
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int iv_loc = IV_DSGL;
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int iv_loc = IV_DSGL;
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int qid = u_ctx->lldi.rxq_ids[ctx->tx_channel_id];
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int qid = u_ctx->lldi.rxq_ids[ctx->rx_qidx];
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unsigned int immdatalen = 0, nr_frags = 0;
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unsigned int immdatalen = 0, nr_frags = 0;
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if (is_ofld_imm(skb)) {
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if (is_ofld_imm(skb)) {
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@ -543,7 +543,7 @@ static inline void create_wreq(struct chcr_context *ctx,
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chcr_req->wreq.cookie = cpu_to_be64((uintptr_t)req);
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chcr_req->wreq.cookie = cpu_to_be64((uintptr_t)req);
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chcr_req->wreq.rx_chid_to_rx_q_id =
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chcr_req->wreq.rx_chid_to_rx_q_id =
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FILL_WR_RX_Q_ID(ctx->dev->rx_channel_id, qid,
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FILL_WR_RX_Q_ID(ctx->dev->rx_channel_id, qid,
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is_iv ? iv_loc : IV_NOP, ctx->tx_channel_id);
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is_iv ? iv_loc : IV_NOP, ctx->tx_qidx);
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chcr_req->ulptx.cmd_dest = FILL_ULPTX_CMD_DEST(ctx->dev->tx_channel_id,
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chcr_req->ulptx.cmd_dest = FILL_ULPTX_CMD_DEST(ctx->dev->tx_channel_id,
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qid);
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qid);
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@ -721,19 +721,19 @@ static int chcr_aes_encrypt(struct ablkcipher_request *req)
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struct sk_buff *skb;
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struct sk_buff *skb;
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if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
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if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
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ctx->tx_channel_id))) {
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ctx->tx_qidx))) {
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if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
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if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
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return -EBUSY;
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return -EBUSY;
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}
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}
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skb = create_cipher_wr(req, u_ctx->lldi.rxq_ids[ctx->tx_channel_id],
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skb = create_cipher_wr(req, u_ctx->lldi.rxq_ids[ctx->rx_qidx],
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CHCR_ENCRYPT_OP);
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CHCR_ENCRYPT_OP);
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if (IS_ERR(skb)) {
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if (IS_ERR(skb)) {
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pr_err("chcr : %s : Failed to form WR. No memory\n", __func__);
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pr_err("chcr : %s : Failed to form WR. No memory\n", __func__);
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return PTR_ERR(skb);
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return PTR_ERR(skb);
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}
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}
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skb->dev = u_ctx->lldi.ports[0];
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skb->dev = u_ctx->lldi.ports[0];
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set_wr_txq(skb, CPL_PRIORITY_DATA, ctx->tx_channel_id);
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set_wr_txq(skb, CPL_PRIORITY_DATA, ctx->tx_qidx);
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chcr_send_wr(skb);
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chcr_send_wr(skb);
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return -EINPROGRESS;
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return -EINPROGRESS;
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}
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}
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@ -746,19 +746,19 @@ static int chcr_aes_decrypt(struct ablkcipher_request *req)
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struct sk_buff *skb;
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struct sk_buff *skb;
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if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
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if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
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ctx->tx_channel_id))) {
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ctx->tx_qidx))) {
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if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
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if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
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return -EBUSY;
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return -EBUSY;
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}
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}
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skb = create_cipher_wr(req, u_ctx->lldi.rxq_ids[0],
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skb = create_cipher_wr(req, u_ctx->lldi.rxq_ids[ctx->rx_qidx],
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CHCR_DECRYPT_OP);
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CHCR_DECRYPT_OP);
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if (IS_ERR(skb)) {
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if (IS_ERR(skb)) {
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pr_err("chcr : %s : Failed to form WR. No memory\n", __func__);
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pr_err("chcr : %s : Failed to form WR. No memory\n", __func__);
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return PTR_ERR(skb);
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return PTR_ERR(skb);
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}
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}
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skb->dev = u_ctx->lldi.ports[0];
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skb->dev = u_ctx->lldi.ports[0];
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set_wr_txq(skb, CPL_PRIORITY_DATA, ctx->tx_channel_id);
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set_wr_txq(skb, CPL_PRIORITY_DATA, ctx->tx_qidx);
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chcr_send_wr(skb);
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chcr_send_wr(skb);
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return -EINPROGRESS;
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return -EINPROGRESS;
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}
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}
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@ -766,7 +766,9 @@ static int chcr_aes_decrypt(struct ablkcipher_request *req)
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static int chcr_device_init(struct chcr_context *ctx)
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static int chcr_device_init(struct chcr_context *ctx)
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{
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{
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struct uld_ctx *u_ctx;
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struct uld_ctx *u_ctx;
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struct adapter *adap;
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unsigned int id;
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unsigned int id;
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int txq_perchan, txq_idx, ntxq;
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int err = 0, rxq_perchan, rxq_idx;
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int err = 0, rxq_perchan, rxq_idx;
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id = smp_processor_id();
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id = smp_processor_id();
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@ -777,11 +779,18 @@ static int chcr_device_init(struct chcr_context *ctx)
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goto out;
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goto out;
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}
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}
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u_ctx = ULD_CTX(ctx);
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u_ctx = ULD_CTX(ctx);
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adap = padap(ctx->dev);
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ntxq = min_not_zero((unsigned int)u_ctx->lldi.nrxq,
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adap->vres.ncrypto_fc);
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rxq_perchan = u_ctx->lldi.nrxq / u_ctx->lldi.nchan;
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rxq_perchan = u_ctx->lldi.nrxq / u_ctx->lldi.nchan;
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txq_perchan = ntxq / u_ctx->lldi.nchan;
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rxq_idx = ctx->dev->tx_channel_id * rxq_perchan;
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rxq_idx = ctx->dev->tx_channel_id * rxq_perchan;
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rxq_idx += id % rxq_perchan;
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rxq_idx += id % rxq_perchan;
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txq_idx = ctx->dev->tx_channel_id * txq_perchan;
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txq_idx += id % txq_perchan;
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spin_lock(&ctx->dev->lock_chcr_dev);
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spin_lock(&ctx->dev->lock_chcr_dev);
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ctx->tx_channel_id = rxq_idx;
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ctx->rx_qidx = rxq_idx;
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ctx->tx_qidx = txq_idx;
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ctx->dev->tx_channel_id = !ctx->dev->tx_channel_id;
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ctx->dev->tx_channel_id = !ctx->dev->tx_channel_id;
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ctx->dev->rx_channel_id = 0;
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ctx->dev->rx_channel_id = 0;
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spin_unlock(&ctx->dev->lock_chcr_dev);
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spin_unlock(&ctx->dev->lock_chcr_dev);
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@ -935,7 +944,7 @@ static int chcr_ahash_update(struct ahash_request *req)
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u_ctx = ULD_CTX(ctx);
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u_ctx = ULD_CTX(ctx);
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if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
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if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
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ctx->tx_channel_id))) {
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ctx->tx_qidx))) {
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if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
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if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
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return -EBUSY;
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return -EBUSY;
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}
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}
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@ -975,7 +984,7 @@ static int chcr_ahash_update(struct ahash_request *req)
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}
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}
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req_ctx->reqlen = remainder;
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req_ctx->reqlen = remainder;
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skb->dev = u_ctx->lldi.ports[0];
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skb->dev = u_ctx->lldi.ports[0];
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set_wr_txq(skb, CPL_PRIORITY_DATA, ctx->tx_channel_id);
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set_wr_txq(skb, CPL_PRIORITY_DATA, ctx->tx_qidx);
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chcr_send_wr(skb);
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chcr_send_wr(skb);
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return -EINPROGRESS;
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return -EINPROGRESS;
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@ -1028,7 +1037,7 @@ static int chcr_ahash_final(struct ahash_request *req)
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return -ENOMEM;
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return -ENOMEM;
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skb->dev = u_ctx->lldi.ports[0];
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skb->dev = u_ctx->lldi.ports[0];
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set_wr_txq(skb, CPL_PRIORITY_DATA, ctx->tx_channel_id);
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set_wr_txq(skb, CPL_PRIORITY_DATA, ctx->tx_qidx);
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chcr_send_wr(skb);
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chcr_send_wr(skb);
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return -EINPROGRESS;
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return -EINPROGRESS;
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}
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}
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@ -1047,7 +1056,7 @@ static int chcr_ahash_finup(struct ahash_request *req)
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u_ctx = ULD_CTX(ctx);
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u_ctx = ULD_CTX(ctx);
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if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
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if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
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ctx->tx_channel_id))) {
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ctx->tx_qidx))) {
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if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
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if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
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return -EBUSY;
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return -EBUSY;
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}
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}
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@ -1079,7 +1088,7 @@ static int chcr_ahash_finup(struct ahash_request *req)
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return -ENOMEM;
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return -ENOMEM;
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skb->dev = u_ctx->lldi.ports[0];
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skb->dev = u_ctx->lldi.ports[0];
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set_wr_txq(skb, CPL_PRIORITY_DATA, ctx->tx_channel_id);
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set_wr_txq(skb, CPL_PRIORITY_DATA, ctx->tx_qidx);
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chcr_send_wr(skb);
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chcr_send_wr(skb);
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return -EINPROGRESS;
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return -EINPROGRESS;
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@ -1100,7 +1109,7 @@ static int chcr_ahash_digest(struct ahash_request *req)
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u_ctx = ULD_CTX(ctx);
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u_ctx = ULD_CTX(ctx);
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if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
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if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
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ctx->tx_channel_id))) {
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ctx->tx_qidx))) {
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if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
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if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
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return -EBUSY;
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return -EBUSY;
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}
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}
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@ -1130,7 +1139,7 @@ static int chcr_ahash_digest(struct ahash_request *req)
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return -ENOMEM;
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return -ENOMEM;
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skb->dev = u_ctx->lldi.ports[0];
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skb->dev = u_ctx->lldi.ports[0];
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set_wr_txq(skb, CPL_PRIORITY_DATA, ctx->tx_channel_id);
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set_wr_txq(skb, CPL_PRIORITY_DATA, ctx->tx_qidx);
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chcr_send_wr(skb);
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chcr_send_wr(skb);
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return -EINPROGRESS;
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return -EINPROGRESS;
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}
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}
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@ -2451,13 +2460,13 @@ static int chcr_aead_op(struct aead_request *req,
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}
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}
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u_ctx = ULD_CTX(ctx);
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u_ctx = ULD_CTX(ctx);
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if (cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
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if (cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
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ctx->tx_channel_id)) {
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ctx->tx_qidx)) {
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if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
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if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
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return -EBUSY;
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return -EBUSY;
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}
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}
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/* Form a WR from req */
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/* Form a WR from req */
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skb = create_wr_fn(req, u_ctx->lldi.rxq_ids[ctx->tx_channel_id], size,
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skb = create_wr_fn(req, u_ctx->lldi.rxq_ids[ctx->rx_qidx], size,
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op_type);
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op_type);
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if (IS_ERR(skb) || skb == NULL) {
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if (IS_ERR(skb) || skb == NULL) {
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@ -2466,7 +2475,7 @@ static int chcr_aead_op(struct aead_request *req,
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}
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}
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skb->dev = u_ctx->lldi.ports[0];
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skb->dev = u_ctx->lldi.ports[0];
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set_wr_txq(skb, CPL_PRIORITY_DATA, ctx->tx_channel_id);
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set_wr_txq(skb, CPL_PRIORITY_DATA, ctx->tx_qidx);
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chcr_send_wr(skb);
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chcr_send_wr(skb);
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return -EINPROGRESS;
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return -EINPROGRESS;
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}
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}
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@ -54,6 +54,8 @@
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#define CHK_MAC_ERR_BIT(x) (((x) >> MAC_ERROR_BIT) & 1)
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#define CHK_MAC_ERR_BIT(x) (((x) >> MAC_ERROR_BIT) & 1)
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#define MAX_SALT 4
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#define MAX_SALT 4
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#define padap(dev) pci_get_drvdata(dev->u_ctx->lldi.pdev)
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struct uld_ctx;
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struct uld_ctx;
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struct _key_ctx {
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struct _key_ctx {
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@ -211,7 +211,8 @@ struct __crypto_ctx {
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struct chcr_context {
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struct chcr_context {
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struct chcr_dev *dev;
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struct chcr_dev *dev;
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unsigned char tx_channel_id;
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unsigned char tx_qidx;
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unsigned char rx_qidx;
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struct __crypto_ctx crypto_ctx[0];
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struct __crypto_ctx crypto_ctx[0];
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};
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};
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@ -3809,6 +3809,15 @@ static int adap_init0(struct adapter *adap)
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}
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}
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if (caps_cmd.cryptocaps) {
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if (caps_cmd.cryptocaps) {
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/* Should query params here...TODO */
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/* Should query params here...TODO */
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params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE);
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ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
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params, val);
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if (ret < 0) {
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if (ret != -EINVAL)
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goto bye;
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} else {
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adap->vres.ncrypto_fc = val[0];
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}
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adap->params.crypto |= ULP_CRYPTO_LOOKASIDE;
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adap->params.crypto |= ULP_CRYPTO_LOOKASIDE;
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adap->num_uld += 1;
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adap->num_uld += 1;
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}
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}
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@ -272,6 +272,7 @@ struct cxgb4_virt_res { /* virtualized HW resources */
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struct cxgb4_range qp;
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struct cxgb4_range qp;
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struct cxgb4_range cq;
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struct cxgb4_range cq;
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struct cxgb4_range ocq;
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struct cxgb4_range ocq;
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unsigned int ncrypto_fc;
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};
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};
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#define OCQ_WIN_OFFSET(pdev, vres) \
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#define OCQ_WIN_OFFSET(pdev, vres) \
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@ -1167,7 +1167,8 @@ enum fw_params_param_pfvf {
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FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
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FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
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FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
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FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
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FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
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FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
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FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31
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FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
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FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x32
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};
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};
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/*
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/*
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