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ARM: 8830/1: NOMMU: Toggle only bits in EXC_RETURN we are really care of
ARMv8M introduces support for Security extension to M class, among other things it affects exception handling, especially, encoding of EXC_RETURN. The new bits have been added: Bit [6] Secure or Non-secure stack Bit [5] Default callee register stacking Bit [0] Exception Secure which conflicts with hard-coded value of EXC_RETURN: In fact, we only care of few bits: Bit [3] Mode (0 - Handler, 1 - Thread) Bit [2] Stack pointer selection (0 - Main, 1 - Process) We can toggle only those bits and left other bits as they were on exception entry. It is basically, what patch does - saves EXC_RETURN when we do transition form Thread to Handler mode (it is first svc), so later saved value is used instead of EXC_RET_THREADMODE_PROCESSSTACK. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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4 changed files with 10 additions and 2 deletions
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@ -49,7 +49,7 @@
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* (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
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*/
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#define EXC_RET_STACK_MASK 0x00000004
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#define EXC_RET_THREADMODE_PROCESSSTACK 0xfffffffd
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#define EXC_RET_THREADMODE_PROCESSSTACK (3 << 2)
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/* Cache related definitions */
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@ -127,7 +127,8 @@
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*/
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.macro v7m_exception_slow_exit ret_r0
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cpsid i
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ldr lr, =EXC_RET_THREADMODE_PROCESSSTACK
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ldr lr, =exc_ret
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ldr lr, [lr]
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@ read original r12, sp, lr, pc and xPSR
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add r12, sp, #S_IP
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@ -146,3 +146,7 @@ ENTRY(vector_table)
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.rept CONFIG_CPU_V7M_NUM_IRQ
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.long __irq_entry @ External Interrupts
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.endr
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.align 2
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.globl exc_ret
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exc_ret:
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.space 4
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@ -139,6 +139,9 @@ __v7m_setup_cont:
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cpsie i
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svc #0
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1: cpsid i
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ldr r0, =exc_ret
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orr lr, lr, #EXC_RET_THREADMODE_PROCESSSTACK
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str lr, [r0]
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ldmia sp, {r0-r3, r12}
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str r5, [r12, #11 * 4] @ restore the original SVC vector entry
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mov lr, r6 @ restore LR
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