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clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL
Until commit05f814402d
("clk: meson: add fdiv clock gates") we relied on the bootloader to enable the fclk_div clock gates. It turns out that our clock tree is incomplete at least on Meson8b (tested with an Odroid-C1, which uses an RGMII PHY) because after the mentioned commit Ethernet is not working anymore (no RX/TX activity can be seen). At the same time Ethernet was still working on Meson8m2 with a RMII PHY. Testing has shown that as soon as "fclk_div2" is disabled Ethernet stops working on Odroid-C1. Unfortunately it's currently not clear what the Ethernet controller IP block uses the fclk_div2 clock for. Mark the clock as CLK_IS_CRITICAL to keep it enabled (as it's already enabled by most bootloaders by default, which is why we didn't notice it before). Fixes:05f814402d
("clk: meson: add fdiv clock gates") Cc: stable@vger.kernel.org Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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@ -232,6 +232,13 @@ static struct clk_regmap meson8b_fclk_div2 = {
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.ops = &clk_regmap_gate_ops,
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "fclk_div2_div" },
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.parent_names = (const char *[]){ "fclk_div2_div" },
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.num_parents = 1,
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.num_parents = 1,
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/*
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* FIXME: Ethernet with a RGMII PHYs is not working if
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* fclk_div2 is disabled. it is currently unclear why this
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* is. keep it enabled until the Ethernet driver knows how
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* to manage this clock.
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*/
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.flags = CLK_IS_CRITICAL,
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},
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},
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};
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};
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