mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-03 07:38:10 +00:00
mvebu dt for 4.9 (part 1)
- update for Armada XP/38x allowing using direct access SPI - various improvement for Armada 39x platforms - add pinctrl information for NANd on Armada 38x - fix the kirkwood based Openblock A6 external GPIO pins -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEABECAAYFAlfMQ0gACgkQCwYYjhRyO9XZQgCfVtygCoGhhk2ou4huuBcWlutL It0An1jM4iRF4RwgWtikxEV00Ovg4dJw =LoDw -----END PGP SIGNATURE----- Merge tag 'mvebu-dt-4.9-1' of git://git.infradead.org/linux-mvebu into next/dt Pull "mvebu dt for 4.9 (part 1)" from Gregory CLEMENT: - update for Armada XP/38x allowing using direct access SPI - various improvement for Armada 39x platforms - add pinctrl information for NANd on Armada 38x - fix the kirkwood based Openblock A6 external GPIO pins * tag 'mvebu-dt-4.9-1' of git://git.infradead.org/linux-mvebu: ARM: dts: mvebu: fix reference to a390 spi controller ARM: dts: armada-38x: Add NAND pinctrl information ARM: dts: kirkwood: Fix Openblock A6 external GPIO pins ARM: dts: mvebu: armada-395-gp: add support for the Armada 395 GP Board ARM: dts: mvebu: armada-390-db: add support for the Armada 390 DB board ARM: dts: mvebu: armada-398-db: enable supported usb interfaces ARM: dts: mvebu: armada-398: update the dtsi about missing interfaces ARM: dts: mvebu: armada-395: add support for the Armada 395 SoC family ARM: dts: mvebu: armada-39x: enable rtc for all Armada-39x SoCs ARM: dts: mvebu: armada-39x: add missing nodes describing GPIO's ARM: dts: mvebu: armada-39x: enable watchdog for all Armada-39x SoCs ARM: dts: mvebu: armada-39x: enable the thermal sensor in Armada-39x SoCs ARM: dts: mvebu: armada-39x: enable PMU, CA9 SoC Controller and Coherency fabric ARM: dts: mvebu: armada-39x: update the SDHCI node on Armada 39x ARM: dts: mvebu: armada-390: add missing compatibility string and bracket ARM: dts: mvebu: a385-db-ap: add default partition description for NAND ARM: dts: mvebu: a385-db-ap: enable USB (orion-ehci) port ARM: dts: mvebu: armada-370-xp: Add MBus mappings for all SPI devices ARM: dts: mvebu: A37x/XP/38x/39x: Move SPI controller nodes into 'soc' node ARM: dts: mvebu: Add SPI1 pinctrl defines for Armada XP
This commit is contained in:
Arnd Bergmann
commit
72f61d2e92
27 changed files with 988 additions and 407 deletions
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@ -8,8 +8,19 @@ Required root node property:
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|||
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||||
- compatible: must contain "marvell,armada390"
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||||
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||||
In addition, boards using the Marvell Armada 398 SoC shall have the
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||||
following property before the previous one:
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||||
In addition, boards using the Marvell Armada 395 SoC shall have the
|
||||
following property before the common "marvell,armada390" one:
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||||
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||||
Required root node property:
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||||
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||||
compatible: must contain "marvell,armada395"
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||||
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||||
Example:
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||||
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||||
compatible = "marvell,a395-gp", "marvell,armada395", "marvell,armada390";
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||||
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||||
Boards using the Marvell Armada 398 SoC shall have the following
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property before the common "marvell,armada390" one:
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Required root node property:
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||||
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@ -155,20 +155,6 @@ usb@51000 {
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status = "okay";
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};
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spi0: spi@10600 {
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pinctrl-0 = <&spi0_pins2>;
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pinctrl-names = "default";
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mx25l25635e", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <50000000>;
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};
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};
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nand@d0000 {
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status = "okay";
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num-cs = <1>;
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@ -274,3 +260,18 @@ spdif_in: spdif-in {
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compatible = "linux,spdif-dir";
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};
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};
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&spi0 {
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pinctrl-0 = <&spi0_pins2>;
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pinctrl-names = "default";
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mx25l25635e", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <50000000>;
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};
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};
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@ -68,26 +68,6 @@ ethernet@74000 {
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phy-mode = "rgmii-id";
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};
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spi@10600 {
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status = "okay";
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pinctrl-0 = <&spi0_pins2>;
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pinctrl-names = "default";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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/* MX25L8006E */
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compatible = "mxicy,mx25l8005", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <50000000>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x100000>;
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};
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};
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};
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usb@50000 {
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status = "okay";
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};
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@ -176,3 +156,23 @@ gpio_led_pin: gpio-led-pin {
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marvell,function = "gpio";
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};
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};
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&spi0 {
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status = "okay";
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pinctrl-0 = <&spi0_pins2>;
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pinctrl-names = "default";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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/* MX25L8006E */
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compatible = "mxicy,mx25l8005", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <50000000>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x100000>;
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};
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};
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};
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@ -87,62 +87,6 @@ rtc@10300 {
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status = "disabled";
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};
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spi0: spi@10600 {
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q064", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <20000000>;
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/*
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* Warning!
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*
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* Synology u-boot uses its compiled-in environment
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* and it seems Synology did not care to change u-boot
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* default configuration in order to allow saving a
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* modified environment at a sensible location. So,
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* if you do a 'saveenv' under u-boot, your modified
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* environment will be saved at 1MB after the start
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* of the flash, i.e. in the middle of the uImage.
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* For that reason, it is strongly advised not to
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* change the default environment, unless you know
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* what you are doing.
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*/
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partition@00000000 { /* u-boot */
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label = "RedBoot";
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reg = <0x00000000 0x000c0000>; /* 768KB */
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};
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partition@000c0000 { /* uImage */
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label = "zImage";
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reg = <0x000c0000 0x002d0000>; /* 2880KB */
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};
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partition@00390000 { /* uInitramfs */
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label = "rd.gz";
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reg = <0x00390000 0x00440000>; /* 4250KB */
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};
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partition@007d0000 { /* MAC address and serial number */
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label = "vendor";
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reg = <0x007d0000 0x00010000>; /* 64KB */
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};
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partition@007e0000 {
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label = "RedBoot config";
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reg = <0x007e0000 0x00010000>; /* 64KB */
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};
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partition@007f0000 {
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label = "FIS directory";
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reg = <0x007f0000 0x00010000>; /* 64KB */
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};
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};
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};
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i2c@11000 {
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compatible = "marvell,mv64xxx-i2c";
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pinctrl-0 = <&i2c0_pins>;
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@ -347,3 +291,59 @@ fan_alarm_pin: fan-alarm-pin {
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marvell,function = "gpio";
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};
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};
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&spi0 {
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q064", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <20000000>;
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/*
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* Warning!
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*
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* Synology u-boot uses its compiled-in environment
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* and it seems Synology did not care to change u-boot
|
||||
* default configuration in order to allow saving a
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||||
* modified environment at a sensible location. So,
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* if you do a 'saveenv' under u-boot, your modified
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* environment will be saved at 1MB after the start
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* of the flash, i.e. in the middle of the uImage.
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* For that reason, it is strongly advised not to
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* change the default environment, unless you know
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* what you are doing.
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*/
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partition@00000000 { /* u-boot */
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label = "RedBoot";
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reg = <0x00000000 0x000c0000>; /* 768KB */
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};
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partition@000c0000 { /* uImage */
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label = "zImage";
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reg = <0x000c0000 0x002d0000>; /* 2880KB */
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};
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partition@00390000 { /* uInitramfs */
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label = "rd.gz";
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reg = <0x00390000 0x00440000>; /* 4250KB */
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};
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partition@007d0000 { /* MAC address and serial number */
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label = "vendor";
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reg = <0x007d0000 0x00010000>; /* 64KB */
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};
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partition@007e0000 {
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label = "RedBoot config";
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reg = <0x007e0000 0x00010000>; /* 64KB */
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};
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partition@007f0000 {
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label = "FIS directory";
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reg = <0x007f0000 0x00010000>; /* 64KB */
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};
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};
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};
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@ -148,26 +148,6 @@ rtc@10300 {
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interrupts = <50>;
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};
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spi0: spi@10600 {
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reg = <0x10600 0x28>;
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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interrupts = <30>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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spi1: spi@10680 {
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reg = <0x10680 0x28>;
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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interrupts = <92>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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i2c0: i2c@11000 {
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compatible = "marvell,mv64xxx-i2c";
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#address-cells = <1>;
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@ -320,6 +300,42 @@ mvsdio@d4000 {
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status = "disabled";
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};
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};
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spi0: spi@10600 {
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reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
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<MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
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<MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
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<MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
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<MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
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<MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
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<MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
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<MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
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<MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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interrupts = <30>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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spi1: spi@10680 {
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reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x28>, /* control */
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<MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */
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<MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
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<MBUS_ID(0x01, 0x9a) 0 0xffffffff>, /* CS2 */
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<MBUS_ID(0x01, 0xda) 0 0xffffffff>, /* CS3 */
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<MBUS_ID(0x01, 0x1b) 0 0xffffffff>, /* CS4 */
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<MBUS_ID(0x01, 0x5b) 0 0xffffffff>, /* CS5 */
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<MBUS_ID(0x01, 0x9b) 0 0xffffffff>, /* CS6 */
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<MBUS_ID(0x01, 0xdb) 0 0xffffffff>; /* CS7 */
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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interrupts = <92>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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};
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clocks {
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|
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@ -134,24 +134,6 @@ L2: l2-cache {
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wt-override;
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};
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/*
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* Default SPI pinctrl setting, can be overwritten on
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* board level if a different configuration is used.
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*/
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spi0: spi@10600 {
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compatible = "marvell,armada-370-spi",
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"marvell,orion-spi";
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pinctrl-0 = <&spi0_pins1>;
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pinctrl-names = "default";
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};
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spi1: spi@10680 {
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compatible = "marvell,armada-370-spi",
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"marvell,orion-spi";
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pinctrl-0 = <&spi1_pins>;
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pinctrl-names = "default";
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||||
};
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i2c0: i2c@11000 {
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reg = <0x11000 0x20>;
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||||
};
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@ -447,3 +429,19 @@ ge1_rgmii_pins: ge1-rgmii-pins {
|
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marvell,function = "ge1";
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* Default SPI pinctrl setting, can be overwritten on
|
||||
* board level if a different configuration is used.
|
||||
*/
|
||||
&spi0 {
|
||||
compatible = "marvell,armada-370-spi", "marvell,orion-spi";
|
||||
pinctrl-0 = <&spi0_pins1>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
compatible = "marvell,armada-370-spi", "marvell,orion-spi";
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
|
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@ -65,20 +65,6 @@ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
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MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
|
||||
|
||||
internal-regs {
|
||||
spi1: spi@10680 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p128", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <54000000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
|
|
@ -155,6 +141,10 @@ ethernet@34000 {
|
|||
bm,pool-short = <3>;
|
||||
};
|
||||
|
||||
usb@58000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON4 */
|
||||
ethernet@70000 {
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -178,15 +168,35 @@ bm@c8000 {
|
|||
|
||||
nfc: flash@d0000 {
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
num-cs = <1>;
|
||||
nand-ecc-strength = <4>;
|
||||
nand-ecc-step-size = <512>;
|
||||
marvell,nand-keep-config;
|
||||
marvell,nand-enable-arbiter;
|
||||
nand-on-flash-bbt;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0x00000000 0x00800000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@800000 {
|
||||
label = "uImage";
|
||||
reg = <0x00800000 0x00400000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@c00000 {
|
||||
label = "Root";
|
||||
reg = <0x00c00000 0x3f400000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb3@f0000 {
|
||||
|
|
@ -239,3 +249,17 @@ reg_xhci0_vbus: xhci0-vbus {
|
|||
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p128", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <54000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -62,11 +62,6 @@ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
|
|||
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
|
||||
|
||||
internal-regs {
|
||||
|
||||
spi@10600 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
|
|
@ -332,3 +327,7 @@ xhci0_vbus_pins: xhci0-vbus-pins {
|
|||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -315,30 +315,6 @@ serial@12100 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
spi@10680 {
|
||||
/*
|
||||
* We don't seem to have the W25Q32 on the
|
||||
* A1 Rev 2.0 boards, so disable SPI.
|
||||
* CS0: W25Q32 (doesn't appear to be present)
|
||||
* CS1:
|
||||
* CS2: mikrobus
|
||||
*/
|
||||
pinctrl-0 = <&spi1_pins
|
||||
&clearfog_spi1_cs_pins
|
||||
&mikro_spi_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "w25q32", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <3000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
usb@58000 {
|
||||
/* CON3, nearest power. */
|
||||
status = "okay";
|
||||
|
|
@ -444,3 +420,27 @@ button_0 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
/*
|
||||
* We don't seem to have the W25Q32 on the
|
||||
* A1 Rev 2.0 boards, so disable SPI.
|
||||
* CS0: W25Q32 (doesn't appear to be present)
|
||||
* CS1:
|
||||
* CS2: mikrobus
|
||||
*/
|
||||
pinctrl-0 = <&spi1_pins
|
||||
&clearfog_spi1_cs_pins
|
||||
&mikro_spi_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "w25q32", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <3000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -70,18 +70,6 @@ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
|
|||
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
|
||||
|
||||
internal-regs {
|
||||
spi@10600 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "w25q32", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
|
@ -201,3 +189,16 @@ pcie@2,0 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "w25q32", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -64,21 +64,6 @@ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
|
|||
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
|
||||
|
||||
internal-regs {
|
||||
spi@10600 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p128", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <50000000>;
|
||||
m25p,fast-read;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
|
|
@ -433,3 +418,18 @@ pca0_pins: pca0_pins {
|
|||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p128", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <50000000>;
|
||||
m25p,fast-read;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -70,18 +70,6 @@ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
|
|||
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
|
||||
|
||||
internal-regs {
|
||||
spi@10600 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p128", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
|
@ -142,3 +130,16 @@ pcie@1,0 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p128", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -170,30 +170,6 @@ gic: interrupt-controller@d000 {
|
|||
<0xc100 0x100>;
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,armada-380-spi",
|
||||
"marvell,orion-spi";
|
||||
reg = <0x10600 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@10680 {
|
||||
compatible = "marvell,armada-380-spi",
|
||||
"marvell,orion-spi";
|
||||
reg = <0x10680 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
reg = <0x11000 0x20>;
|
||||
|
|
@ -287,6 +263,15 @@ spi1_pins: spi-pins-1 {
|
|||
marvell,function = "spi1";
|
||||
};
|
||||
|
||||
nand_pins: nand-pins {
|
||||
marvell,pins = "mpp22", "mpp34", "mpp23",
|
||||
"mpp33", "mpp38", "mpp28",
|
||||
"mpp40", "mpp42", "mpp35",
|
||||
"mpp36", "mpp25", "mpp30",
|
||||
"mpp32";
|
||||
marvell,function = "dev";
|
||||
};
|
||||
|
||||
uart0_pins: uart-pins-0 {
|
||||
marvell,pins = "mpp0", "mpp1";
|
||||
marvell,function = "ua0";
|
||||
|
|
@ -649,6 +634,30 @@ bm_bppi: bm-bppi {
|
|||
no-memory-wc;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,armada-380-spi",
|
||||
"marvell,orion-spi";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@10680 {
|
||||
compatible = "marvell,armada-380-spi",
|
||||
"marvell,orion-spi";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
|
|
|
|||
175
arch/arm/boot/dts/armada-390-db.dts
Normal file
175
arch/arm/boot/dts/armada-390-db.dts
Normal file
|
|
@ -0,0 +1,175 @@
|
|||
/*
|
||||
* Device Tree file for Marvell Armada 390 Development Board
|
||||
* (DB-88F6920)
|
||||
*
|
||||
* Copyright (C) 2016 Marvell
|
||||
*
|
||||
* Grzegorz Jaszczyk <jaz@semihalf.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "armada-390.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 390 Development Board";
|
||||
compatible = "marvell,a390-db", "marvell,armada390";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x80000000>; /* 2 GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
|
||||
|
||||
internal-regs {
|
||||
i2c@11000 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
/* CON104 */
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON97 */
|
||||
usb@58000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
flash@d0000 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
num-cs = <1>;
|
||||
marvell,nand-keep-config;
|
||||
marvell,nand-enable-arbiter;
|
||||
nand-on-flash-bbt;
|
||||
nand-ecc-strength = <8>;
|
||||
nand-ecc-step-size = <512>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0 0x800000>;
|
||||
};
|
||||
partition@800000 {
|
||||
label = "Linux";
|
||||
reg = <0x800000 0x800000>;
|
||||
};
|
||||
partition@1000000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x1000000 0x3f000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* CON98 */
|
||||
usb3@f8000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/* CON30 */
|
||||
pcie@1,0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON44 */
|
||||
pcie@2,0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON61 */
|
||||
pcie@3,0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
spi-flash@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13",
|
||||
"jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0 0x400000>;
|
||||
};
|
||||
partition@400000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x400000 0xc00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -47,6 +47,8 @@
|
|||
#include "armada-39x.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "marvell,armada390";
|
||||
|
||||
soc {
|
||||
internal-regs {
|
||||
pinctrl@18000 {
|
||||
|
|
@ -54,4 +56,5 @@ pinctrl@18000 {
|
|||
reg = <0x18000 0x20>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
163
arch/arm/boot/dts/armada-395-gp.dts
Normal file
163
arch/arm/boot/dts/armada-395-gp.dts
Normal file
|
|
@ -0,0 +1,163 @@
|
|||
/*
|
||||
* Device Tree file for Marvell Armada 395 GP board
|
||||
*
|
||||
* Copyright (C) 2016 Marvell
|
||||
*
|
||||
* Grzegorz Jaszczyk <jaz@semihalf.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "armada-395.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 395 GP Board";
|
||||
compatible = "marvell,a395-gp", "marvell,armada395",
|
||||
"marvell,armada390";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x40000000>; /* 1 GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
|
||||
|
||||
internal-regs {
|
||||
i2c@11000 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
eeprom@57 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x57>;
|
||||
};
|
||||
};
|
||||
|
||||
serial@12000 {
|
||||
/*
|
||||
* Exported on the micro USB connector CON17
|
||||
* through an FTDI
|
||||
*/
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON1 */
|
||||
usb@58000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON2 */
|
||||
sata@a8000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
flash@d0000 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
num-cs = <1>;
|
||||
marvell,nand-keep-config;
|
||||
marvell,nand-enable-arbiter;
|
||||
nand-on-flash-bbt;
|
||||
nand-ecc-strength = <4>;
|
||||
nand-ecc-step-size = <512>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0x00000000 0x00600000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@800000 {
|
||||
label = "uImage";
|
||||
reg = <0x00600000 0x00400000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@1000000 {
|
||||
label = "Root";
|
||||
reg = <0x00a00000 0x3f600000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* CON18 */
|
||||
sdhci@d8000 {
|
||||
clock-frequency = <200000000>;
|
||||
broken-cd;
|
||||
wp-inverted;
|
||||
bus-width = <8>;
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
};
|
||||
|
||||
/* CON4 */
|
||||
usb3@f0000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* The two PCIe units are accessible through
|
||||
* mini PCIe slot on the board.
|
||||
*/
|
||||
|
||||
/* CON7 */
|
||||
pcie@2,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON8 */
|
||||
pcie@4,0 {
|
||||
/* Port 3, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
76
arch/arm/boot/dts/armada-395.dtsi
Normal file
76
arch/arm/boot/dts/armada-395.dtsi
Normal file
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada 395 SoC.
|
||||
*
|
||||
* Copyright (C) 2016 Marvell
|
||||
*
|
||||
* Grzegorz Jaszczyk <jaz@semihalf.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "armada-39x.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "marvell,armada395", "marvell,armada390";
|
||||
|
||||
soc {
|
||||
internal-regs {
|
||||
pinctrl@18000 {
|
||||
compatible = "marvell,mv88f6925-pinctrl";
|
||||
reg = <0x18000 0x20>;
|
||||
};
|
||||
|
||||
sata@a8000 {
|
||||
compatible = "marvell,armada-380-ahci";
|
||||
reg = <0xa8000 0x2000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3@f0000 {
|
||||
compatible = "marvell,armada-380-xhci";
|
||||
reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -65,30 +65,6 @@ soc {
|
|||
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
|
||||
|
||||
internal-regs {
|
||||
spi@10680 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "n25q128a13", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <108000000>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0 0x400000>;
|
||||
};
|
||||
|
||||
partition@400000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x400000 0x1000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -108,6 +84,10 @@ serial@12100 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
usb@58000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
flash@d0000 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
|
|
@ -132,6 +112,10 @@ partition@1000000 {
|
|||
reg = <0x1000000 0x3f000000>;
|
||||
};
|
||||
};
|
||||
|
||||
usb3@f8000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
|
|
@ -151,3 +135,27 @@ pcie@3,0 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "n25q128a13", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <108000000>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0 0x400000>;
|
||||
};
|
||||
|
||||
partition@400000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x400000 0x1000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@
|
|||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "armada-39x.dtsi"
|
||||
#include "armada-395.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "marvell,armada398", "marvell,armada390";
|
||||
|
|
@ -55,6 +55,14 @@ pinctrl@18000 {
|
|||
compatible = "marvell,mv88f6928-pinctrl";
|
||||
reg = <0x18000 0x20>;
|
||||
};
|
||||
|
||||
sata@e0000 {
|
||||
compatible = "marvell,armada-380-ahci";
|
||||
reg = <0xe0000 0x2000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 30>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -55,6 +55,8 @@ / {
|
|||
compatible = "marvell,armada390";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
|
|
@ -78,6 +80,11 @@ cpu@1 {
|
|||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts-extended = <&mpic 3>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
|
||||
"simple-bus";
|
||||
|
|
@ -131,30 +138,6 @@ gic: interrupt-controller@d000 {
|
|||
<0xc100 0x100>;
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,armada-390-spi",
|
||||
"marvell,orion-spi";
|
||||
reg = <0x10600 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@10680 {
|
||||
compatible = "marvell,armada-390-spi",
|
||||
"marvell,orion-spi";
|
||||
reg = <0x10680 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
reg = <0x11000 0x20>;
|
||||
|
|
@ -269,6 +252,34 @@ nand_pins: nand-pins {
|
|||
};
|
||||
};
|
||||
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
ngpios = <28>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
system-controller@18200 {
|
||||
compatible = "marvell,armada-390-system-controller",
|
||||
"marvell,armada-370-xp-system-controller";
|
||||
|
|
@ -317,11 +328,29 @@ timer@20300 {
|
|||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
watchdog@20300 {
|
||||
compatible = "marvell,armada-380-wdt";
|
||||
reg = <0x20300 0x34>, <0x20704 0x4>,
|
||||
<0x18260 0x4>;
|
||||
clocks = <&coreclk 2>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
cpurst@20800 {
|
||||
compatible = "marvell,armada-370-cpu-reset";
|
||||
reg = <0x20800 0x10>;
|
||||
};
|
||||
|
||||
mpcore-soc-ctrl@20d20 {
|
||||
compatible = "marvell,armada-380-mpcore-soc-ctrl";
|
||||
reg = <0x20d20 0x6c>;
|
||||
};
|
||||
|
||||
coherency-fabric@21010 {
|
||||
compatible = "marvell,armada-380-coherency-fabric";
|
||||
reg = <0x21010 0x1c>;
|
||||
};
|
||||
|
||||
pmsu@22000 {
|
||||
compatible = "marvell,armada-390-pmsu",
|
||||
"marvell,armada-380-pmsu";
|
||||
|
|
@ -368,6 +397,13 @@ xor11 {
|
|||
};
|
||||
};
|
||||
|
||||
rtc@a3800 {
|
||||
compatible = "marvell,armada-380-rtc";
|
||||
reg = <0xa3800 0x20>, <0x184a0 0x0c>;
|
||||
reg-names = "rtc", "rtc-soc";
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
flash@d0000 {
|
||||
compatible = "marvell,armada370-nand";
|
||||
reg = <0xd0000 0x54>;
|
||||
|
|
@ -380,7 +416,10 @@ flash@d0000 {
|
|||
|
||||
sdhci@d8000 {
|
||||
compatible = "marvell,armada-380-sdhci";
|
||||
reg = <0xd8000 0x1000>, <0xdc000 0x100>;
|
||||
reg-names = "sdhci", "mbus", "conf-sdio3";
|
||||
reg = <0xd8000 0x1000>,
|
||||
<0xdc000 0x100>,
|
||||
<0x18454 0x4>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 17>;
|
||||
mrvl,clk-delay-cycles = <0x1F>;
|
||||
|
|
@ -395,6 +434,12 @@ coredivclk: clock@e4250 {
|
|||
clocks = <&mainpll>;
|
||||
clock-output-names = "nand";
|
||||
};
|
||||
|
||||
thermal@e8078 {
|
||||
compatible = "marvell,armada380-thermal";
|
||||
reg = <0xe4078 0x4>, <0xe4074 0x4>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
|
|
@ -501,6 +546,30 @@ pcie@4,0 {
|
|||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,armada-390-spi",
|
||||
"marvell,orion-spi";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@10680 {
|
||||
compatible = "marvell,armada-390-spi",
|
||||
"marvell,orion-spi";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
|
|
@ -510,5 +579,12 @@ mainpll: mainpll {
|
|||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000000>;
|
||||
};
|
||||
|
||||
/* 25 MHz reference crystal */
|
||||
refclk: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -135,18 +135,6 @@ ethernet@74000 {
|
|||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -179,3 +167,15 @@ phy_int_pin: phy-int-pin {
|
|||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -231,18 +231,6 @@ usb@52000 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "m25p64", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
};
|
||||
|
||||
nand@d0000 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
|
|
@ -277,3 +265,15 @@ bm-bppi {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "m25p64", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -232,18 +232,6 @@ usb@51000 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bm@c0000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -262,3 +250,15 @@ bm-bppi {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -279,18 +279,6 @@ partition@180000 {
|
|||
reg = <0x180000 0x780000>; /* 7.5MB */
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "everspin,mr25h256";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <40000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -398,3 +386,15 @@ gpio_fan_pin: gpio-fan-pin {
|
|||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "everspin,mr25h256";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <40000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -110,62 +110,6 @@ rtc@10300 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q064", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <20000000>;
|
||||
|
||||
/*
|
||||
* Warning!
|
||||
*
|
||||
* Synology u-boot uses its compiled-in environment
|
||||
* and it seems Synology did not care to change u-boot
|
||||
* default configuration in order to allow saving a
|
||||
* modified environment at a sensible location. So,
|
||||
* if you do a 'saveenv' under u-boot, your modified
|
||||
* environment will be saved at 1MB after the start
|
||||
* of the flash, i.e. in the middle of the uImage.
|
||||
* For that reason, it is strongly advised not to
|
||||
* change the default environment, unless you know
|
||||
* what you are doing.
|
||||
*/
|
||||
partition@00000000 { /* u-boot */
|
||||
label = "RedBoot";
|
||||
reg = <0x00000000 0x000d0000>; /* 832KB */
|
||||
};
|
||||
|
||||
partition@000c0000 { /* uImage */
|
||||
label = "zImage";
|
||||
reg = <0x000d0000 0x002d0000>; /* 2880KB */
|
||||
};
|
||||
|
||||
partition@003a0000 { /* uInitramfs */
|
||||
label = "rd.gz";
|
||||
reg = <0x003a0000 0x00430000>; /* 4250KB */
|
||||
};
|
||||
|
||||
partition@007d0000 { /* MAC address and serial number */
|
||||
label = "vendor";
|
||||
reg = <0x007d0000 0x00010000>; /* 64KB */
|
||||
};
|
||||
|
||||
partition@007e0000 {
|
||||
label = "RedBoot config";
|
||||
reg = <0x007e0000 0x00010000>; /* 64KB */
|
||||
};
|
||||
|
||||
partition@007f0000 {
|
||||
label = "FIS directory";
|
||||
reg = <0x007f0000 0x00010000>; /* 64KB */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
|
@ -362,3 +306,59 @@ fan2_alarm_pin: fan2-alarm-pin {
|
|||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q064", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <20000000>;
|
||||
|
||||
/*
|
||||
* Warning!
|
||||
*
|
||||
* Synology u-boot uses its compiled-in environment
|
||||
* and it seems Synology did not care to change u-boot
|
||||
* default configuration in order to allow saving a
|
||||
* modified environment at a sensible location. So,
|
||||
* if you do a 'saveenv' under u-boot, your modified
|
||||
* environment will be saved at 1MB after the start
|
||||
* of the flash, i.e. in the middle of the uImage.
|
||||
* For that reason, it is strongly advised not to
|
||||
* change the default environment, unless you know
|
||||
* what you are doing.
|
||||
*/
|
||||
partition@00000000 { /* u-boot */
|
||||
label = "RedBoot";
|
||||
reg = <0x00000000 0x000d0000>; /* 832KB */
|
||||
};
|
||||
|
||||
partition@000c0000 { /* uImage */
|
||||
label = "zImage";
|
||||
reg = <0x000d0000 0x002d0000>; /* 2880KB */
|
||||
};
|
||||
|
||||
partition@003a0000 { /* uInitramfs */
|
||||
label = "rd.gz";
|
||||
reg = <0x003a0000 0x00430000>; /* 4250KB */
|
||||
};
|
||||
|
||||
partition@007d0000 { /* MAC address and serial number */
|
||||
label = "vendor";
|
||||
reg = <0x007d0000 0x00010000>; /* 64KB */
|
||||
};
|
||||
|
||||
partition@007e0000 {
|
||||
label = "RedBoot config";
|
||||
reg = <0x007e0000 0x00010000>; /* 64KB */
|
||||
};
|
||||
|
||||
partition@007f0000 {
|
||||
label = "FIS directory";
|
||||
reg = <0x007f0000 0x00010000>; /* 64KB */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -84,19 +84,6 @@ L2: l2-cache {
|
|||
wt-override;
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,armada-xp-spi",
|
||||
"marvell,orion-spi";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
spi1: spi@10680 {
|
||||
compatible = "marvell,armada-xp-spi",
|
||||
"marvell,orion-spi";
|
||||
};
|
||||
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
|
||||
reg = <0x11000 0x100>;
|
||||
|
|
@ -362,6 +349,12 @@ spi0_pins: spi0-pins {
|
|||
marvell,function = "spi0";
|
||||
};
|
||||
|
||||
spi1_pins: spi1-pins {
|
||||
marvell,pins = "mpp13", "mpp14",
|
||||
"mpp16", "mpp17";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
marvell,pins = "mpp42", "mpp43";
|
||||
marvell,function = "uart2";
|
||||
|
|
@ -372,3 +365,15 @@ uart3_pins: uart3-pins {
|
|||
marvell,function = "uart3";
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ s35390a: s35390a@30 {
|
|||
};
|
||||
|
||||
pinctrl: pin-controller@10000 {
|
||||
pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>;
|
||||
pinctrl-0 = <&pmx_dip_switches>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
pmx_uart0: pmx-uart0 {
|
||||
|
|
@ -174,3 +174,10 @@ ethernet0-port@0 {
|
|||
phy-handle = <ðphy0>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&pmx_gpio_header>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue