s390: convert ".insn" encoding to instruction names
With z10 as minimum supported machine generation many ".insn" encodings could be now converted to instruction names. There are couple of exceptions - stfle is used from the als code built for z900 and cannot be converted - few ".insn" directives encode unsupported instruction formats The generated code is identical before/after this change. Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
This commit is contained in:
Vasily Gorbik
parent
10bc15ba3a
commit
731efc9613
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@ -312,7 +312,7 @@ ENTRY(chacha20_vx_4x)
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VPERM XC0,XC0,XC0,BEPERM
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VPERM XD0,XD0,XD0,BEPERM
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.insn rilu,0xc20e00000000,LEN,0x40 # clgfi LEN,0x40
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clgfi LEN,0x40
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jl .Ltail_4x
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VLM XT0,XT3,0,INP,0
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@ -339,7 +339,7 @@ ENTRY(chacha20_vx_4x)
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VPERM XC0,XC0,XC0,BEPERM
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VPERM XD0,XD0,XD0,BEPERM
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.insn rilu,0xc20e00000000,LEN,0x40 # clgfi LEN,0x40
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clgfi LEN,0x40
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jl .Ltail_4x
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VLM XT0,XT3,0,INP,0
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@ -366,7 +366,7 @@ ENTRY(chacha20_vx_4x)
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VPERM XC0,XC0,XC0,BEPERM
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VPERM XD0,XD0,XD0,BEPERM
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.insn rilu,0xc20e00000000,LEN,0x40 # clgfi LEN,0x40
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clgfi LEN,0x40
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jl .Ltail_4x
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VLM XT0,XT3,0,INP,0
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@ -472,7 +472,7 @@ ENDPROC(chacha20_vx_4x)
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#define T3 %v30
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ENTRY(chacha20_vx)
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.insn rilu,0xc20e00000000,LEN,256 # clgfi LEN,256
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clgfi LEN,256
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jle chacha20_vx_4x
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stmg %r6,%r7,6*8(SP)
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@ -725,7 +725,7 @@ ENTRY(chacha20_vx)
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VPERM C0,C0,C0,BEPERM
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VPERM D0,D0,D0,BEPERM
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.insn rilu,0xc20e00000000,LEN,0x40 # clgfi LEN,0x40
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clgfi LEN,0x40
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jl .Ltail_vx
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VAF D2,D2,T2 # +K[3]+2
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@ -754,7 +754,7 @@ ENTRY(chacha20_vx)
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VPERM C0,C1,C1,BEPERM
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VPERM D0,D1,D1,BEPERM
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.insn rilu,0xc20e00000000,LEN,0x40 # clgfi LEN,0x40
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clgfi LEN,0x40
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jl .Ltail_vx
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VLM A1,D1,0,INP,0
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@ -780,7 +780,7 @@ ENTRY(chacha20_vx)
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VPERM C0,C2,C2,BEPERM
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VPERM D0,D2,D2,BEPERM
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.insn rilu,0xc20e00000000,LEN,0x40 # clgfi LEN,0x40
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clgfi LEN,0x40
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jl .Ltail_vx
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VLM A1,D1,0,INP,0
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@ -807,7 +807,7 @@ ENTRY(chacha20_vx)
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VPERM C0,C3,C3,BEPERM
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VPERM D0,D3,D3,BEPERM
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.insn rilu,0xc20e00000000,LEN,0x40 # clgfi LEN,0x40
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clgfi LEN,0x40
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jl .Ltail_vx
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VAF D3,D2,T1 # K[3]+4
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@ -837,7 +837,7 @@ ENTRY(chacha20_vx)
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VPERM C0,C4,C4,BEPERM
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VPERM D0,D4,D4,BEPERM
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.insn rilu,0xc20e00000000,LEN,0x40 # clgfi LEN,0x40
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clgfi LEN,0x40
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jl .Ltail_vx
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VLM A1,D1,0,INP,0
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@ -864,7 +864,7 @@ ENTRY(chacha20_vx)
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VPERM C0,C5,C5,BEPERM
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VPERM D0,D5,D5,BEPERM
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.insn rilu,0xc20e00000000,LEN,0x40 # clgfi LEN,0x40
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clgfi LEN,0x40
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jl .Ltail_vx
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VLM A1,D1,0,INP,0
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@ -160,7 +160,7 @@ struct hws_trailer_entry {
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/* Load program parameter */
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static inline void lpp(void *pp)
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{
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asm volatile(".insn s,0xb2800000,0(%0)\n":: "a" (pp) : "memory");
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asm volatile("lpp 0(%0)\n" :: "a" (pp) : "memory");
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}
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/* Query counter information */
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@ -169,7 +169,7 @@ static inline int qctri(struct cpumf_ctr_info *info)
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int rc = -EINVAL;
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asm volatile (
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"0: .insn s,0xb28e0000,%1\n"
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"0: qctri %1\n"
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"1: lhi %0,0\n"
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"2:\n"
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EX_TABLE(1b, 2b)
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@ -183,7 +183,7 @@ static inline int lcctl(u64 ctl)
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int cc;
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asm volatile (
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" .insn s,0xb2840000,%1\n"
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" lcctl %1\n"
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" ipm %0\n"
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" srl %0,28\n"
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: "=d" (cc) : "Q" (ctl) : "cc");
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@ -197,7 +197,7 @@ static inline int __ecctr(u64 ctr, u64 *content)
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int cc;
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asm volatile (
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" .insn rre,0xb2e40000,%0,%2\n"
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" ecctr %0,%2\n"
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" ipm %1\n"
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" srl %1,28\n"
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: "=d" (_content), "=d" (cc) : "d" (ctr) : "cc");
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@ -247,7 +247,7 @@ static inline int qsi(struct hws_qsi_info_block *info)
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int cc = 1;
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asm volatile(
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"0: .insn s,0xb2860000,%1\n"
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"0: qsi %1\n"
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"1: lhi %0,0\n"
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"2:\n"
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EX_TABLE(0b, 2b) EX_TABLE(1b, 2b)
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@ -262,7 +262,7 @@ static inline int lsctl(struct hws_lsctl_request_block *req)
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cc = 1;
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asm volatile(
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"0: .insn s,0xb2870000,0(%1)\n"
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"0: lsctl 0(%1)\n"
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"1: ipm %0\n"
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" srl %0,28\n"
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"2:\n"
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@ -600,7 +600,7 @@ static inline void cspg(unsigned long *ptr, unsigned long old, unsigned long new
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unsigned long address = (unsigned long)ptr | 1;
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asm volatile(
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" .insn rre,0xb98a0000,%[r1],%[address]"
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" cspg %[r1],%[address]"
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: [r1] "+&d" (r1.pair), "+m" (*ptr)
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: [address] "d" (address)
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: "cc");
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@ -1052,7 +1052,7 @@ static __always_inline void __ptep_ipte(unsigned long address, pte_t *ptep,
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if (__builtin_constant_p(opt) && opt == 0) {
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/* Invalidation + TLB flush for the pte */
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asm volatile(
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" .insn rrf,0xb2210000,%[r1],%[r2],0,%[m4]"
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" ipte %[r1],%[r2],0,%[m4]"
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: "+m" (*ptep) : [r1] "a" (pto), [r2] "a" (address),
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[m4] "i" (local));
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return;
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@ -1061,7 +1061,7 @@ static __always_inline void __ptep_ipte(unsigned long address, pte_t *ptep,
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/* Invalidate ptes with options + TLB flush of the ptes */
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opt = opt | (asce & _ASCE_ORIGIN);
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asm volatile(
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" .insn rrf,0xb2210000,%[r1],%[r2],%[r3],%[m4]"
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" ipte %[r1],%[r2],%[r3],%[m4]"
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: [r2] "+a" (address), [r3] "+a" (opt)
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: [r1] "a" (pto), [m4] "i" (local) : "memory");
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}
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@ -1074,7 +1074,7 @@ static __always_inline void __ptep_ipte_range(unsigned long address, int nr,
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/* Invalidate a range of ptes + TLB flush of the ptes */
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do {
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asm volatile(
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" .insn rrf,0xb2210000,%[r1],%[r2],%[r3],%[m4]"
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" ipte %[r1],%[r2],%[r3],%[m4]"
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: [r2] "+a" (address), [r3] "+a" (nr)
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: [r1] "a" (pto), [m4] "i" (local) : "memory");
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} while (nr != 255);
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@ -1535,7 +1535,7 @@ static __always_inline void __pmdp_idte(unsigned long addr, pmd_t *pmdp,
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if (__builtin_constant_p(opt) && opt == 0) {
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/* flush without guest asce */
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asm volatile(
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" .insn rrf,0xb98e0000,%[r1],%[r2],0,%[m4]"
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" idte %[r1],0,%[r2],%[m4]"
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: "+m" (*pmdp)
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: [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK)),
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[m4] "i" (local)
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@ -1543,7 +1543,7 @@ static __always_inline void __pmdp_idte(unsigned long addr, pmd_t *pmdp,
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} else {
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/* flush with guest asce */
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asm volatile(
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" .insn rrf,0xb98e0000,%[r1],%[r2],%[r3],%[m4]"
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" idte %[r1],%[r3],%[r2],%[m4]"
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: "+m" (*pmdp)
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: [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK) | opt),
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[r3] "a" (asce), [m4] "i" (local)
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@ -1562,7 +1562,7 @@ static __always_inline void __pudp_idte(unsigned long addr, pud_t *pudp,
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if (__builtin_constant_p(opt) && opt == 0) {
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/* flush without guest asce */
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asm volatile(
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" .insn rrf,0xb98e0000,%[r1],%[r2],0,%[m4]"
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" idte %[r1],0,%[r2],%[m4]"
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: "+m" (*pudp)
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: [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK)),
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[m4] "i" (local)
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@ -1570,7 +1570,7 @@ static __always_inline void __pudp_idte(unsigned long addr, pud_t *pudp,
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} else {
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/* flush with guest asce */
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asm volatile(
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" .insn rrf,0xb98e0000,%[r1],%[r2],%[r3],%[m4]"
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" idte %[r1],%[r3],%[r2],%[m4]"
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: "+m" (*pudp)
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: [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK) | opt),
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[r3] "a" (asce), [m4] "i" (local)
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@ -225,8 +225,7 @@ static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
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{
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unsigned long val;
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asm volatile(".insn rsy,0xeb000000004c,%0,0,0(%1)" /* ecag */
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: "=d" (val) : "a" (asi << 8 | parm));
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asm volatile("ecag %0,0,0(%1)" : "=d" (val) : "a" (asi << 8 | parm));
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return val;
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}
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@ -148,7 +148,7 @@ struct ptff_qui {
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asm volatile( \
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" lgr 0,%[reg0]\n" \
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" lgr 1,%[reg1]\n" \
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" .insn e,0x0104\n" \
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" ptff\n" \
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" ipm %[rc]\n" \
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" srl %[rc],28\n" \
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: [rc] "=&d" (rc), "+m" (*(struct addrtype *)reg1) \
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@ -25,9 +25,7 @@ static inline void __tlb_flush_idte(unsigned long asce)
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if (MACHINE_HAS_TLB_GUEST)
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opt |= IDTE_GUEST_ASCE;
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/* Global TLB flush for the mm */
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asm volatile(
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" .insn rrf,0xb98e0000,0,%0,%1,0"
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: : "a" (opt), "a" (asce) : "cc");
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asm volatile("idte 0,%1,%0" : : "a" (opt), "a" (asce) : "cc");
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}
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/*
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@ -226,7 +226,7 @@ ENTRY(__switch_to)
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aghi %r3,__TASK_pid
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mvc __LC_CURRENT_PID(4,%r0),0(%r3) # store pid of next
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lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task
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ALTERNATIVE "", ".insn s,0xb2800000,_LPP_OFFSET", 40
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ALTERNATIVE "", "lpp _LPP_OFFSET", 40
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BR_EX %r14
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ENDPROC(__switch_to)
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@ -648,7 +648,7 @@ ENTRY(mcck_int_handler)
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ENDPROC(mcck_int_handler)
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ENTRY(restart_int_handler)
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ALTERNATIVE "", ".insn s,0xb2800000,_LPP_OFFSET", 40
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ALTERNATIVE "", "lpp _LPP_OFFSET", 40
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stg %r15,__LC_SAVE_AREA_RESTART
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TSTMSK __LC_RESTART_FLAGS,RESTART_FLAG_CTLREGS,4
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jz 0f
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@ -62,7 +62,7 @@ asm(
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" .align 16\n"
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"ftrace_shared_hotpatch_trampoline_exrl:\n"
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" lmg %r0,%r1,2(%r1)\n"
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" .insn ril,0xc60000000000,%r0,0f\n" /* exrl */
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" exrl %r0,0f\n"
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" j .\n"
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"0: br %r1\n"
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"ftrace_shared_hotpatch_trampoline_exrl_end:\n"
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@ -45,7 +45,7 @@ static unsigned long raw_copy_from_user_key(void *to, const void __user *from,
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tmp1 = -4096UL;
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asm volatile(
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" lr 0,%[spec]\n"
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"0: .insn ss,0xc80000000000,0(%0,%2),0(%1),0\n"
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"0: mvcos 0(%2),0(%1),%0\n"
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"6: jz 4f\n"
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"1: algr %0,%3\n"
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" slgr %1,%3\n"
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@ -56,7 +56,7 @@ static unsigned long raw_copy_from_user_key(void *to, const void __user *from,
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" slgr %4,%1\n"
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" clgr %0,%4\n" /* copy crosses next page boundary? */
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" jnh 5f\n"
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"3: .insn ss,0xc80000000000,0(%4,%2),0(%1),0\n"
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"3: mvcos 0(%2),0(%1),%4\n"
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"7: slgr %0,%4\n"
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" j 5f\n"
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"4: slgr %0,%0\n"
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@ -104,7 +104,7 @@ static unsigned long raw_copy_to_user_key(void __user *to, const void *from,
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tmp1 = -4096UL;
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asm volatile(
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" lr 0,%[spec]\n"
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"0: .insn ss,0xc80000000000,0(%0,%1),0(%2),0\n"
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"0: mvcos 0(%1),0(%2),%0\n"
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"6: jz 4f\n"
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"1: algr %0,%3\n"
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" slgr %1,%3\n"
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@ -115,7 +115,7 @@ static unsigned long raw_copy_to_user_key(void __user *to, const void *from,
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" slgr %4,%1\n"
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" clgr %0,%4\n" /* copy crosses next page boundary? */
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" jnh 5f\n"
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"3: .insn ss,0xc80000000000,0(%4,%1),0(%2),0\n"
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"3: mvcos 0(%1),0(%2),%4\n"
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"7: slgr %0,%4\n"
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" j 5f\n"
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"4: slgr %0,%0\n"
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@ -155,7 +155,7 @@ unsigned long __clear_user(void __user *to, unsigned long size)
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tmp1 = -4096UL;
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asm volatile(
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" lr 0,%[spec]\n"
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"0: .insn ss,0xc80000000000,0(%0,%1),0(%4),0\n"
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"0: mvcos 0(%1),0(%4),%0\n"
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" jz 4f\n"
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"1: algr %0,%2\n"
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" slgr %1,%2\n"
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@ -165,7 +165,7 @@ unsigned long __clear_user(void __user *to, unsigned long size)
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" slgr %3,%1\n"
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" clgr %0,%3\n" /* copy crosses next page boundary? */
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" jnh 5f\n"
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"3: .insn ss,0xc80000000000,0(%3,%1),0(%4),0\n"
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"3: mvcos 0(%1),0(%4),%3\n"
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" slgr %0,%3\n"
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" j 5f\n"
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"4: slgr %0,%0\n"
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@ -1278,7 +1278,7 @@ static int gmap_protect_rmap(struct gmap *sg, unsigned long raddr,
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static inline void gmap_idte_one(unsigned long asce, unsigned long vaddr)
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{
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asm volatile(
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" .insn rrf,0xb98e0000,%0,%1,0,0"
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" idte %0,0,%1"
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: : "a" (asce), "a" (vaddr) : "cc", "memory");
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}
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