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iio: adc: mcp3911: add support for the whole MCP39xx family
Microchip does have many similar chips, add support for those. The new supported chips are: - microchip,mcp3910 - microchip,mcp3912 - microchip,mcp3913 - microchip,mcp3914 - microchip,mcp3918 - microchip,mcp3919 Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230822192259.1125792-7-marcus.folkesson@gmail.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Marcus Folkesson
Jonathan Cameron
parent
593d73629a
commit
732ad34260
2 changed files with 415 additions and 57 deletions
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@ -785,8 +785,10 @@ config MCP3911
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select IIO_BUFFER
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select IIO_TRIGGERED_BUFFER
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help
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Say yes here to build support for Microchip Technology's MCP3911
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analog to digital converter.
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Say yes here to build support for one of the following
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Microchip Technology's analog to digital converters:
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MCP3910, MCP3911, MCP3912, MCP3913, MCP3914,
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MCP3918 and MCP3919.
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This driver can also be built as a module. If so, the module will be
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called mcp3911.
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@ -61,12 +61,56 @@
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#define MCP3911_REG_WRITE(reg, id) ((((reg) << 1) | ((id) << 6) | (0 << 0)) & 0xff)
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#define MCP3911_REG_MASK GENMASK(4, 1)
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#define MCP3911_NUM_CHANNELS 2
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#define MCP3911_NUM_SCALES 6
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/* Registers compatible with MCP3910 */
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#define MCP3910_REG_STATUSCOM 0x0c
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#define MCP3910_STATUSCOM_READ GENMASK(23, 22)
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#define MCP3910_STATUSCOM_DRHIZ BIT(20)
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#define MCP3910_REG_GAIN 0x0b
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#define MCP3910_REG_CONFIG0 0x0d
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#define MCP3910_CONFIG0_EN_OFFCAL BIT(23)
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#define MCP3910_CONFIG0_OSR GENMASK(15, 13)
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#define MCP3910_REG_CONFIG1 0x0e
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#define MCP3910_CONFIG1_CLKEXT BIT(6)
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#define MCP3910_CONFIG1_VREFEXT BIT(7)
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#define MCP3910_REG_OFFCAL_CH0 0x0f
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#define MCP3910_OFFCAL(ch) (MCP3910_REG_OFFCAL_CH0 + (ch) * 6)
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/* Maximal number of channels used by the MCP39XX family */
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#define MCP39XX_MAX_NUM_CHANNELS 8
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static const int mcp3911_osr_table[] = { 32, 64, 128, 256, 512, 1024, 2048, 4096 };
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static u32 mcp3911_scale_table[MCP3911_NUM_SCALES][2];
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enum mcp3911_id {
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MCP3910,
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MCP3911,
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MCP3912,
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MCP3913,
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MCP3914,
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MCP3918,
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MCP3919,
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};
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struct mcp3911;
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struct mcp3911_chip_info {
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const struct iio_chan_spec *channels;
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unsigned int num_channels;
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int (*config)(struct mcp3911 *adc);
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int (*get_osr)(struct mcp3911 *adc, u32 *val);
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int (*set_osr)(struct mcp3911 *adc, u32 val);
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int (*enable_offset)(struct mcp3911 *adc, bool enable);
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int (*get_offset)(struct mcp3911 *adc, int channel, int *val);
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int (*set_offset)(struct mcp3911 *adc, int channel, int val);
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int (*set_scale)(struct mcp3911 *adc, int channel, u32 val);
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};
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struct mcp3911 {
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struct spi_device *spi;
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struct mutex lock;
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@ -74,14 +118,15 @@ struct mcp3911 {
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struct clk *clki;
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u32 dev_addr;
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struct iio_trigger *trig;
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u32 gain[MCP3911_NUM_CHANNELS];
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u32 gain[MCP39XX_MAX_NUM_CHANNELS];
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const struct mcp3911_chip_info *chip;
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struct {
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u32 channels[MCP3911_NUM_CHANNELS];
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u32 channels[MCP39XX_MAX_NUM_CHANNELS];
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s64 ts __aligned(8);
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} scan;
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u8 tx_buf __aligned(IIO_DMA_MINALIGN);
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u8 rx_buf[MCP3911_NUM_CHANNELS * 3];
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u8 rx_buf[MCP39XX_MAX_NUM_CHANNELS * 3];
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};
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static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len)
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@ -125,6 +170,112 @@ static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask, u32 val, u8 len
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return mcp3911_write(adc, reg, val, len);
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}
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static int mcp3910_enable_offset(struct mcp3911 *adc, bool enable)
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{
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unsigned int mask = MCP3910_CONFIG0_EN_OFFCAL;
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unsigned int value = enable ? mask : 0;
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return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, value, 3);
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}
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static int mcp3910_get_offset(struct mcp3911 *adc, int channel, int *val)
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{
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return mcp3911_read(adc, MCP3910_OFFCAL(channel), val, 3);
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}
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static int mcp3910_set_offset(struct mcp3911 *adc, int channel, int val)
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{
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int ret;
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ret = mcp3911_write(adc, MCP3910_OFFCAL(channel), val, 3);
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if (ret)
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return ret;
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return adc->chip->enable_offset(adc, 1);
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}
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static int mcp3911_enable_offset(struct mcp3911 *adc, bool enable)
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{
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unsigned int mask = MCP3911_STATUSCOM_EN_OFFCAL;
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unsigned int value = enable ? mask : 0;
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return mcp3911_update(adc, MCP3911_REG_STATUSCOM, mask, value, 2);
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}
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static int mcp3911_get_offset(struct mcp3911 *adc, int channel, int *val)
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{
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return mcp3911_read(adc, MCP3911_OFFCAL(channel), val, 3);
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}
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static int mcp3911_set_offset(struct mcp3911 *adc, int channel, int val)
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{
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int ret;
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ret = mcp3911_write(adc, MCP3911_OFFCAL(channel), val, 3);
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if (ret)
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return ret;
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return adc->chip->enable_offset(adc, 1);
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}
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static int mcp3910_get_osr(struct mcp3911 *adc, u32 *val)
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{
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int ret;
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unsigned int osr;
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ret = mcp3911_read(adc, MCP3910_REG_CONFIG0, val, 3);
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if (ret)
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return ret;
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osr = FIELD_GET(MCP3910_CONFIG0_OSR, *val);
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*val = 32 << osr;
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return 0;
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}
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static int mcp3910_set_osr(struct mcp3911 *adc, u32 val)
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{
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unsigned int osr = FIELD_PREP(MCP3910_CONFIG0_OSR, val);
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unsigned int mask = MCP3910_CONFIG0_OSR;
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return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, osr, 3);
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}
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static int mcp3911_set_osr(struct mcp3911 *adc, u32 val)
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{
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unsigned int osr = FIELD_PREP(MCP3911_CONFIG_OSR, val);
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unsigned int mask = MCP3911_CONFIG_OSR;
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return mcp3911_update(adc, MCP3911_REG_CONFIG, mask, osr, 2);
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}
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static int mcp3911_get_osr(struct mcp3911 *adc, u32 *val)
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{
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int ret;
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unsigned int osr;
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ret = mcp3911_read(adc, MCP3911_REG_CONFIG, val, 2);
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if (ret)
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return ret;
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osr = FIELD_GET(MCP3911_CONFIG_OSR, *val);
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*val = 32 << osr;
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return ret;
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}
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static int mcp3910_set_scale(struct mcp3911 *adc, int channel, u32 val)
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{
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return mcp3911_update(adc, MCP3910_REG_GAIN,
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MCP3911_GAIN_MASK(channel),
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MCP3911_GAIN_VAL(channel, val), 3);
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}
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static int mcp3911_set_scale(struct mcp3911 *adc, int channel, u32 val)
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{
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return mcp3911_update(adc, MCP3911_REG_GAIN,
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MCP3911_GAIN_MASK(channel),
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MCP3911_GAIN_VAL(channel, val), 1);
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}
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static int mcp3911_write_raw_get_fmt(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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long mask)
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@ -181,20 +332,18 @@ static int mcp3911_read_raw(struct iio_dev *indio_dev,
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break;
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case IIO_CHAN_INFO_OFFSET:
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ret = mcp3911_read(adc,
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MCP3911_OFFCAL(channel->channel), val, 3);
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ret = adc->chip->get_offset(adc, channel->channel, val);
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if (ret)
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goto out;
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ret = IIO_VAL_INT;
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break;
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case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
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ret = mcp3911_read(adc, MCP3911_REG_CONFIG, val, 2);
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ret = adc->chip->get_osr(adc, val);
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if (ret)
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goto out;
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*val = FIELD_GET(MCP3911_CONFIG_OSR, *val);
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*val = 32 << *val;
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ret = IIO_VAL_INT;
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break;
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@ -225,9 +374,7 @@ static int mcp3911_write_raw(struct iio_dev *indio_dev,
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val2 == mcp3911_scale_table[i][1]) {
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adc->gain[channel->channel] = BIT(i);
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ret = mcp3911_update(adc, MCP3911_REG_GAIN,
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MCP3911_GAIN_MASK(channel->channel),
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MCP3911_GAIN_VAL(channel->channel, i), 1);
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ret = adc->chip->set_scale(adc, channel->channel, i);
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}
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}
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break;
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@ -237,24 +384,13 @@ static int mcp3911_write_raw(struct iio_dev *indio_dev,
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goto out;
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}
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/* Write offset */
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ret = mcp3911_write(adc, MCP3911_OFFCAL(channel->channel), val,
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3);
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if (ret)
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goto out;
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/* Enable offset*/
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ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM,
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MCP3911_STATUSCOM_EN_OFFCAL,
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MCP3911_STATUSCOM_EN_OFFCAL, 2);
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ret = adc->chip->set_offset(adc, channel->channel, val);
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break;
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case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
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for (int i = 0; i < ARRAY_SIZE(mcp3911_osr_table); i++) {
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if (val == mcp3911_osr_table[i]) {
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val = FIELD_PREP(MCP3911_CONFIG_OSR, i);
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ret = mcp3911_update(adc, MCP3911_REG_CONFIG, MCP3911_CONFIG_OSR,
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val, 2);
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ret = adc->chip->set_osr(adc, i);
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break;
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}
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}
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@ -323,12 +459,60 @@ static int mcp3911_calc_scale_table(struct mcp3911 *adc)
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}, \
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}
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static const struct iio_chan_spec mcp3910_channels[] = {
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MCP3911_CHAN(0),
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MCP3911_CHAN(1),
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IIO_CHAN_SOFT_TIMESTAMP(2),
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};
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static const struct iio_chan_spec mcp3911_channels[] = {
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MCP3911_CHAN(0),
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MCP3911_CHAN(1),
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IIO_CHAN_SOFT_TIMESTAMP(2),
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};
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static const struct iio_chan_spec mcp3912_channels[] = {
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MCP3911_CHAN(0),
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MCP3911_CHAN(1),
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MCP3911_CHAN(2),
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MCP3911_CHAN(3),
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IIO_CHAN_SOFT_TIMESTAMP(4),
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};
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static const struct iio_chan_spec mcp3913_channels[] = {
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MCP3911_CHAN(0),
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MCP3911_CHAN(1),
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MCP3911_CHAN(2),
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MCP3911_CHAN(3),
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MCP3911_CHAN(4),
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MCP3911_CHAN(5),
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IIO_CHAN_SOFT_TIMESTAMP(6),
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};
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static const struct iio_chan_spec mcp3914_channels[] = {
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MCP3911_CHAN(0),
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MCP3911_CHAN(1),
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MCP3911_CHAN(2),
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MCP3911_CHAN(3),
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MCP3911_CHAN(4),
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MCP3911_CHAN(5),
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MCP3911_CHAN(6),
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MCP3911_CHAN(7),
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IIO_CHAN_SOFT_TIMESTAMP(8),
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};
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static const struct iio_chan_spec mcp3918_channels[] = {
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MCP3911_CHAN(0),
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IIO_CHAN_SOFT_TIMESTAMP(1),
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};
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static const struct iio_chan_spec mcp3919_channels[] = {
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MCP3911_CHAN(0),
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MCP3911_CHAN(1),
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MCP3911_CHAN(2),
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IIO_CHAN_SOFT_TIMESTAMP(3),
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};
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static irqreturn_t mcp3911_trigger_handler(int irq, void *p)
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{
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struct iio_poll_func *pf = p;
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@ -341,7 +525,7 @@ static irqreturn_t mcp3911_trigger_handler(int irq, void *p)
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.len = 1,
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}, {
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.rx_buf = adc->rx_buf,
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.len = sizeof(adc->rx_buf),
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.len = (adc->chip->num_channels - 1) * 3,
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},
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};
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int scan_index;
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@ -384,21 +568,6 @@ static int mcp3911_config(struct mcp3911 *adc)
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u32 regval;
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int ret;
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ret = device_property_read_u32(dev, "microchip,device-addr", &adc->dev_addr);
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/*
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* Fallback to "device-addr" due to historical mismatch between
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* dt-bindings and implementation
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*/
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if (ret)
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device_property_read_u32(dev, "device-addr", &adc->dev_addr);
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if (adc->dev_addr > 3) {
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return dev_err_probe(dev, -EINVAL,
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"invalid device address (%i). Must be in range 0-3.\n",
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adc->dev_addr);
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}
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dev_dbg(dev, "use device address %i\n", adc->dev_addr);
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ret = mcp3911_read(adc, MCP3911_REG_CONFIG, ®val, 2);
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if (ret)
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return ret;
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@ -433,7 +602,97 @@ static int mcp3911_config(struct mcp3911 *adc)
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regval &= ~MCP3911_STATUSCOM_READ;
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regval |= FIELD_PREP(MCP3911_STATUSCOM_READ, 0x02);
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return mcp3911_write(adc, MCP3911_REG_STATUSCOM, regval, 2);
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regval &= ~MCP3911_STATUSCOM_DRHIZ;
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if (device_property_read_bool(dev, "microchip,data-ready-hiz"))
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regval |= FIELD_PREP(MCP3911_STATUSCOM_DRHIZ, 0);
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else
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regval |= FIELD_PREP(MCP3911_STATUSCOM_DRHIZ, 1);
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/* Disable offset to ignore any old values in offset register */
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regval &= ~MCP3911_STATUSCOM_EN_OFFCAL;
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ret = mcp3911_write(adc, MCP3911_REG_STATUSCOM, regval, 2);
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if (ret)
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return ret;
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/* Set gain to 1 for all channels */
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ret = mcp3911_read(adc, MCP3911_REG_GAIN, ®val, 1);
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if (ret)
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return ret;
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for (int i = 0; i < adc->chip->num_channels - 1; i++) {
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adc->gain[i] = 1;
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regval &= ~MCP3911_GAIN_MASK(i);
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}
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return mcp3911_write(adc, MCP3911_REG_GAIN, regval, 1);
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}
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static int mcp3910_config(struct mcp3911 *adc)
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{
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struct device *dev = &adc->spi->dev;
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u32 regval;
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int ret;
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ret = mcp3911_read(adc, MCP3910_REG_CONFIG1, ®val, 3);
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if (ret)
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return ret;
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regval &= ~MCP3910_CONFIG1_VREFEXT;
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if (adc->vref) {
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dev_dbg(dev, "use external voltage reference\n");
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regval |= FIELD_PREP(MCP3910_CONFIG1_VREFEXT, 1);
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} else {
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dev_dbg(dev, "use internal voltage reference (1.2V)\n");
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regval |= FIELD_PREP(MCP3910_CONFIG1_VREFEXT, 0);
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}
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regval &= ~MCP3910_CONFIG1_CLKEXT;
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if (adc->clki) {
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dev_dbg(dev, "use external clock as clocksource\n");
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regval |= FIELD_PREP(MCP3910_CONFIG1_CLKEXT, 1);
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} else {
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dev_dbg(dev, "use crystal oscillator as clocksource\n");
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regval |= FIELD_PREP(MCP3910_CONFIG1_CLKEXT, 0);
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}
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ret = mcp3911_write(adc, MCP3910_REG_CONFIG1, regval, 3);
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||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = mcp3911_read(adc, MCP3910_REG_STATUSCOM, ®val, 3);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Address counter incremented, cycle through register types */
|
||||
regval &= ~MCP3910_STATUSCOM_READ;
|
||||
regval |= FIELD_PREP(MCP3910_STATUSCOM_READ, 0x02);
|
||||
|
||||
regval &= ~MCP3910_STATUSCOM_DRHIZ;
|
||||
if (device_property_read_bool(dev, "microchip,data-ready-hiz"))
|
||||
regval |= FIELD_PREP(MCP3910_STATUSCOM_DRHIZ, 0);
|
||||
else
|
||||
regval |= FIELD_PREP(MCP3910_STATUSCOM_DRHIZ, 1);
|
||||
|
||||
ret = mcp3911_write(adc, MCP3910_REG_STATUSCOM, regval, 3);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Set gain to 1 for all channels */
|
||||
ret = mcp3911_read(adc, MCP3910_REG_GAIN, ®val, 3);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
for (int i = 0; i < adc->chip->num_channels - 1; i++) {
|
||||
adc->gain[i] = 1;
|
||||
regval &= ~MCP3911_GAIN_MASK(i);
|
||||
}
|
||||
ret = mcp3911_write(adc, MCP3910_REG_GAIN, regval, 3);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Disable offset to ignore any old values in offset register */
|
||||
return adc->chip->enable_offset(adc, 0);
|
||||
}
|
||||
|
||||
static void mcp3911_cleanup_regulator(void *vref)
|
||||
|
|
@ -471,6 +730,7 @@ static int mcp3911_probe(struct spi_device *spi)
|
|||
|
||||
adc = iio_priv(indio_dev);
|
||||
adc->spi = spi;
|
||||
adc->chip = spi_get_device_match_data(spi);
|
||||
|
||||
adc->vref = devm_regulator_get_optional(dev, "vref");
|
||||
if (IS_ERR(adc->vref)) {
|
||||
|
|
@ -499,16 +759,21 @@ static int mcp3911_probe(struct spi_device *spi)
|
|||
}
|
||||
}
|
||||
|
||||
ret = mcp3911_config(adc);
|
||||
/*
|
||||
* Fallback to "device-addr" due to historical mismatch between
|
||||
* dt-bindings and implementation.
|
||||
*/
|
||||
ret = device_property_read_u32(dev, "microchip,device-addr", &adc->dev_addr);
|
||||
if (ret)
|
||||
return ret;
|
||||
device_property_read_u32(dev, "device-addr", &adc->dev_addr);
|
||||
if (adc->dev_addr > 3) {
|
||||
return dev_err_probe(dev, -EINVAL,
|
||||
"invalid device address (%i). Must be in range 0-3.\n",
|
||||
adc->dev_addr);
|
||||
}
|
||||
dev_dbg(dev, "use device address %i\n", adc->dev_addr);
|
||||
|
||||
if (device_property_read_bool(dev, "microchip,data-ready-hiz"))
|
||||
ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM, MCP3911_STATUSCOM_DRHIZ,
|
||||
0, 2);
|
||||
else
|
||||
ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM, MCP3911_STATUSCOM_DRHIZ,
|
||||
MCP3911_STATUSCOM_DRHIZ, 2);
|
||||
ret = adc->chip->config(adc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -517,7 +782,7 @@ static int mcp3911_probe(struct spi_device *spi)
|
|||
return ret;
|
||||
|
||||
/* Set gain to 1 for all channels */
|
||||
for (int i = 0; i < MCP3911_NUM_CHANNELS; i++) {
|
||||
for (int i = 0; i < adc->chip->num_channels - 1; i++) {
|
||||
adc->gain[i] = 1;
|
||||
ret = mcp3911_update(adc, MCP3911_REG_GAIN,
|
||||
MCP3911_GAIN_MASK(i),
|
||||
|
|
@ -531,8 +796,8 @@ static int mcp3911_probe(struct spi_device *spi)
|
|||
indio_dev->info = &mcp3911_info;
|
||||
spi_set_drvdata(spi, indio_dev);
|
||||
|
||||
indio_dev->channels = mcp3911_channels;
|
||||
indio_dev->num_channels = ARRAY_SIZE(mcp3911_channels);
|
||||
indio_dev->channels = adc->chip->channels;
|
||||
indio_dev->num_channels = adc->chip->num_channels;
|
||||
|
||||
mutex_init(&adc->lock);
|
||||
|
||||
|
|
@ -568,14 +833,105 @@ static int mcp3911_probe(struct spi_device *spi)
|
|||
return devm_iio_device_register(dev, indio_dev);
|
||||
}
|
||||
|
||||
static const struct mcp3911_chip_info mcp3911_chip_info[] = {
|
||||
[MCP3910] = {
|
||||
.channels = mcp3910_channels,
|
||||
.num_channels = ARRAY_SIZE(mcp3910_channels),
|
||||
.config = mcp3910_config,
|
||||
.get_osr = mcp3910_get_osr,
|
||||
.set_osr = mcp3910_set_osr,
|
||||
.enable_offset = mcp3910_enable_offset,
|
||||
.get_offset = mcp3910_get_offset,
|
||||
.set_offset = mcp3910_set_offset,
|
||||
.set_scale = mcp3910_set_scale,
|
||||
},
|
||||
[MCP3911] = {
|
||||
.channels = mcp3911_channels,
|
||||
.num_channels = ARRAY_SIZE(mcp3911_channels),
|
||||
.config = mcp3911_config,
|
||||
.get_osr = mcp3911_get_osr,
|
||||
.set_osr = mcp3911_set_osr,
|
||||
.enable_offset = mcp3911_enable_offset,
|
||||
.get_offset = mcp3911_get_offset,
|
||||
.set_offset = mcp3911_set_offset,
|
||||
.set_scale = mcp3911_set_scale,
|
||||
},
|
||||
[MCP3912] = {
|
||||
.channels = mcp3912_channels,
|
||||
.num_channels = ARRAY_SIZE(mcp3912_channels),
|
||||
.config = mcp3910_config,
|
||||
.get_osr = mcp3910_get_osr,
|
||||
.set_osr = mcp3910_set_osr,
|
||||
.enable_offset = mcp3910_enable_offset,
|
||||
.get_offset = mcp3910_get_offset,
|
||||
.set_offset = mcp3910_set_offset,
|
||||
.set_scale = mcp3910_set_scale,
|
||||
},
|
||||
[MCP3913] = {
|
||||
.channels = mcp3913_channels,
|
||||
.num_channels = ARRAY_SIZE(mcp3913_channels),
|
||||
.config = mcp3910_config,
|
||||
.get_osr = mcp3910_get_osr,
|
||||
.set_osr = mcp3910_set_osr,
|
||||
.enable_offset = mcp3910_enable_offset,
|
||||
.get_offset = mcp3910_get_offset,
|
||||
.set_offset = mcp3910_set_offset,
|
||||
.set_scale = mcp3910_set_scale,
|
||||
},
|
||||
[MCP3914] = {
|
||||
.channels = mcp3914_channels,
|
||||
.num_channels = ARRAY_SIZE(mcp3914_channels),
|
||||
.config = mcp3910_config,
|
||||
.get_osr = mcp3910_get_osr,
|
||||
.set_osr = mcp3910_set_osr,
|
||||
.enable_offset = mcp3910_enable_offset,
|
||||
.get_offset = mcp3910_get_offset,
|
||||
.set_offset = mcp3910_set_offset,
|
||||
.set_scale = mcp3910_set_scale,
|
||||
},
|
||||
[MCP3918] = {
|
||||
.channels = mcp3918_channels,
|
||||
.num_channels = ARRAY_SIZE(mcp3918_channels),
|
||||
.config = mcp3910_config,
|
||||
.get_osr = mcp3910_get_osr,
|
||||
.set_osr = mcp3910_set_osr,
|
||||
.enable_offset = mcp3910_enable_offset,
|
||||
.get_offset = mcp3910_get_offset,
|
||||
.set_offset = mcp3910_set_offset,
|
||||
.set_scale = mcp3910_set_scale,
|
||||
},
|
||||
[MCP3919] = {
|
||||
.channels = mcp3919_channels,
|
||||
.num_channels = ARRAY_SIZE(mcp3919_channels),
|
||||
.config = mcp3910_config,
|
||||
.get_osr = mcp3910_get_osr,
|
||||
.set_osr = mcp3910_set_osr,
|
||||
.enable_offset = mcp3910_enable_offset,
|
||||
.get_offset = mcp3910_get_offset,
|
||||
.set_offset = mcp3910_set_offset,
|
||||
.set_scale = mcp3910_set_scale,
|
||||
},
|
||||
};
|
||||
static const struct of_device_id mcp3911_dt_ids[] = {
|
||||
{ .compatible = "microchip,mcp3911" },
|
||||
{ .compatible = "microchip,mcp3910", .data = &mcp3911_chip_info[MCP3910] },
|
||||
{ .compatible = "microchip,mcp3911", .data = &mcp3911_chip_info[MCP3911] },
|
||||
{ .compatible = "microchip,mcp3912", .data = &mcp3911_chip_info[MCP3912] },
|
||||
{ .compatible = "microchip,mcp3913", .data = &mcp3911_chip_info[MCP3913] },
|
||||
{ .compatible = "microchip,mcp3914", .data = &mcp3911_chip_info[MCP3914] },
|
||||
{ .compatible = "microchip,mcp3918", .data = &mcp3911_chip_info[MCP3918] },
|
||||
{ .compatible = "microchip,mcp3919", .data = &mcp3911_chip_info[MCP3919] },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mcp3911_dt_ids);
|
||||
|
||||
static const struct spi_device_id mcp3911_id[] = {
|
||||
{ "mcp3911", 0 },
|
||||
{ "mcp3910", (kernel_ulong_t)&mcp3911_chip_info[MCP3910] },
|
||||
{ "mcp3911", (kernel_ulong_t)&mcp3911_chip_info[MCP3911] },
|
||||
{ "mcp3912", (kernel_ulong_t)&mcp3911_chip_info[MCP3912] },
|
||||
{ "mcp3913", (kernel_ulong_t)&mcp3911_chip_info[MCP3913] },
|
||||
{ "mcp3914", (kernel_ulong_t)&mcp3911_chip_info[MCP3914] },
|
||||
{ "mcp3918", (kernel_ulong_t)&mcp3911_chip_info[MCP3918] },
|
||||
{ "mcp3919", (kernel_ulong_t)&mcp3911_chip_info[MCP3919] },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(spi, mcp3911_id);
|
||||
|
|
|
|||
Loading…
Reference in a new issue