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drm/i915: Use literal representation of cdclk tables
The bspec lays out legal cdclk frequencies, PLL ratios, and CD2X dividers in an easy-to-read table for most recent platforms. We've been translating the data from that table into platform-specific code logic, but it's easy to overlook an area we need to update when adding new cdclk values or enabling new platforms. Let's just add a form of the bspec table to the code and then adjust our functions to pull what they need directly out of the table. v2: Fix comparison when finding best cdclk. v3: Another logic fix for calc_cdclk. v4: - Use named initializers for cdclk tables. (Ville) - Include refclk as a field in the table instead of adding all three ratios for each entry. (Ville) - Terminate tables with an empty entry to avoid needing to store the table size. (Ville) - Don't try so hard to return reasonable values from our lookup functions if we get impossible inputs; just WARN and return 0. (Ville) - Keep a bxt_ prefix on the lookup functions since they're still only used on bxt+ for now. We can rename them later if we extend this table-based approach back to older platforms. (Ville) v5: - Fix cnl table's ratios for 24mhz refclk. (Ville) - Don't miss the named initializers on the cnl table. (Ville) - Represent refclk in table as u16 rather than u32. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190910161506.7158-1-matthew.d.roper@intel.com
This commit is contained in:
Matt Roper
parent
71dc367e2b
commit
736da8112f
3 changed files with 109 additions and 202 deletions
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@ -1161,28 +1161,88 @@ static void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
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skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
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}
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static int bxt_calc_cdclk(int min_cdclk)
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static const struct intel_cdclk_vals bxt_cdclk_table[] = {
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{ .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
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{ .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
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{ .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
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{ .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
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{ .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
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{}
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};
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static const struct intel_cdclk_vals glk_cdclk_table[] = {
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{ .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
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{ .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
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{ .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
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{}
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};
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static const struct intel_cdclk_vals cnl_cdclk_table[] = {
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{ .refclk = 19200, .cdclk = 168000, .divider = 4, .ratio = 35 },
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{ .refclk = 19200, .cdclk = 336000, .divider = 2, .ratio = 35 },
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{ .refclk = 19200, .cdclk = 528000, .divider = 2, .ratio = 55 },
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{ .refclk = 24000, .cdclk = 168000, .divider = 4, .ratio = 28 },
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{ .refclk = 24000, .cdclk = 336000, .divider = 2, .ratio = 28 },
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{ .refclk = 24000, .cdclk = 528000, .divider = 2, .ratio = 44 },
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{}
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};
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static const struct intel_cdclk_vals icl_cdclk_table[] = {
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{ .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
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{ .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
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{ .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
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{ .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
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{ .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
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{ .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
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{ .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
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{ .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
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{ .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
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{ .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
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{ .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
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{ .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
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{ .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
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{ .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
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{ .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
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{ .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
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{ .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
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{ .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
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{}
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};
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static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
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{
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if (min_cdclk > 576000)
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return 624000;
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else if (min_cdclk > 384000)
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return 576000;
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else if (min_cdclk > 288000)
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return 384000;
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else if (min_cdclk > 144000)
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return 288000;
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else
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return 144000;
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const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
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int i;
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for (i = 0; table[i].refclk; i++)
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if (table[i].refclk == dev_priv->cdclk.hw.ref &&
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table[i].cdclk >= min_cdclk)
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return table[i].cdclk;
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WARN(1, "Cannot satisfy minimum cdclk %d with refclk %u\n",
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min_cdclk, dev_priv->cdclk.hw.ref);
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return 0;
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}
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static int glk_calc_cdclk(int min_cdclk)
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static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
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{
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if (min_cdclk > 158400)
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return 316800;
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else if (min_cdclk > 79200)
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return 158400;
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else
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return 79200;
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const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
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int i;
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if (cdclk == dev_priv->cdclk.hw.bypass)
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return 0;
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for (i = 0; table[i].refclk; i++)
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if (table[i].refclk == dev_priv->cdclk.hw.ref &&
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table[i].cdclk == cdclk)
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return dev_priv->cdclk.hw.ref * table[i].ratio;
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WARN(1, "cdclk %d not valid for refclk %u\n",
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cdclk, dev_priv->cdclk.hw.ref);
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return 0;
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}
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static u8 bxt_calc_voltage_level(int cdclk)
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@ -1220,52 +1280,6 @@ static u8 ehl_calc_voltage_level(int cdclk)
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return 0;
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}
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static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
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{
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int ratio;
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if (cdclk == dev_priv->cdclk.hw.bypass)
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return 0;
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switch (cdclk) {
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default:
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MISSING_CASE(cdclk);
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/* fall through */
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case 144000:
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case 288000:
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case 384000:
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case 576000:
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ratio = 60;
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break;
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case 624000:
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ratio = 65;
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break;
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}
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return dev_priv->cdclk.hw.ref * ratio;
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}
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static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
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{
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int ratio;
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if (cdclk == dev_priv->cdclk.hw.bypass)
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return 0;
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switch (cdclk) {
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default:
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MISSING_CASE(cdclk);
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/* fall through */
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case 79200:
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case 158400:
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case 316800:
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ratio = 33;
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break;
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}
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return dev_priv->cdclk.hw.ref * ratio;
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}
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static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
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struct intel_cdclk_state *cdclk_state)
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{
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@ -1576,13 +1590,8 @@ static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
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* - The initial CDCLK needs to be read from VBT.
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* Need to make this change after VBT has changes for BXT.
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*/
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if (IS_GEMINILAKE(dev_priv)) {
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cdclk_state.cdclk = glk_calc_cdclk(0);
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cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
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} else {
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cdclk_state.cdclk = bxt_calc_cdclk(0);
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cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
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}
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cdclk_state.cdclk = bxt_calc_cdclk(dev_priv, 0);
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cdclk_state.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
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cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
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bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
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@ -1599,16 +1608,6 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
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bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
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}
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static int cnl_calc_cdclk(int min_cdclk)
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{
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if (min_cdclk > 336000)
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return 528000;
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else if (min_cdclk > 168000)
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return 336000;
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else
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return 168000;
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}
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static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
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{
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u32 val;
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@ -1718,29 +1717,6 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
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dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
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}
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static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
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{
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int ratio;
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if (cdclk == dev_priv->cdclk.hw.bypass)
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return 0;
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switch (cdclk) {
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default:
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MISSING_CASE(cdclk);
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/* fall through */
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case 168000:
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case 336000:
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ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
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break;
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case 528000:
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ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
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break;
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}
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return dev_priv->cdclk.hw.ref * ratio;
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}
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static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
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{
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u32 cdctl, expected;
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@ -1783,77 +1759,6 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
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dev_priv->cdclk.hw.vco = -1;
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}
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static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
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{
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static const int ranges_24[] = { 180000, 192000, 312000, 324000,
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552000, 648000 };
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static const int ranges_19_38[] = { 172800, 192000, 307200, 326400,
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556800, 652800 };
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const int *ranges;
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int len, i;
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switch (ref) {
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default:
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MISSING_CASE(ref);
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/* fall through */
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case 24000:
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ranges = ranges_24;
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len = ARRAY_SIZE(ranges_24);
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break;
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case 19200:
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case 38400:
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ranges = ranges_19_38;
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len = ARRAY_SIZE(ranges_19_38);
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break;
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}
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for (i = 0; i < len; i++) {
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if (min_cdclk <= ranges[i])
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return ranges[i];
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}
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WARN_ON(min_cdclk > ranges[len - 1]);
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return ranges[len - 1];
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}
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static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
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{
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int ratio;
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if (cdclk == dev_priv->cdclk.hw.bypass)
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return 0;
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switch (cdclk) {
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default:
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MISSING_CASE(cdclk);
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/* fall through */
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case 172800:
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case 307200:
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case 326400:
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case 556800:
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case 652800:
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WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
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dev_priv->cdclk.hw.ref != 38400);
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break;
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case 180000:
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case 312000:
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case 324000:
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case 552000:
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case 648000:
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WARN_ON(dev_priv->cdclk.hw.ref != 24000);
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break;
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case 192000:
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WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
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dev_priv->cdclk.hw.ref != 38400 &&
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dev_priv->cdclk.hw.ref != 24000);
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break;
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}
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ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
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return dev_priv->cdclk.hw.ref * ratio;
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}
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static void icl_init_cdclk(struct drm_i915_private *dev_priv)
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{
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struct intel_cdclk_state sanitized_state;
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@ -1882,8 +1787,8 @@ static void icl_init_cdclk(struct drm_i915_private *dev_priv)
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DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
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sanitized_state.ref = dev_priv->cdclk.hw.ref;
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sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
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sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
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sanitized_state.cdclk = bxt_calc_cdclk(dev_priv, 0);
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sanitized_state.vco = bxt_calc_cdclk_pll_vco(dev_priv,
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sanitized_state.cdclk);
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if (IS_ELKHARTLAKE(dev_priv))
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sanitized_state.voltage_level =
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@ -1923,8 +1828,8 @@ static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
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cdclk_state = dev_priv->cdclk.hw;
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cdclk_state.cdclk = cnl_calc_cdclk(0);
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cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
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cdclk_state.cdclk = bxt_calc_cdclk(dev_priv, 0);
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cdclk_state.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
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cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
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cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
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@ -2426,13 +2331,8 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
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if (min_cdclk < 0)
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return min_cdclk;
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if (IS_GEMINILAKE(dev_priv)) {
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cdclk = glk_calc_cdclk(min_cdclk);
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vco = glk_de_pll_vco(dev_priv, cdclk);
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} else {
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cdclk = bxt_calc_cdclk(min_cdclk);
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vco = bxt_de_pll_vco(dev_priv, cdclk);
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}
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cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
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vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
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state->cdclk.logical.vco = vco;
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state->cdclk.logical.cdclk = cdclk;
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@ -2440,13 +2340,8 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
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bxt_calc_voltage_level(cdclk);
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if (!state->active_pipes) {
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if (IS_GEMINILAKE(dev_priv)) {
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cdclk = glk_calc_cdclk(state->cdclk.force_min_cdclk);
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vco = glk_de_pll_vco(dev_priv, cdclk);
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} else {
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cdclk = bxt_calc_cdclk(state->cdclk.force_min_cdclk);
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vco = bxt_de_pll_vco(dev_priv, cdclk);
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}
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cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
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vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
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state->cdclk.actual.vco = vco;
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state->cdclk.actual.cdclk = cdclk;
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@ -2468,8 +2363,8 @@ static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
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if (min_cdclk < 0)
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return min_cdclk;
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cdclk = cnl_calc_cdclk(min_cdclk);
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vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
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cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
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vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
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state->cdclk.logical.vco = vco;
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state->cdclk.logical.cdclk = cdclk;
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@ -2478,8 +2373,8 @@ static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
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cnl_compute_min_voltage_level(state));
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if (!state->active_pipes) {
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cdclk = cnl_calc_cdclk(state->cdclk.force_min_cdclk);
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vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
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cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
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vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
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state->cdclk.actual.vco = vco;
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state->cdclk.actual.cdclk = cdclk;
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@ -2495,15 +2390,14 @@ static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
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static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
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{
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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||||
unsigned int ref = state->cdclk.logical.ref;
|
||||
int min_cdclk, cdclk, vco;
|
||||
|
||||
min_cdclk = intel_compute_min_cdclk(state);
|
||||
if (min_cdclk < 0)
|
||||
return min_cdclk;
|
||||
|
||||
cdclk = icl_calc_cdclk(min_cdclk, ref);
|
||||
vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
|
||||
cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
|
||||
vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
|
||||
|
||||
state->cdclk.logical.vco = vco;
|
||||
state->cdclk.logical.cdclk = cdclk;
|
||||
|
|
@ -2517,8 +2411,8 @@ static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
|
|||
cnl_compute_min_voltage_level(state));
|
||||
|
||||
if (!state->active_pipes) {
|
||||
cdclk = icl_calc_cdclk(state->cdclk.force_min_cdclk, ref);
|
||||
vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
|
||||
cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
|
||||
vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
|
||||
|
||||
state->cdclk.actual.vco = vco;
|
||||
state->cdclk.actual.cdclk = cdclk;
|
||||
|
|
@ -2754,12 +2648,15 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
|
|||
if (INTEL_GEN(dev_priv) >= 11) {
|
||||
dev_priv->display.set_cdclk = cnl_set_cdclk;
|
||||
dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
|
||||
dev_priv->cdclk.table = icl_cdclk_table;
|
||||
} else if (IS_CANNONLAKE(dev_priv)) {
|
||||
dev_priv->display.set_cdclk = cnl_set_cdclk;
|
||||
dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
|
||||
dev_priv->cdclk.table = cnl_cdclk_table;
|
||||
} else if (IS_GEN9_LP(dev_priv)) {
|
||||
dev_priv->display.set_cdclk = bxt_set_cdclk;
|
||||
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
|
||||
dev_priv->cdclk.table = bxt_cdclk_table;
|
||||
} else if (IS_GEN9_BC(dev_priv)) {
|
||||
dev_priv->display.set_cdclk = skl_set_cdclk;
|
||||
dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
|
||||
|
|
|
|||
|
|
@ -15,6 +15,13 @@ struct intel_atomic_state;
|
|||
struct intel_cdclk_state;
|
||||
struct intel_crtc_state;
|
||||
|
||||
struct intel_cdclk_vals {
|
||||
u16 refclk;
|
||||
u32 cdclk;
|
||||
u8 divider; /* CD2X divider * 2 */
|
||||
u8 ratio;
|
||||
};
|
||||
|
||||
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
|
||||
void intel_cdclk_init(struct drm_i915_private *i915);
|
||||
void intel_cdclk_uninit(struct drm_i915_private *i915);
|
||||
|
|
|
|||
|
|
@ -1420,6 +1420,9 @@ struct drm_i915_private {
|
|||
/* The current hardware cdclk state */
|
||||
struct intel_cdclk_state hw;
|
||||
|
||||
/* cdclk, divider, and ratio table from bspec */
|
||||
const struct intel_cdclk_vals *table;
|
||||
|
||||
int force_min_cdclk;
|
||||
} cdclk;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue