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drm/amd/display: Add debug prints for SMU messages

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[Why&How]
Add debug prints for SMU messages with regard to
versions, clocks, and more.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Robin Singh <Robin.Singh@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry Wentland 2020-06-24 10:36:00 -04:00 committed by Alex Deucher
parent 3306ace54e
commit 73affd3052
1 changed files with 25 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

29
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
View file

@ -113,10 +113,13 @@ int dcn301_smu_send_msg_with_param(
int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
{
return dcn301_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_GetSmuVersion,
0);
int smu_version = dcn301_smu_send_msg_with_param(clk_mgr,
VBIOSSMC_MSG_GetSmuVersion,
0);
DC_LOG_DEBUG("%s %x\n", __func__, smu_version);
return smu_version;
}
@ -124,6 +127,8 @@ int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispc
{
int actual_dispclk_set_mhz = -1;
DC_LOG_DEBUG("%s(%d)\n", __func__, requested_dispclk_khz);
/* Unit of SMU msg parameter is Mhz */
actual_dispclk_set_mhz = dcn301_smu_send_msg_with_param(
clk_mgr,
@ -137,6 +142,8 @@ int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
{
int actual_dprefclk_set_mhz = -1;
DC_LOG_DEBUG("%s %d\n", __func__, clk_mgr->base.dprefclk_khz / 1000);
actual_dprefclk_set_mhz = dcn301_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetDprefclkFreq,
@ -151,6 +158,8 @@ int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int request
{
int actual_dcfclk_set_mhz = -1;
DC_LOG_DEBUG("%s(%d)\n", __func__, requested_dcfclk_khz);
actual_dcfclk_set_mhz = dcn301_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
@ -163,6 +172,8 @@ int dcn301_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int r
{
int actual_min_ds_dcfclk_mhz = -1;
DC_LOG_DEBUG("%s(%d)\n", __func__, requested_min_ds_dcfclk_khz);
actual_min_ds_dcfclk_mhz = dcn301_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetMinDeepSleepDcfclk,
@ -175,6 +186,8 @@ int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_kh
{
int actual_dppclk_set_mhz = -1;
DC_LOG_DEBUG("%s(%d)\n", __func__, requested_dpp_khz);
actual_dppclk_set_mhz = dcn301_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetDppclkFreq,
@ -187,6 +200,8 @@ void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr,
{
//TODO: Work with smu team to define optimization options.
DC_LOG_DEBUG("%s(%x)\n", __func__, idle_info);
dcn301_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetDisplayIdleOptimizations,
@ -202,6 +217,8 @@ void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool
idle_info.idle_info.phy_ref_clk_off = 1;
}
DC_LOG_DEBUG("%s(%d)\n", __func__, enable);
dcn301_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetDisplayIdleOptimizations,
@ -218,12 +235,16 @@ void dcn301_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
{
DC_LOG_DEBUG("%s(%x)\n", __func__, addr_high);
dcn301_smu_send_msg_with_param(clk_mgr,
VBIOSSMC_MSG_SetVbiosDramAddrHigh, addr_high);
}
void dcn301_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)
{
DC_LOG_DEBUG("%s(%x)\n", __func__, addr_low);
dcn301_smu_send_msg_with_param(clk_mgr,
VBIOSSMC_MSG_SetVbiosDramAddrLow, addr_low);
}