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drm/amdgpu: Add CLK IP base offset
so we can read/write the registers in CLK domain through RREG32/WREG32_SOC15 Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2 changed files with 2 additions and 0 deletions
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@ -1398,6 +1398,7 @@ enum amd_hw_ip_block_type {
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PWR_HWIP,
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NBIF_HWIP,
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THM_HWIP,
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CLK_HWIP,
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MAX_HWIP
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};
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@ -51,6 +51,7 @@ int vega10_reg_base_init(struct amdgpu_device *adev)
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adev->reg_offset[PWR_HWIP][i] = (uint32_t *)(&(PWR_BASE.instance[i]));
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adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIF_BASE.instance[i]));
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adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
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adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
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}
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return 0;
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}
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