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drm/amdgpu: switch back to 32bit hw fences v2
We don't need to extend them to 64bits any more, so avoid the extra overhead. v2: update commit message. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
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480d0bf07e
commit
742c085fa8
2 changed files with 21 additions and 32 deletions
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@ -386,8 +386,8 @@ struct amdgpu_fence_driver {
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uint64_t gpu_addr;
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volatile uint32_t *cpu_addr;
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/* sync_seq is protected by ring emission lock */
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uint64_t sync_seq;
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atomic64_t last_seq;
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uint32_t sync_seq;
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atomic_t last_seq;
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bool initialized;
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struct amdgpu_irq_src *irq_src;
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unsigned irq_type;
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@ -52,7 +52,6 @@ struct amdgpu_fence {
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/* RB, DMA, etc. */
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struct amdgpu_ring *ring;
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uint64_t seq;
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};
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static struct kmem_cache *amdgpu_fence_slab;
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@ -104,7 +103,7 @@ static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
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if (drv->cpu_addr)
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seq = le32_to_cpu(*drv->cpu_addr);
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else
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seq = lower_32_bits(atomic64_read(&drv->last_seq));
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seq = atomic_read(&drv->last_seq);
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return seq;
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}
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@ -123,23 +122,22 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f)
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struct amdgpu_device *adev = ring->adev;
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struct amdgpu_fence *fence;
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struct fence **ptr;
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unsigned idx;
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uint32_t seq;
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fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
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if (fence == NULL)
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return -ENOMEM;
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fence->seq = ++ring->fence_drv.sync_seq;
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seq = ++ring->fence_drv.sync_seq;
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fence->ring = ring;
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fence_init(&fence->base, &amdgpu_fence_ops,
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&ring->fence_drv.lock,
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adev->fence_context + ring->idx,
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fence->seq);
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seq);
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amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
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fence->seq, AMDGPU_FENCE_FLAG_INT);
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seq, AMDGPU_FENCE_FLAG_INT);
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idx = fence->seq & ring->fence_drv.num_fences_mask;
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ptr = &ring->fence_drv.fences[idx];
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ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
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/* This function can't be called concurrently anyway, otherwise
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* emitting the fence would mess up the hardware ring buffer.
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*/
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@ -177,22 +175,16 @@ static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
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void amdgpu_fence_process(struct amdgpu_ring *ring)
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{
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struct amdgpu_fence_driver *drv = &ring->fence_drv;
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uint64_t seq, last_seq, last_emitted;
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uint32_t seq, last_seq;
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int r;
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do {
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last_seq = atomic64_read(&ring->fence_drv.last_seq);
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last_emitted = ring->fence_drv.sync_seq;
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last_seq = atomic_read(&ring->fence_drv.last_seq);
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seq = amdgpu_fence_read(ring);
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seq |= last_seq & 0xffffffff00000000LL;
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if (seq < last_seq) {
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seq &= 0xffffffff;
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seq |= last_emitted & 0xffffffff00000000LL;
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}
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} while (atomic64_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
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} while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
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if (seq < last_emitted)
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if (seq != ring->fence_drv.sync_seq)
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amdgpu_fence_schedule_fallback(ring);
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while (last_seq != seq) {
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@ -279,13 +271,10 @@ unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
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* but it's ok to report slightly wrong fence count here.
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*/
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amdgpu_fence_process(ring);
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emitted = ring->fence_drv.sync_seq
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- atomic64_read(&ring->fence_drv.last_seq);
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/* to avoid 32bits warp around */
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if (emitted > 0x10000000)
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emitted = 0x10000000;
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return (unsigned)emitted;
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emitted = 0x100000000ull;
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emitted -= atomic_read(&ring->fence_drv.last_seq);
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emitted += ACCESS_ONCE(ring->fence_drv.sync_seq);
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return lower_32_bits(emitted);
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}
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/**
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@ -317,7 +306,7 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
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ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index;
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ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index;
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}
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amdgpu_fence_write(ring, atomic64_read(&ring->fence_drv.last_seq));
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amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
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amdgpu_irq_get(adev, irq_src, irq_type);
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ring->fence_drv.irq_src = irq_src;
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@ -353,7 +342,7 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
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ring->fence_drv.cpu_addr = NULL;
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ring->fence_drv.gpu_addr = 0;
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ring->fence_drv.sync_seq = 0;
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atomic64_set(&ring->fence_drv.last_seq, 0);
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atomic_set(&ring->fence_drv.last_seq, 0);
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ring->fence_drv.initialized = false;
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setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback,
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@ -621,9 +610,9 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
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amdgpu_fence_process(ring);
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seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
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seq_printf(m, "Last signaled fence 0x%016llx\n",
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(unsigned long long)atomic64_read(&ring->fence_drv.last_seq));
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seq_printf(m, "Last emitted 0x%016llx\n",
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seq_printf(m, "Last signaled fence 0x%08x\n",
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atomic_read(&ring->fence_drv.last_seq));
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seq_printf(m, "Last emitted 0x%08x\n",
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ring->fence_drv.sync_seq);
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}
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return 0;
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