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This is the pxa changes for v4.2 cycle. 

The main and only feature is the conversion of all pxa variants to clock
 framework. This encompasses pxa25x, pxa27x and pxa3xx, for all boards.
 
 This should be a disruptive cycle in the normally quiet pxa history, as
 the change can break any platform, and the test were performed on only 4
 boards (lubbock, zylonite, mioa701, cm-x300).
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Merge tag 'pxa-for-4.2' of https://github.com/rjarzmik/linux into next/soc

Merge "pxa changes for v4.2 cycle" from Robert Jarzmik:

The main and only feature is the conversion of all pxa variants to clock
framework. This encompasses pxa25x, pxa27x and pxa3xx, for all boards.

This should be a disruptive cycle in the normally quiet pxa history, as
the change can break any platform, and the test were performed on only 4
boards (lubbock, zylonite, mioa701, cm-x300).

* tag 'pxa-for-4.2' of https://github.com/rjarzmik/linux:
  ARM: pxa: Constify irq_domain_ops
  ARM: pxa: Transition pxa25x, pxa27x, pxa3xx to clk framework
  ARM: pxa: convert eseries to clock framework
  ARM: pxa: Transition pxa25x and pxa27x to clk framework
  ARM: pxa: pxa27x skip default device initialization with DT
  clk: pxa: add missing pxa27x clocks for Irda and sa1100-rtc
  ARM: pxa: move gpio11 clock to board files
  ARM: pxa: change clocks init sequence
This commit is contained in:
Arnd Bergmann 2015-05-15 17:40:15 +02:00
parent e3abcb25d2 64227114c6
commit 7448adca93
19 changed files with 63 additions and 910 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/Kconfig
View File

@ -606,6 +606,7 @@ config ARCH_PXA
select ARCH_REQUIRE_GPIOLIB
select ARM_CPU_SUSPEND if PM
select AUTO_ZRELADDR
select COMMON_CLK
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_OF

9
arch/arm/mach-pxa/Makefile
View File

@ -3,16 +3,15 @@
#
# Common support (must be linked before board specific support)
obj-y += clock.o devices.o generic.o irq.o \
reset.o
obj-y += devices.o generic.o irq.o reset.o
obj-$(CONFIG_PM) += pm.o sleep.o standby.o
# Generic drivers that other drivers may depend upon
# SoC-specific code
obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa25x.o
obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa27x.o
obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa2xx.o pxa25x.o
obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa2xx.o pxa27x.o
obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
obj-$(CONFIG_CPU_PXA300) += pxa300.o
obj-$(CONFIG_CPU_PXA320) += pxa320.o
obj-$(CONFIG_CPU_PXA930) += pxa930.o

55
arch/arm/mach-pxa/clock-pxa2xx.c
View File

@ -1,55 +0,0 @@
/*
* linux/arch/arm/mach-pxa/clock-pxa2xx.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/syscore_ops.h>
#include <mach/pxa2xx-regs.h>
#include "clock.h"
void clk_pxa2xx_cken_enable(struct clk *clk)
{
CKEN |= 1 << clk->cken;
}
void clk_pxa2xx_cken_disable(struct clk *clk)
{
CKEN &= ~(1 << clk->cken);
}
const struct clkops clk_pxa2xx_cken_ops = {
.enable = clk_pxa2xx_cken_enable,
.disable = clk_pxa2xx_cken_disable,
};
#ifdef CONFIG_PM
static uint32_t saved_cken;
static int pxa2xx_clock_suspend(void)
{
saved_cken = CKEN;
return 0;
}
static void pxa2xx_clock_resume(void)
{
CKEN = saved_cken;
}
#else
#define pxa2xx_clock_suspend NULL
#define pxa2xx_clock_resume NULL
#endif
struct syscore_ops pxa2xx_clock_syscore_ops = {
.suspend = pxa2xx_clock_suspend,
.resume = pxa2xx_clock_resume,
};

212
arch/arm/mach-pxa/clock-pxa3xx.c
View File

@ -1,212 +0,0 @@
/*
* linux/arch/arm/mach-pxa/clock-pxa3xx.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/syscore_ops.h>
#include <mach/smemc.h>
#include <mach/pxa3xx-regs.h>
#include "clock.h"
/* Crystal clock: 13MHz */
#define BASE_CLK 13000000
/* Ring Oscillator Clock: 60MHz */
#define RO_CLK 60000000
#define ACCR_D0CS (1 << 26)
#define ACCR_PCCE (1 << 11)
/* crystal frequency to HSIO bus frequency multiplier (HSS) */
static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
/*
* Get the clock frequency as reflected by CCSR and the turbo flag.
* We assume these values have been applied via a fcs.
* If info is not 0 we also display the current settings.
*/
unsigned int pxa3xx_get_clk_frequency_khz(int info)
{
unsigned long acsr, xclkcfg;
unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
/* Read XCLKCFG register turbo bit */
__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
t = xclkcfg & 0x1;
acsr = ACSR;
xl = acsr & 0x1f;
xn = (acsr >> 8) & 0x7;
hss = (acsr >> 14) & 0x3;
XL = xl * BASE_CLK;
XN = xn * XL;
ro = acsr & ACCR_D0CS;
CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
if (info) {
pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
(ro) ? "" : "in");
pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
XL / 1000000, (XL % 1000000) / 10000, xl);
pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
XN / 1000000, (XN % 1000000) / 10000, xn,
(t) ? "" : "in");
pr_info("HSIO bus clock: %d.%02dMHz\n",
HSS / 1000000, (HSS % 1000000) / 10000);
}
return CLK / 1000;
}
/*
* Return the current AC97 clock frequency.
*/
static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
{
unsigned long rate = 312000000;
unsigned long ac97_div;
ac97_div = AC97_DIV;
/* This may loose precision for some rates but won't for the
* standard 24.576MHz.
*/
rate /= (ac97_div >> 12) & 0x7fff;
rate *= (ac97_div & 0xfff);
return rate;
}
/*
* Return the current HSIO bus clock frequency
*/
static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
{
unsigned long acsr;
unsigned int hss, hsio_clk;
acsr = ACSR;
hss = (acsr >> 14) & 0x3;
hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
return hsio_clk;
}
/* crystal frequency to static memory controller multiplier (SMCFS) */
static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
static unsigned int df_clkdiv[4] = { 1, 2, 4, 1 };
static unsigned long clk_pxa3xx_smemc_getrate(struct clk *clk)
{
unsigned long acsr = ACSR;
unsigned long memclkcfg = __raw_readl(MEMCLKCFG);
return BASE_CLK * smcfs_mult[(acsr >> 23) & 0x7] /
df_clkdiv[(memclkcfg >> 16) & 0x3];
}
void clk_pxa3xx_cken_enable(struct clk *clk)
{
unsigned long mask = 1ul << (clk->cken & 0x1f);
if (clk->cken < 32)
CKENA |= mask;
else if (clk->cken < 64)
CKENB |= mask;
else
CKENC |= mask;
}
void clk_pxa3xx_cken_disable(struct clk *clk)
{
unsigned long mask = 1ul << (clk->cken & 0x1f);
if (clk->cken < 32)
CKENA &= ~mask;
else if (clk->cken < 64)
CKENB &= ~mask;
else
CKENC &= ~mask;
}
const struct clkops clk_pxa3xx_cken_ops = {
.enable = clk_pxa3xx_cken_enable,
.disable = clk_pxa3xx_cken_disable,
};
const struct clkops clk_pxa3xx_hsio_ops = {
.enable = clk_pxa3xx_cken_enable,
.disable = clk_pxa3xx_cken_disable,
.getrate = clk_pxa3xx_hsio_getrate,
};
const struct clkops clk_pxa3xx_ac97_ops = {
.enable = clk_pxa3xx_cken_enable,
.disable = clk_pxa3xx_cken_disable,
.getrate = clk_pxa3xx_ac97_getrate,
};
const struct clkops clk_pxa3xx_smemc_ops = {
.enable = clk_pxa3xx_cken_enable,
.disable = clk_pxa3xx_cken_disable,
.getrate = clk_pxa3xx_smemc_getrate,
};
static void clk_pout_enable(struct clk *clk)
{
OSCC |= OSCC_PEN;
}
static void clk_pout_disable(struct clk *clk)
{
OSCC &= ~OSCC_PEN;
}
const struct clkops clk_pxa3xx_pout_ops = {
.enable = clk_pout_enable,
.disable = clk_pout_disable,
};
#ifdef CONFIG_PM
static uint32_t cken[2];
static uint32_t accr;
static int pxa3xx_clock_suspend(void)
{
cken[0] = CKENA;
cken[1] = CKENB;
accr = ACCR;
return 0;
}
static void pxa3xx_clock_resume(void)
{
ACCR = accr;
CKENA = cken[0];
CKENB = cken[1];
}
#else
#define pxa3xx_clock_suspend NULL
#define pxa3xx_clock_resume NULL
#endif
struct syscore_ops pxa3xx_clock_syscore_ops = {
.suspend = pxa3xx_clock_suspend,
.resume = pxa3xx_clock_resume,
};

86
arch/arm/mach-pxa/clock.c
View File

@ -1,86 +0,0 @@
/*
* linux/arch/arm/mach-sa1100/clock.c
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/clkdev.h>
#include "clock.h"
static DEFINE_SPINLOCK(clocks_lock);
int clk_enable(struct clk *clk)
{
unsigned long flags;
spin_lock_irqsave(&clocks_lock, flags);
if (clk->enabled++ == 0)
clk->ops->enable(clk);
spin_unlock_irqrestore(&clocks_lock, flags);
if (clk->delay)
udelay(clk->delay);
return 0;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
unsigned long flags;
WARN_ON(clk->enabled == 0);
spin_lock_irqsave(&clocks_lock, flags);
if (--clk->enabled == 0)
clk->ops->disable(clk);
spin_unlock_irqrestore(&clocks_lock, flags);
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
unsigned long rate;
rate = clk->rate;
if (clk->ops->getrate)
rate = clk->ops->getrate(clk);
return rate;
}
EXPORT_SYMBOL(clk_get_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
unsigned long flags;
int ret = -EINVAL;
if (clk->ops->setrate) {
spin_lock_irqsave(&clocks_lock, flags);
ret = clk->ops->setrate(clk, rate);
spin_unlock_irqrestore(&clocks_lock, flags);
}
return ret;
}
EXPORT_SYMBOL(clk_set_rate);
void clk_dummy_enable(struct clk *clk)
{
}
void clk_dummy_disable(struct clk *clk)
{
}
const struct clkops clk_dummy_ops = {
.enable = clk_dummy_enable,
.disable = clk_dummy_disable,
};
struct clk clk_dummy = {
.ops = &clk_dummy_ops,
};

80
arch/arm/mach-pxa/clock.h
View File

@ -1,80 +0,0 @@
#include <linux/clkdev.h>
#include <linux/syscore_ops.h>
struct clkops {
void (*enable)(struct clk *);
void (*disable)(struct clk *);
unsigned long (*getrate)(struct clk *);
int (*setrate)(struct clk *, unsigned long);
};
struct clk {
const struct clkops *ops;
unsigned long rate;
unsigned int cken;
unsigned int delay;
unsigned int enabled;
};
void clk_dummy_enable(struct clk *);
void clk_dummy_disable(struct clk *);
extern const struct clkops clk_dummy_ops;
extern struct clk clk_dummy;
#define INIT_CLKREG(_clk,_devname,_conname) \
{ \
.clk = _clk, \
.dev_id = _devname, \
.con_id = _conname, \
}
#define DEFINE_CK(_name, _cken, _ops) \
struct clk clk_##_name = { \
.ops = _ops, \
.cken = CKEN_##_cken, \
}
#define DEFINE_CLK(_name, _ops, _rate, _delay) \
struct clk clk_##_name = { \
.ops = _ops, \
.rate = _rate, \
.delay = _delay, \
}
#define DEFINE_PXA2_CKEN(_name, _cken, _rate, _delay) \
struct clk clk_##_name = { \
.ops = &clk_pxa2xx_cken_ops, \
.rate = _rate, \
.cken = CKEN_##_cken, \
.delay = _delay, \
}
extern const struct clkops clk_pxa2xx_cken_ops;
void clk_pxa2xx_cken_enable(struct clk *clk);
void clk_pxa2xx_cken_disable(struct clk *clk);
extern struct syscore_ops pxa2xx_clock_syscore_ops;
#if defined(CONFIG_PXA3xx)
#define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay) \
struct clk clk_##_name = { \
.ops = &clk_pxa3xx_cken_ops, \
.rate = _rate, \
.cken = CKEN_##_cken, \
.delay = _delay, \
}
extern const struct clkops clk_pxa3xx_cken_ops;
extern const struct clkops clk_pxa3xx_hsio_ops;
extern const struct clkops clk_pxa3xx_ac97_ops;
extern const struct clkops clk_pxa3xx_pout_ops;
extern const struct clkops clk_pxa3xx_smemc_ops;
extern void clk_pxa3xx_cken_enable(struct clk *);
extern void clk_pxa3xx_cken_disable(struct clk *);
extern struct syscore_ops pxa3xx_clock_syscore_ops;
#endif

27
arch/arm/mach-pxa/eseries.c
View File

@ -12,6 +12,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk-provider.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
@ -39,7 +40,6 @@
#include "devices.h"
#include "generic.h"
#include "clock.h"
/* Only e800 has 128MB RAM */
void __init eseries_fixup(struct tag *tags, char **cmdline)
@ -125,27 +125,9 @@ struct resource eseries_tmio_resources[] = {
};
/* Some e-series hardware cannot control the 32K clock */
static void clk_32k_dummy(struct clk *clk)
{
}
static const struct clkops clk_32k_dummy_ops = {
.enable = clk_32k_dummy,
.disable = clk_32k_dummy,
};
static struct clk tmio_dummy_clk = {
.ops = &clk_32k_dummy_ops,
.rate = 32768,
};
static struct clk_lookup eseries_clkregs[] = {
INIT_CLKREG(&tmio_dummy_clk, NULL, "CLK_CK32K"),
};
static void __init eseries_register_clks(void)
{
clkdev_add_table(eseries_clkregs, ARRAY_SIZE(eseries_clkregs));
clk_register_fixed_rate(NULL, "CLK_CK32K", NULL, CLK_IS_ROOT, 32768);
}
#ifdef CONFIG_MACH_E330
@ -683,7 +665,7 @@ static unsigned long e750_pin_config[] __initdata = {
/* PC Card */
GPIO8_GPIO, /* CD0 */
GPIO44_GPIO, /* CD1 */
GPIO11_GPIO, /* IRQ0 */
/* GPIO11_GPIO, IRQ0 */
GPIO6_GPIO, /* IRQ1 */
GPIO27_GPIO, /* RST0 */
GPIO24_GPIO, /* RST1 */
@ -778,6 +760,9 @@ static unsigned long e800_pin_config[] __initdata = {
GPIO29_AC97_SDATA_IN_0,
GPIO30_AC97_SDATA_OUT,
GPIO31_AC97_SYNC,
/* tc6393xb */
GPIO11_3_6MHz,
};
static struct w100_gen_regs e800_lcd_regs = {

6
arch/arm/mach-pxa/generic.c
View File

@ -63,6 +63,12 @@ EXPORT_SYMBOL(get_clock_tick_rate);
*/
void __init pxa_timer_init(void)
{
if (cpu_is_pxa25x())
pxa25x_clocks_init();
if (cpu_is_pxa27x())
pxa27x_clocks_init();
if (cpu_is_pxa3xx())
pxa3xx_clocks_init();
pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000),
get_clock_tick_rate());
}

3
arch/arm/mach-pxa/generic.h
View File

@ -26,17 +26,20 @@ extern void pxa_timer_init(void);
#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
#define pxa25x_handle_irq icip_handle_irq
extern int __init pxa25x_clocks_init(void);
extern void __init pxa25x_init_irq(void);
extern void __init pxa25x_map_io(void);
extern void __init pxa26x_init_irq(void);
#define pxa27x_handle_irq ichp_handle_irq
extern int __init pxa27x_clocks_init(void);
extern void __init pxa27x_dt_init_irq(void);
extern unsigned pxa27x_get_clk_frequency_khz(int);
extern void __init pxa27x_init_irq(void);
extern void __init pxa27x_map_io(void);
#define pxa3xx_handle_irq ichp_handle_irq
extern int __init pxa3xx_clocks_init(void);
extern void __init pxa3xx_dt_init_irq(void);
extern void __init pxa3xx_init_irq(void);
extern void __init pxa3xx_map_io(void);

2
arch/arm/mach-pxa/irq.c
View File

@ -138,7 +138,7 @@ static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
return 0;
}
static struct irq_domain_ops pxa_irq_ops = {
static const struct irq_domain_ops pxa_irq_ops = {
.map = pxa_irq_map,
.xlate = irq_domain_xlate_onecell,
};

4
arch/arm/mach-pxa/lubbock.c
View File

@ -57,7 +57,6 @@
#include <mach/smemc.h>
#include "generic.h"
#include "clock.h"
#include "devices.h"
static unsigned long lubbock_pin_config[] __initdata = {
@ -102,6 +101,9 @@ static unsigned long lubbock_pin_config[] __initdata = {
GPIO6_MMC_CLK,
GPIO8_MMC_CS0,
/* SA1111 chip */
GPIO11_3_6MHz,
/* wakeup */
GPIO1_GPIO | WAKEUP_ON_EDGE_RISE,
};

183
arch/arm/mach-pxa/pxa25x.c
View File

@ -38,187 +38,11 @@
#include "generic.h"
#include "devices.h"
#include "clock.h"
/*
* Various clock factors driven by the CCCR register.
*/
/* Crystal Frequency to Memory Frequency Multiplier (L) */
static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
/* Memory Frequency to Run Mode Frequency Multiplier (M) */
static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
/* Note: we store the value N * 2 here. */
static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
/* Crystal clock */
#define BASE_CLK 3686400
/*
* Get the clock frequency as reflected by CCCR and the turbo flag.
* We assume these values have been applied via a fcs.
* If info is not 0 we also display the current settings.
*/
unsigned int pxa25x_get_clk_frequency_khz(int info)
{
unsigned long cccr, turbo;
unsigned int l, L, m, M, n2, N;
cccr = CCCR;
asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
l = L_clk_mult[(cccr >> 0) & 0x1f];
m = M_clk_mult[(cccr >> 5) & 0x03];
n2 = N2_clk_mult[(cccr >> 7) & 0x07];
L = l * BASE_CLK;
M = m * L;
N = n2 * M / 2;
if(info)
{
L += 5000;
printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
L / 1000000, (L % 1000000) / 10000, l );
M += 5000;
printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
M / 1000000, (M % 1000000) / 10000, m );
N += 5000;
printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
(turbo & 1) ? "" : "in" );
}
return (turbo & 1) ? (N/1000) : (M/1000);
}
static unsigned long clk_pxa25x_mem_getrate(struct clk *clk)
{
return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK;
}
static const struct clkops clk_pxa25x_mem_ops = {
.enable = clk_dummy_enable,
.disable = clk_dummy_disable,
.getrate = clk_pxa25x_mem_getrate,
};
static const struct clkops clk_pxa25x_lcd_ops = {
.enable = clk_pxa2xx_cken_enable,
.disable = clk_pxa2xx_cken_disable,
.getrate = clk_pxa25x_mem_getrate,
};
static unsigned long gpio12_config_32k[] = {
GPIO12_32KHz,
};
static unsigned long gpio12_config_gpio[] = {
GPIO12_GPIO,
};
static void clk_gpio12_enable(struct clk *clk)
{
pxa2xx_mfp_config(gpio12_config_32k, 1);
}
static void clk_gpio12_disable(struct clk *clk)
{
pxa2xx_mfp_config(gpio12_config_gpio, 1);
}
static const struct clkops clk_pxa25x_gpio12_ops = {
.enable = clk_gpio12_enable,
.disable = clk_gpio12_disable,
};
static unsigned long gpio11_config_3m6[] = {
GPIO11_3_6MHz,
};
static unsigned long gpio11_config_gpio[] = {
GPIO11_GPIO,
};
static void clk_gpio11_enable(struct clk *clk)
{
pxa2xx_mfp_config(gpio11_config_3m6, 1);
}
static void clk_gpio11_disable(struct clk *clk)
{
pxa2xx_mfp_config(gpio11_config_gpio, 1);
}
static const struct clkops clk_pxa25x_gpio11_ops = {
.enable = clk_gpio11_enable,
.disable = clk_gpio11_disable,
};
/*
* 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
* 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
* 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
*/
/*
* PXA 2xx clock declarations.
*/
static DEFINE_PXA2_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
static DEFINE_PXA2_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
static DEFINE_PXA2_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
static DEFINE_PXA2_CKEN(pxa25x_stuart, STUART, 14745600, 1);
static DEFINE_PXA2_CKEN(pxa25x_usb, USB, 47923000, 5);
static DEFINE_PXA2_CKEN(pxa25x_mmc, MMC, 19169000, 0);
static DEFINE_PXA2_CKEN(pxa25x_i2c, I2C, 31949000, 0);
static DEFINE_PXA2_CKEN(pxa25x_ssp, SSP, 3686400, 0);
static DEFINE_PXA2_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
static DEFINE_PXA2_CKEN(pxa25x_assp, ASSP, 3686400, 0);
static DEFINE_PXA2_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
static DEFINE_PXA2_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
static DEFINE_PXA2_CKEN(pxa25x_ac97, AC97, 24576000, 0);
static DEFINE_PXA2_CKEN(pxa25x_i2s, I2S, 14745600, 0);
static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0);
static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops);
static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0);
static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0);
static struct clk_lookup pxa25x_clkregs[] = {
INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
INIT_CLKREG(&clk_pxa25x_ffuart, "pxa2xx-uart.0", NULL),
INIT_CLKREG(&clk_pxa25x_btuart, "pxa2xx-uart.1", NULL),
INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-uart.2", NULL),
INIT_CLKREG(&clk_pxa25x_usb, "pxa25x-udc", NULL),
INIT_CLKREG(&clk_pxa25x_mmc, "pxa2xx-mci.0", NULL),
INIT_CLKREG(&clk_pxa25x_i2c, "pxa2xx-i2c.0", NULL),
INIT_CLKREG(&clk_pxa25x_ssp, "pxa25x-ssp.0", NULL),
INIT_CLKREG(&clk_pxa25x_nssp, "pxa25x-nssp.1", NULL),
INIT_CLKREG(&clk_pxa25x_assp, "pxa25x-nssp.2", NULL),
INIT_CLKREG(&clk_pxa25x_pwm0, "pxa25x-pwm.0", NULL),
INIT_CLKREG(&clk_pxa25x_pwm1, "pxa25x-pwm.1", NULL),
INIT_CLKREG(&clk_pxa25x_i2s, "pxa2xx-i2s", NULL),
INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-ir", "UARTCLK"),
INIT_CLKREG(&clk_pxa25x_ficp, "pxa2xx-ir", "FICPCLK"),
INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"),
INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
#ifdef CONFIG_CPU_PXA26x
INIT_CLKREG(&clk_dummy, "pxa26x-gpio", NULL),
#else
INIT_CLKREG(&clk_dummy, "pxa25x-gpio", NULL),
#endif
INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
};
static struct clk_lookup pxa25x_hwuart_clkreg =
INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
#ifdef CONFIG_PM
#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
@ -374,8 +198,6 @@ static int __init pxa25x_init(void)
reset_status = RCSR;
clkdev_add_table(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));
if ((ret = pxa_init_dma(IRQ_DMA, 16)))
return ret;
@ -383,7 +205,6 @@ static int __init pxa25x_init(void)
register_syscore_ops(&pxa_irq_syscore_ops);
register_syscore_ops(&pxa2xx_mfp_syscore_ops);
register_syscore_ops(&pxa2xx_clock_syscore_ops);
pxa_register_device(&pxa25x_device_gpio, &pxa25x_gpio_info);
ret = platform_add_devices(pxa25x_devices,
@ -392,10 +213,6 @@ static int __init pxa25x_init(void)
return ret;
}
/* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
if (cpu_is_pxa255())
clkdev_add(&pxa25x_hwuart_clkreg);
return ret;
}

182
arch/arm/mach-pxa/pxa27x.c
View File

@ -37,7 +37,8 @@
#include "generic.h"
#include "devices.h"
#include "clock.h"
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
void pxa27x_clear_otgph(void)
{
@ -73,174 +74,6 @@ void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio)
}
EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset);
/* Crystal clock: 13MHz */
#define BASE_CLK 13000000
/*
* Get the clock frequency as reflected by CCSR and the turbo flag.
* We assume these values have been applied via a fcs.
* If info is not 0 we also display the current settings.
*/
unsigned int pxa27x_get_clk_frequency_khz(int info)
{
unsigned long ccsr, clkcfg;
unsigned int l, L, m, M, n2, N, S;
int cccr_a, t, ht, b;
ccsr = CCSR;
cccr_a = CCCR & (1 << 25);
/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
t = clkcfg & (1 << 0);
ht = clkcfg & (1 << 2);
b = clkcfg & (1 << 3);
l = ccsr & 0x1f;
n2 = (ccsr>>7) & 0xf;
m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
L = l * BASE_CLK;
N = (L * n2) / 2;
M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
S = (b) ? L : (L/2);
if (info) {
printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
L / 1000000, (L % 1000000) / 10000, l );
printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
(t) ? "" : "in" );
printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
M / 1000000, (M % 1000000) / 10000, m );
printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
S / 1000000, (S % 1000000) / 10000 );
}
return (t) ? (N/1000) : (L/1000);
}
/*
* Return the current mem clock frequency as reflected by CCCR[A], B, and L
*/
static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
{
unsigned long ccsr, clkcfg;
unsigned int l, L, m, M;
int cccr_a, b;
ccsr = CCSR;
cccr_a = CCCR & (1 << 25);
/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
b = clkcfg & (1 << 3);
l = ccsr & 0x1f;
m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
L = l * BASE_CLK;
M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
return M;
}
static const struct clkops clk_pxa27x_mem_ops = {
.enable = clk_dummy_enable,
.disable = clk_dummy_disable,
.getrate = clk_pxa27x_mem_getrate,
};
/*
* Return the current LCD clock frequency in units of 10kHz as
*/
static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
{
unsigned long ccsr;
unsigned int l, L, k, K;
ccsr = CCSR;
l = ccsr & 0x1f;
k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
L = l * BASE_CLK;
K = L / k;
return (K / 10000);
}
static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
{
return pxa27x_get_lcdclk_frequency_10khz() * 10000;
}
static const struct clkops clk_pxa27x_lcd_ops = {
.enable = clk_pxa2xx_cken_enable,
.disable = clk_pxa2xx_cken_disable,
.getrate = clk_pxa27x_lcd_getrate,
};
static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);
static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);
static struct clk_lookup pxa27x_clkregs[] = {
INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
INIT_CLKREG(&clk_dummy, "pxa27x-gpio", NULL),
INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
};
#ifdef CONFIG_PM
#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
@ -466,8 +299,6 @@ static int __init pxa27x_init(void)
reset_status = RCSR;
clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
if ((ret = pxa_init_dma(IRQ_DMA, 32)))
return ret;
@ -475,10 +306,13 @@ static int __init pxa27x_init(void)
register_syscore_ops(&pxa_irq_syscore_ops);
register_syscore_ops(&pxa2xx_mfp_syscore_ops);
register_syscore_ops(&pxa2xx_clock_syscore_ops);
pxa_register_device(&pxa27x_device_gpio, &pxa27x_gpio_info);
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
if (!of_have_populated_dt()) {
pxa_register_device(&pxa27x_device_gpio,
&pxa27x_gpio_info);
ret = platform_add_devices(devices,
ARRAY_SIZE(devices));
}
}
return ret;

20
arch/arm/mach-pxa/pxa300.c
View File

@ -22,7 +22,6 @@
#include "generic.h"
#include "devices.h"
#include "clock.h"
static struct mfp_addr_map pxa300_mfp_addr_map[] __initdata = {
@ -84,32 +83,15 @@ static struct mfp_addr_map pxa310_mfp_addr_map[] __initdata = {
MFP_ADDR_END,
};
static DEFINE_PXA3_CKEN(common_nand, NAND, 156000000, 0);
static DEFINE_PXA3_CKEN(gcu, PXA300_GCU, 0, 0);
static struct clk_lookup common_clkregs[] = {
INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", NULL),
INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL),
};
static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0);
static struct clk_lookup pxa310_clkregs[] = {
INIT_CLKREG(&clk_pxa310_mmc3, "pxa2xx-mci.2", NULL),
};
static int __init pxa300_init(void)
{
if (cpu_is_pxa300() || cpu_is_pxa310()) {
mfp_init_base(io_p2v(MFPR_BASE));
mfp_init_addr(pxa300_mfp_addr_map);
clkdev_add_table(ARRAY_AND_SIZE(common_clkregs));
}
if (cpu_is_pxa310()) {
if (cpu_is_pxa310())
mfp_init_addr(pxa310_mfp_addr_map);
clkdev_add_table(ARRAY_AND_SIZE(pxa310_clkregs));
}
return 0;
}

10
arch/arm/mach-pxa/pxa320.c
View File

@ -22,7 +22,6 @@
#include "generic.h"
#include "devices.h"
#include "clock.h"
static struct mfp_addr_map pxa320_mfp_addr_map[] __initdata = {
@ -78,20 +77,11 @@ static struct mfp_addr_map pxa320_mfp_addr_map[] __initdata = {
MFP_ADDR_END,
};
static DEFINE_PXA3_CKEN(pxa320_nand, NAND, 104000000, 0);
static DEFINE_PXA3_CKEN(gcu, PXA320_GCU, 0, 0);
static struct clk_lookup pxa320_clkregs[] = {
INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", NULL),
INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL),
};
static int __init pxa320_init(void)
{
if (cpu_is_pxa320()) {
mfp_init_base(io_p2v(MFPR_BASE));
mfp_init_addr(pxa320_mfp_addr_map);
clkdev_add_table(ARRAY_AND_SIZE(pxa320_clkregs));
}
return 0;

59
arch/arm/mach-pxa/pxa3xx.c
View File

@ -37,67 +37,11 @@
#include "generic.h"
#include "devices.h"
#include "clock.h"
#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_gpio, GPIO, 13000000, 0);
static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
static struct clk_lookup pxa3xx_clkregs[] = {
INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
/* Power I2C clock is always on */
INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa3xx-ssp.0", NULL),
INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa3xx-ssp.1", NULL),
INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa3xx-ssp.2", NULL),
INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa3xx-ssp.3", NULL),
INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
INIT_CLKREG(&clk_pxa3xx_gpio, "pxa3xx-gpio", NULL),
INIT_CLKREG(&clk_pxa3xx_gpio, "pxa93x-gpio", NULL),
INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
};
#ifdef CONFIG_PM
#define ISRAM_START 0x5c000000
@ -476,8 +420,6 @@ static int __init pxa3xx_init(void)
*/
ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
if ((ret = pxa_init_dma(IRQ_DMA, 32)))
return ret;
@ -485,7 +427,6 @@ static int __init pxa3xx_init(void)
register_syscore_ops(&pxa_irq_syscore_ops);
register_syscore_ops(&pxa3xx_mfp_syscore_ops);
register_syscore_ops(&pxa3xx_clock_syscore_ops);
if (of_have_populated_dt())
return 0;

1
arch/arm/mach-pxa/raumfeld.c
View File

@ -56,7 +56,6 @@
#include "generic.h"
#include "devices.h"
#include "clock.h"
/* common GPIO definitions */

1
arch/arm/mach-pxa/tosa.c
View File

@ -58,7 +58,6 @@
#include <asm/mach/sharpsl_param.h>
#include "generic.h"
#include "clock.h"
#include "devices.h"
static unsigned long tosa_pin_config[] = {

32
drivers/clk/pxa/clk-pxa27x.c
View File

@ -353,6 +353,34 @@ static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw)
PARENTS(clk_pxa27x_memory) = { "osc_13mhz", "system_bus", "run" };
MUX_RO_RATE_RO_OPS(clk_pxa27x_memory, "memory");
#define DUMMY_CLK(_con_id, _dev_id, _parent) \
{ .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
struct dummy_clk {
const char *con_id;
const char *dev_id;
const char *parent;
};
static struct dummy_clk dummy_clks[] __initdata = {
DUMMY_CLK(NULL, "pxa27x-gpio", "osc_32_768khz"),
DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
};
static void __init pxa27x_dummy_clocks_init(void)
{
struct clk *clk;
struct dummy_clk *d;
const char *name;
int i;
for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
d = &dummy_clks[i];
name = d->dev_id ? d->dev_id : d->con_id;
clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
clk_register_clkdev(clk, d->con_id, d->dev_id);
}
}
static void __init pxa27x_base_clocks_init(void)
{
pxa27x_register_plls();
@ -362,12 +390,12 @@ static void __init pxa27x_base_clocks_init(void)
clk_register_clk_pxa27x_lcd_base();
}
static int __init pxa27x_clocks_init(void)
int __init pxa27x_clocks_init(void)
{
pxa27x_base_clocks_init();
pxa27x_dummy_clocks_init();
return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks));
}
postcore_initcall(pxa27x_clocks_init);
static void __init pxa27x_dt_clocks_init(struct device_node *np)
{