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MIPS: RM7000: Add support for tertiary cache
Add support for the external T-cache interface. Allow for platform independent size probing from 512KB to 8MB in powers of two. Signed-off-by: Ricardo Mendoza <ricmm@gentoo.org> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1477/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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58a6d45193
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2 changed files with 128 additions and 21 deletions
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@ -62,6 +62,8 @@
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* RM7000-specific cacheops
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* RM7000-specific cacheops
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*/
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*/
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#define Page_Invalidate_T 0x16
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#define Page_Invalidate_T 0x16
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#define Index_Store_Tag_T 0x0a
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#define Index_Load_Tag_T 0x06
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/*
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/*
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* R10000-specific cacheops
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* R10000-specific cacheops
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@ -16,6 +16,7 @@
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#include <asm/cacheops.h>
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#include <asm/cacheops.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsregs.h>
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#include <asm/processor.h>
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#include <asm/processor.h>
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#include <asm/sections.h>
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#include <asm/cacheflush.h> /* for run_uncached() */
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#include <asm/cacheflush.h> /* for run_uncached() */
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/* Primary cache parameters. */
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/* Primary cache parameters. */
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@ -25,11 +26,15 @@
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/* Secondary cache parameters. */
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/* Secondary cache parameters. */
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#define scache_size (256*1024) /* Fixed to 256KiB on RM7000 */
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#define scache_size (256*1024) /* Fixed to 256KiB on RM7000 */
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/* Tertiary cache parameters */
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#define tc_lsize 32
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extern unsigned long icache_way_size, dcache_way_size;
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extern unsigned long icache_way_size, dcache_way_size;
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unsigned long tcache_size;
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#include <asm/r4kcache.h>
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#include <asm/r4kcache.h>
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static int rm7k_tcache_enabled;
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static int rm7k_tcache_init;
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/*
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/*
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* Writeback and invalidate the primary cache dcache before DMA.
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* Writeback and invalidate the primary cache dcache before DMA.
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@ -46,7 +51,7 @@ static void rm7k_sc_wback_inv(unsigned long addr, unsigned long size)
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blast_scache_range(addr, addr + size);
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blast_scache_range(addr, addr + size);
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if (!rm7k_tcache_enabled)
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if (!rm7k_tcache_init)
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return;
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return;
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a = addr & ~(tc_pagesize - 1);
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a = addr & ~(tc_pagesize - 1);
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@ -70,7 +75,7 @@ static void rm7k_sc_inv(unsigned long addr, unsigned long size)
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blast_inv_scache_range(addr, addr + size);
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blast_inv_scache_range(addr, addr + size);
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if (!rm7k_tcache_enabled)
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if (!rm7k_tcache_init)
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return;
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return;
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a = addr & ~(tc_pagesize - 1);
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a = addr & ~(tc_pagesize - 1);
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@ -83,6 +88,45 @@ static void rm7k_sc_inv(unsigned long addr, unsigned long size)
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}
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}
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}
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}
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static void blast_rm7k_tcache(void)
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{
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unsigned long start = CKSEG0ADDR(0);
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unsigned long end = start + tcache_size;
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write_c0_taglo(0);
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while (start < end) {
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cache_op(Page_Invalidate_T, start);
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start += tc_pagesize;
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}
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}
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/*
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* This function is executed in uncached address space.
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*/
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static __cpuinit void __rm7k_tc_enable(void)
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{
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int i;
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set_c0_config(RM7K_CONF_TE);
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write_c0_taglo(0);
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write_c0_taghi(0);
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for (i = 0; i < tcache_size; i += tc_lsize)
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cache_op(Index_Store_Tag_T, CKSEG0ADDR(i));
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}
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static __cpuinit void rm7k_tc_enable(void)
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{
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if (read_c0_config() & RM7K_CONF_TE)
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return;
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BUG_ON(tcache_size == 0);
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run_uncached(__rm7k_tc_enable);
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}
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/*
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/*
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* This function is executed in uncached address space.
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* This function is executed in uncached address space.
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*/
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*/
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@ -104,13 +148,29 @@ static __cpuinit void rm7k_sc_enable(void)
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if (read_c0_config() & RM7K_CONF_SE)
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if (read_c0_config() & RM7K_CONF_SE)
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return;
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return;
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printk(KERN_INFO "Enabling secondary cache...\n");
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pr_info("Enabling secondary cache...\n");
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run_uncached(__rm7k_sc_enable);
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run_uncached(__rm7k_sc_enable);
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if (rm7k_tcache_init)
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rm7k_tc_enable();
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}
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static void rm7k_tc_disable(void)
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{
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unsigned long flags;
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local_irq_save(flags);
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blast_rm7k_tcache();
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clear_c0_config(RM7K_CONF_TE);
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local_irq_save(flags);
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}
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}
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static void rm7k_sc_disable(void)
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static void rm7k_sc_disable(void)
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{
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{
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clear_c0_config(RM7K_CONF_SE);
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clear_c0_config(RM7K_CONF_SE);
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if (rm7k_tcache_init)
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rm7k_tc_disable();
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}
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}
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static struct bcache_ops rm7k_sc_ops = {
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static struct bcache_ops rm7k_sc_ops = {
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@ -120,6 +180,52 @@ static struct bcache_ops rm7k_sc_ops = {
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.bc_inv = rm7k_sc_inv
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.bc_inv = rm7k_sc_inv
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};
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};
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/*
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* This is a probing function like the one found in c-r4k.c, we look for the
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* wrap around point with different addresses.
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*/
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static __cpuinit void __probe_tcache(void)
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{
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unsigned long flags, addr, begin, end, pow2;
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begin = (unsigned long) &_stext;
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begin &= ~((8 * 1024 * 1024) - 1);
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end = begin + (8 * 1024 * 1024);
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local_irq_save(flags);
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set_c0_config(RM7K_CONF_TE);
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/* Fill size-multiple lines with a valid tag */
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pow2 = (256 * 1024);
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for (addr = begin; addr <= end; addr = (begin + pow2)) {
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unsigned long *p = (unsigned long *) addr;
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__asm__ __volatile__("nop" : : "r" (*p));
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pow2 <<= 1;
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}
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/* Load first line with a 0 tag, to check after */
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write_c0_taglo(0);
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write_c0_taghi(0);
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cache_op(Index_Store_Tag_T, begin);
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/* Look for the wrap-around */
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pow2 = (512 * 1024);
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for (addr = begin + (512 * 1024); addr <= end; addr = begin + pow2) {
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cache_op(Index_Load_Tag_T, addr);
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if (!read_c0_taglo())
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break;
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pow2 <<= 1;
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}
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addr -= begin;
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tcache_size = addr;
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clear_c0_config(RM7K_CONF_TE);
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local_irq_restore(flags);
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}
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void __cpuinit rm7k_sc_init(void)
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void __cpuinit rm7k_sc_init(void)
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{
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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struct cpuinfo_mips *c = ¤t_cpu_data;
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@ -139,27 +245,26 @@ void __cpuinit rm7k_sc_init(void)
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if (!(config & RM7K_CONF_SE))
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if (!(config & RM7K_CONF_SE))
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rm7k_sc_enable();
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rm7k_sc_enable();
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bcops = &rm7k_sc_ops;
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/*
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/*
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* While we're at it let's deal with the tertiary cache.
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* While we're at it let's deal with the tertiary cache.
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*/
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*/
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if (!(config & RM7K_CONF_TC)) {
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/*
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rm7k_tcache_init = 0;
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* We can't enable the L3 cache yet. There may be board-specific
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tcache_size = 0;
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* magic necessary to turn it on, and blindly asking the CPU to
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* start using it would may give cache errors.
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*
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* Also, board-specific knowledge may allow us to use the
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* CACHE Flash_Invalidate_T instruction if the tag RAM supports
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* it, and may specify the size of the L3 cache so we don't have
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* to probe it.
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*/
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printk(KERN_INFO "Tertiary cache present, %s enabled\n",
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(config & RM7K_CONF_TE) ? "already" : "not (yet)");
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if ((config & RM7K_CONF_TE))
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if (config & RM7K_CONF_TC)
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rm7k_tcache_enabled = 1;
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return;
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}
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bcops = &rm7k_sc_ops;
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/*
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* No efficient way to ask the hardware for the size of the tcache,
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* so must probe for it.
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*/
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run_uncached(__probe_tcache);
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rm7k_tc_enable();
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rm7k_tcache_init = 1;
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c->tcache.linesz = tc_lsize;
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c->tcache.ways = 1;
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pr_info("Tertiary cache size %ldK.\n", (tcache_size >> 10));
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}
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}
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