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ARM: EXYNOS: Modified files for SPI consolidation work
As SPI platform devices are consolidated to plat-samsung, some corresponding changes are required in the respective machine folder. Setup files are added for SPI GPIO configurations and platform data initialization. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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6640790ce2
commit
74ac23a3e4
7 changed files with 147 additions and 30 deletions
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@ -148,6 +148,11 @@ config EXYNOS4_SETUP_USB_PHY
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help
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Common setup code for USB PHY controller
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config EXYNOS4_SETUP_SPI
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bool
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help
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Common setup code for SPI GPIO configurations.
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# machine support
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if ARCH_EXYNOS4
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@ -60,3 +60,4 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
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obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
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obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
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obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o
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obj-$(CONFIG_EXYNOS4_SETUP_SPI) += setup-spi.o
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@ -1109,36 +1109,6 @@ static struct clksrc_clk clksrcs[] = {
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.sources = &clkset_group,
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.reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
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.reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.0",
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.enable = exynos4_clksrc_mask_peril1_ctrl,
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.ctrlbit = (1 << 16),
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},
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.sources = &clkset_group,
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.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
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.reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.1",
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.enable = exynos4_clksrc_mask_peril1_ctrl,
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.ctrlbit = (1 << 20),
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},
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.sources = &clkset_group,
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.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
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.reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.2",
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.enable = exynos4_clksrc_mask_peril1_ctrl,
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.ctrlbit = (1 << 24),
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},
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.sources = &clkset_group,
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.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
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.reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_fimg2d",
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@ -1257,6 +1227,42 @@ static struct clksrc_clk clk_sclk_mmc3 = {
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.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
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};
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static struct clksrc_clk clk_sclk_spi0 = {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.0",
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.enable = exynos4_clksrc_mask_peril1_ctrl,
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.ctrlbit = (1 << 16),
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},
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.sources = &clkset_group,
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.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
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.reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
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};
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static struct clksrc_clk clk_sclk_spi1 = {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.1",
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.enable = exynos4_clksrc_mask_peril1_ctrl,
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.ctrlbit = (1 << 20),
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},
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.sources = &clkset_group,
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.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
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.reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
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};
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static struct clksrc_clk clk_sclk_spi2 = {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.2",
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.enable = exynos4_clksrc_mask_peril1_ctrl,
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.ctrlbit = (1 << 24),
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},
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.sources = &clkset_group,
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.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
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.reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
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};
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/* Clock initialization code */
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static struct clksrc_clk *sysclks[] = {
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&clk_mout_apll,
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@ -1305,6 +1311,10 @@ static struct clksrc_clk *clksrc_cdev[] = {
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&clk_sclk_mmc1,
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&clk_sclk_mmc2,
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&clk_sclk_mmc3,
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&clk_sclk_spi0,
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&clk_sclk_spi1,
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&clk_sclk_spi2,
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};
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static struct clk_lookup exynos4_clk_lookup[] = {
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@ -1318,6 +1328,9 @@ static struct clk_lookup exynos4_clk_lookup[] = {
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CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
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CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
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CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
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CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk),
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CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk),
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CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk),
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};
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static int xtal_rate;
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@ -72,6 +72,9 @@
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#define IRQ_IIC5 IRQ_SPI(63)
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#define IRQ_IIC6 IRQ_SPI(64)
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#define IRQ_IIC7 IRQ_SPI(65)
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#define IRQ_SPI0 IRQ_SPI(66)
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#define IRQ_SPI1 IRQ_SPI(67)
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#define IRQ_SPI2 IRQ_SPI(68)
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#define IRQ_USB_HOST IRQ_SPI(70)
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#define IRQ_USB_HSOTG IRQ_SPI(71)
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@ -87,6 +87,10 @@
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#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
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#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
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#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
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#define EXYNOS4_PA_SPI0 0x13920000
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#define EXYNOS4_PA_SPI1 0x13930000
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#define EXYNOS4_PA_SPI2 0x13940000
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#define EXYNOS4_PA_GPIO1 0x11400000
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#define EXYNOS4_PA_GPIO2 0x11000000
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@ -148,6 +152,9 @@
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#define S3C_PA_RTC EXYNOS4_PA_RTC
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#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
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#define S3C_PA_UART EXYNOS4_PA_UART
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#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
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#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
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#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
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#define S5P_PA_CHIPID EXYNOS4_PA_CHIPID
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#define S5P_PA_EHCI EXYNOS4_PA_EHCI
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16
arch/arm/mach-exynos/include/mach/spi-clocks.h
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16
arch/arm/mach-exynos/include/mach/spi-clocks.h
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@ -0,0 +1,16 @@
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/* linux/arch/arm/mach-exynos4/include/mach/spi-clocks.h
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*
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* Copyright (C) 2011 Samsung Electronics Co. Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_SPI_CLKS_H
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#define __ASM_ARCH_SPI_CLKS_H __FILE__
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/* Must source from SCLK_SPI */
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#define EXYNOS4_SPI_SRCCLK_SCLK 0
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#endif /* __ASM_ARCH_SPI_CLKS_H */
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arch/arm/mach-exynos/setup-spi.c
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72
arch/arm/mach-exynos/setup-spi.c
Normal file
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@ -0,0 +1,72 @@
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/* linux/arch/arm/mach-exynos4/setup-spi.c
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*
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* Copyright (C) 2011 Samsung Electronics Ltd.
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* http://www.samsung.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <plat/gpio-cfg.h>
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#include <plat/s3c64xx-spi.h>
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#ifdef CONFIG_S3C64XX_DEV_SPI0
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struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
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.fifo_lvl_mask = 0x1ff,
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.rx_lvl_offset = 15,
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.high_speed = 1,
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.clk_from_cmu = true,
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.tx_st_done = 25,
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};
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int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
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{
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s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
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s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP);
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s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
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S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
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return 0;
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}
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#endif
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#ifdef CONFIG_S3C64XX_DEV_SPI1
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struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
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.fifo_lvl_mask = 0x7f,
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.rx_lvl_offset = 15,
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.high_speed = 1,
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.clk_from_cmu = true,
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.tx_st_done = 25,
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};
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int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
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{
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s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
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s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP);
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s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
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S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
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return 0;
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}
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#endif
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#ifdef CONFIG_S3C64XX_DEV_SPI2
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struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
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.fifo_lvl_mask = 0x7f,
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.rx_lvl_offset = 15,
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.high_speed = 1,
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.clk_from_cmu = true,
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.tx_st_done = 25,
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};
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int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
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{
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s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));
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s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP);
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s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
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S3C_GPIO_SFN(5), S3C_GPIO_PULL_UP);
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return 0;
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}
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#endif
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