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powerpc/8xx: don't use r12/SPRN_SPRG_SCRATCH2 in TLB Miss handlers
This patch reworks the TLB Miss handler in order to not use r12 register, hence avoiding having to save it into SPRN_SPRG_SCRATCH2. In the DAR Fixup code we can now use SPRN_M_TW, freeing SPRN_SPRG_SCRATCH2. Then SPRN_SPRG_SCRATCH2 may be used for something else in the future. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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parent
55c8fc3f49
commit
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1 changed files with 49 additions and 61 deletions
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@ -302,90 +302,87 @@ SystemCall:
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*/
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#ifdef CONFIG_8xx_CPU15
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#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \
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addi tmp, addr, PAGE_SIZE; \
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tlbie tmp; \
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addi tmp, addr, -PAGE_SIZE; \
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tlbie tmp
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#define INVALIDATE_ADJACENT_PAGES_CPU15(addr) \
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addi addr, addr, PAGE_SIZE; \
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tlbie addr; \
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addi addr, addr, -(PAGE_SIZE << 1); \
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tlbie addr; \
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addi addr, addr, PAGE_SIZE
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#else
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#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr)
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#define INVALIDATE_ADJACENT_PAGES_CPU15(addr)
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#endif
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InstructionTLBMiss:
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mtspr SPRN_SPRG_SCRATCH0, r10
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#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP)
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mtspr SPRN_SPRG_SCRATCH1, r11
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#ifdef ITLB_MISS_KERNEL
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mtspr SPRN_SPRG_SCRATCH2, r12
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#endif
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/* If we are faulting a kernel address, we have to use the
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* kernel page tables.
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*/
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mfspr r10, SPRN_SRR0 /* Get effective address of fault */
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INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10)
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INVALIDATE_ADJACENT_PAGES_CPU15(r10)
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mtspr SPRN_MD_EPN, r10
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/* Only modules will cause ITLB Misses as we always
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* pin the first 8MB of kernel memory */
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#ifdef ITLB_MISS_KERNEL
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mfcr r12
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mfcr r11
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#if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
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andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
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cmpi cr0, r10, 0 /* Address >= 0x80000000 */
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#else
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rlwinm r11, r10, 16, 0xfff8
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cmpli cr0, r11, PAGE_OFFSET@h
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rlwinm r10, r10, 16, 0xfff8
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cmpli cr0, r10, PAGE_OFFSET@h
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#ifndef CONFIG_PIN_TLB_TEXT
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/* It is assumed that kernel code fits into the first 8M page */
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0: cmpli cr7, r11, (PAGE_OFFSET + 0x0800000)@h
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0: cmpli cr7, r10, (PAGE_OFFSET + 0x0800000)@h
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patch_site 0b, patch__itlbmiss_linmem_top
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#endif
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#endif
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#endif
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mfspr r11, SPRN_M_TWB /* Get level 1 table */
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mfspr r10, SPRN_M_TWB /* Get level 1 table */
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#ifdef ITLB_MISS_KERNEL
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#if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
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beq+ 3f
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bge+ 3f
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#else
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blt+ 3f
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#endif
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#ifndef CONFIG_PIN_TLB_TEXT
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blt cr7, ITLBMissLinear
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#endif
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rlwinm r11, r11, 0, 20, 31
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oris r11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha
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rlwinm r10, r10, 0, 20, 31
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oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
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3:
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#endif
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lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
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lwz r10, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */
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mtspr SPRN_MI_TWC, r10 /* Set segment attributes */
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mtspr SPRN_MD_TWC, r11
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mtspr SPRN_MD_TWC, r10
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mfspr r10, SPRN_MD_TWC
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lwz r10, 0(r10) /* Get the pte */
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#ifdef ITLB_MISS_KERNEL
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mtcr r12
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mtcr r11
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#endif
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/* Load the MI_TWC with the attributes for this "segment." */
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mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
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#ifdef CONFIG_SWAP
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rlwinm r11, r10, 32-5, _PAGE_PRESENT
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and r11, r11, r10
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rlwimi r10, r11, 0, _PAGE_PRESENT
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#endif
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li r11, RPN_PATTERN | 0x200
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/* The Linux PTE won't go exactly into the MMU TLB.
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* Software indicator bits 20 and 23 must be clear.
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* Software indicator bits 22, 24, 25, 26, and 27 must be
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* set. All other Linux PTE bits control the behavior
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* of the MMU.
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*/
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rlwimi r11, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */
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rlwimi r10, r11, 0, 0x0ff0 /* Set 22, 24-27, clear 20,23 */
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rlwimi r10, r10, 0, 0x0f00 /* Clear bits 20-23 */
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rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */
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ori r10, r10, RPN_PATTERN | 0x200 /* Set 22 and 24-27 */
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mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
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/* Restore registers */
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0: mfspr r10, SPRN_SPRG_SCRATCH0
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#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP)
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mfspr r11, SPRN_SPRG_SCRATCH1
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#ifdef ITLB_MISS_KERNEL
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mfspr r12, SPRN_SPRG_SCRATCH2
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#endif
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rfi
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patch_site 0b, patch__itlbmiss_exit_1
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@ -396,9 +393,8 @@ InstructionTLBMiss:
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addi r10, r10, 1
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stw r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
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mfspr r10, SPRN_SPRG_SCRATCH0
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#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP)
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mfspr r11, SPRN_SPRG_SCRATCH1
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#ifdef ITLB_MISS_KERNEL
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mfspr r12, SPRN_SPRG_SCRATCH2
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#endif
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rfi
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#endif
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@ -407,40 +403,37 @@ InstructionTLBMiss:
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DataStoreTLBMiss:
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mtspr SPRN_SPRG_SCRATCH0, r10
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mtspr SPRN_SPRG_SCRATCH1, r11
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mtspr SPRN_SPRG_SCRATCH2, r12
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mfcr r12
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mfcr r11
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/* If we are faulting a kernel address, we have to use the
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* kernel page tables.
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*/
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mfspr r10, SPRN_MD_EPN
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rlwinm r11, r10, 16, 0xfff8
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cmpli cr0, r11, PAGE_OFFSET@h
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mfspr r11, SPRN_M_TWB /* Get level 1 table */
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blt+ 3f
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rlwinm r11, r10, 16, 0xfff8
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rlwinm r10, r10, 16, 0xfff8
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cmpli cr0, r10, PAGE_OFFSET@h
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#ifndef CONFIG_PIN_TLB_IMMR
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cmpli cr0, r11, VIRT_IMMR_BASE@h
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cmpli cr6, r10, VIRT_IMMR_BASE@h
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#endif
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0: cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
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0: cmpli cr7, r10, (PAGE_OFFSET + 0x1800000)@h
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patch_site 0b, patch__dtlbmiss_linmem_top
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mfspr r10, SPRN_M_TWB /* Get level 1 table */
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blt+ 3f
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#ifndef CONFIG_PIN_TLB_IMMR
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0: beq- DTLBMissIMMR
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0: beq- cr6, DTLBMissIMMR
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patch_site 0b, patch__dtlbmiss_immr_jmp
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#endif
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blt cr7, DTLBMissLinear
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mfspr r11, SPRN_M_TWB /* Get level 1 table */
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rlwinm r11, r11, 0, 20, 31
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oris r11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha
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rlwinm r10, r10, 0, 20, 31
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oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
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3:
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lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
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mtcr r11
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lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */
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mtspr SPRN_MD_TWC, r11
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mfspr r10, SPRN_MD_TWC
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lwz r10, 0(r10) /* Get the pte */
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mtcr r12
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/* Insert the Guarded flag into the TWC from the Linux PTE.
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* It is bit 27 of both the Linux PTE and the TWC (at least
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* I got that right :-). It will be better when we can put
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@ -478,7 +471,6 @@ DataStoreTLBMiss:
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0: mfspr r10, SPRN_SPRG_SCRATCH0
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mfspr r11, SPRN_SPRG_SCRATCH1
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mfspr r12, SPRN_SPRG_SCRATCH2
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rfi
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patch_site 0b, patch__dtlbmiss_exit_1
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@ -489,7 +481,6 @@ DataStoreTLBMiss:
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stw r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)
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mfspr r10, SPRN_SPRG_SCRATCH0
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mfspr r11, SPRN_SPRG_SCRATCH1
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mfspr r12, SPRN_SPRG_SCRATCH2
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rfi
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#endif
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@ -597,7 +588,7 @@ InstructionBreakpoint:
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* not enough space in the DataStoreTLBMiss area.
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*/
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DTLBMissIMMR:
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mtcr r12
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mtcr r11
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/* Set 512k byte guarded page and mark it valid */
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li r10, MD_PS512K | MD_GUARDED | MD_SVALID
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mtspr SPRN_MD_TWC, r10
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@ -612,16 +603,15 @@ DTLBMissIMMR:
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0: mfspr r10, SPRN_SPRG_SCRATCH0
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mfspr r11, SPRN_SPRG_SCRATCH1
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mfspr r12, SPRN_SPRG_SCRATCH2
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rfi
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patch_site 0b, patch__dtlbmiss_exit_2
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DTLBMissLinear:
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mtcr r12
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mtcr r11
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/* Set 8M byte page and mark it valid */
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li r11, MD_PS8MEG | MD_SVALID
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mtspr SPRN_MD_TWC, r11
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rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
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rlwinm r10, r10, 20, 0x0f800000 /* 8xx supports max 256Mb RAM */
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ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
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_PAGE_PRESENT
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mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
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@ -631,24 +621,22 @@ DTLBMissLinear:
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0: mfspr r10, SPRN_SPRG_SCRATCH0
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mfspr r11, SPRN_SPRG_SCRATCH1
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mfspr r12, SPRN_SPRG_SCRATCH2
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rfi
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patch_site 0b, patch__dtlbmiss_exit_3
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#ifndef CONFIG_PIN_TLB_TEXT
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ITLBMissLinear:
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mtcr r12
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mtcr r11
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/* Set 8M byte page and mark it valid */
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li r11, MI_PS8MEG | MI_SVALID
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mtspr SPRN_MI_TWC, r11
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rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
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rlwinm r10, r10, 20, 0x0f800000 /* 8xx supports max 256Mb RAM */
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ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
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_PAGE_PRESENT
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mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
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0: mfspr r10, SPRN_SPRG_SCRATCH0
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mfspr r11, SPRN_SPRG_SCRATCH1
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mfspr r12, SPRN_SPRG_SCRATCH2
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rfi
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patch_site 0b, patch__itlbmiss_exit_2
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#endif
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/* define if you don't want to use self modifying code */
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#define NO_SELF_MODIFYING_CODE
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FixupDAR:/* Entry point for dcbx workaround. */
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mtspr SPRN_SPRG_SCRATCH2, r10
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mtspr SPRN_M_TW, r10
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/* fetch instruction from memory. */
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mfspr r10, SPRN_SRR0
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mtspr SPRN_MD_EPN, r10
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beq+ 142f
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cmpwi cr0, r10, 1964 /* Is icbi? */
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beq+ 142f
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141: mfspr r10,SPRN_SPRG_SCRATCH2
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141: mfspr r10,SPRN_M_TW
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b DARFixed /* Nope, go back to normal TLB processing */
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200:
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bne+ 143f
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subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
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143: mtdar r10 /* store faulting EA in DAR */
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mfspr r10,SPRN_SPRG_SCRATCH2
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mfspr r10,SPRN_M_TW
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b DARFixed /* Go back to normal TLB handling */
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#else
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mfctr r10
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mfdar r11
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mtctr r11 /* restore ctr reg from DAR */
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mtdar r10 /* save fault EA to DAR */
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mfspr r10,SPRN_SPRG_SCRATCH2
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mfspr r10,SPRN_M_TW
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b DARFixed /* Go back to normal TLB handling */
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/* special handling for r10,r11 since these are modified already */
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