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IOMMU Fixes for Linux v3.17-rc4
Including: * Two fixes for issues found by Coverity * Various fixes for the ARM SMMU driver * A warning fix for the FSL PAMU driver -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABAgAGBQJUEvbvAAoJECvwRC2XARrjTbgQAKfSftH7StWiVgR3MyiO1JVy c0AAImQZ2rk7LO1R3xMxDn6DZD9sLTJNy9ogWr5YEyqMIVOdJt7hicrbgo0gGSS1 zU8numZweMPD7tzvFk93GjsSEdy+T4PYpmR2KncYB2OQ3szMd7GqooKohp1P1BfC 3fb9k9rjstnZXn0nKN6KxZ7QWaGme8e02cRz+5U+8N+AYHmV6ZcUumqig6KmYjuP AtyQz2Sj8v2VAnVr+3yOz/bBLBSRChfc1q9aFSrD3mLhTLlJ7uk0+4NviGsPbZww vGvWqy3w8aLzRDA9x+036FU6BoBQtaRdF/JCCPw8yOmfmUi6hA6kvTJbfgxIJPRK ZZM6KBdPWfo8y83dVXsT3NpineA622VhstZVT7NGczDVtimnxI6wjLlNUj0ve4g5 AbaujBbnRtBclEWk23AjLpoiEA3iGw4putvCxFlWaclh0AEX0wx4W2scqCtF6hP5 w3d6HiuYnB5lKl+IMb1jYvybRLc1CrXbnsJGsyjjfYMztv31pY3s0gO9xAQldLCV 8Ah0njJ1GDKwXcmNUAgLcgrnmLIPat6IMT44vH15OYgjczsx0mN8ZChto24iOwx1 ZrSfBWQ2IVylHyIuGrIe6C1+HR6ixrzcOaCXJaa7cTvo7vXWL6E8KZa4uth74Jq1 VjmkefTgBjtrs656E+fr =jHx2 -----END PGP SIGNATURE----- Merge tag 'iommu-fixes-v3.17-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull iommu fixes from Joerg Roedel: - two fixes for issues found by Coverity - various fixes for the ARM SMMU driver - a warning fix for the FSL PAMU driver * tag 'iommu-fixes-v3.17-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: iommu/fsl: Fix warning resulting from adding PCI device twice iommu/arm-smmu: fix corner cases in address size calculations iommu/arm-smmu: fix decimal printf format specifiers prefixed with 0x iommu/arm-smmu: Do not access non-existing S2CR registers iommu/arm-smmu: fix s2cr and smr teardown on device detach from domain iommu/arm-smmu: remove pgtable_page_{c,d}tor() iommu/arm-smmu: fix programming of SMMU_CBn_TCR for stage 1 iommu/arm-smmu: avoid calling request_irq in atomic context iommu/vt-d: Check return value of acpi_bus_get_device() iommu/core: Make iommu_group_get_for_dev() more robust
This commit is contained in:
commit
753a6cb7e4
4 changed files with 87 additions and 61 deletions
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@ -146,6 +146,8 @@
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#define ID0_CTTW (1 << 14)
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#define ID0_CTTW (1 << 14)
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#define ID0_NUMIRPT_SHIFT 16
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#define ID0_NUMIRPT_SHIFT 16
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#define ID0_NUMIRPT_MASK 0xff
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#define ID0_NUMIRPT_MASK 0xff
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#define ID0_NUMSIDB_SHIFT 9
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#define ID0_NUMSIDB_MASK 0xf
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#define ID0_NUMSMRG_SHIFT 0
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#define ID0_NUMSMRG_SHIFT 0
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#define ID0_NUMSMRG_MASK 0xff
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#define ID0_NUMSMRG_MASK 0xff
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@ -524,9 +526,18 @@ static int register_smmu_master(struct arm_smmu_device *smmu,
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master->of_node = masterspec->np;
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master->of_node = masterspec->np;
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master->cfg.num_streamids = masterspec->args_count;
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master->cfg.num_streamids = masterspec->args_count;
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for (i = 0; i < master->cfg.num_streamids; ++i)
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for (i = 0; i < master->cfg.num_streamids; ++i) {
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master->cfg.streamids[i] = masterspec->args[i];
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u16 streamid = masterspec->args[i];
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if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) &&
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(streamid >= smmu->num_mapping_groups)) {
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dev_err(dev,
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"stream ID for master device %s greater than maximum allowed (%d)\n",
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masterspec->np->name, smmu->num_mapping_groups);
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return -ERANGE;
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}
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master->cfg.streamids[i] = streamid;
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}
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return insert_smmu_master(smmu, master);
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return insert_smmu_master(smmu, master);
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}
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}
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@ -623,7 +634,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
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if (fsr & FSR_IGN)
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if (fsr & FSR_IGN)
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dev_err_ratelimited(smmu->dev,
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dev_err_ratelimited(smmu->dev,
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"Unexpected context fault (fsr 0x%u)\n",
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"Unexpected context fault (fsr 0x%x)\n",
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fsr);
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fsr);
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fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
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fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
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@ -752,6 +763,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
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reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
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reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
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break;
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break;
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case 39:
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case 39:
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case 40:
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reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
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reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
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break;
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break;
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case 42:
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case 42:
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@ -773,6 +785,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
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reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT);
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reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT);
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break;
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break;
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case 39:
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case 39:
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case 40:
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reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT);
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reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT);
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break;
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break;
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case 42:
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case 42:
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@ -843,8 +856,11 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
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reg |= TTBCR_EAE |
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reg |= TTBCR_EAE |
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(TTBCR_SH_IS << TTBCR_SH0_SHIFT) |
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(TTBCR_SH_IS << TTBCR_SH0_SHIFT) |
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(TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) |
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(TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) |
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(TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) |
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(TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT);
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(TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
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if (!stage1)
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reg |= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
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writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
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writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
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/* MAIR0 (stage-1 only) */
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/* MAIR0 (stage-1 only) */
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@ -868,10 +884,15 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
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static int arm_smmu_init_domain_context(struct iommu_domain *domain,
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static int arm_smmu_init_domain_context(struct iommu_domain *domain,
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struct arm_smmu_device *smmu)
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struct arm_smmu_device *smmu)
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{
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{
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int irq, ret, start;
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int irq, start, ret = 0;
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unsigned long flags;
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struct arm_smmu_domain *smmu_domain = domain->priv;
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struct arm_smmu_domain *smmu_domain = domain->priv;
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struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
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struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
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spin_lock_irqsave(&smmu_domain->lock, flags);
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if (smmu_domain->smmu)
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goto out_unlock;
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if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
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if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
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/*
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/*
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* We will likely want to change this if/when KVM gets
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* We will likely want to change this if/when KVM gets
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@ -890,7 +911,7 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
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ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
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ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
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smmu->num_context_banks);
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smmu->num_context_banks);
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if (IS_ERR_VALUE(ret))
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if (IS_ERR_VALUE(ret))
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return ret;
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goto out_unlock;
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cfg->cbndx = ret;
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cfg->cbndx = ret;
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if (smmu->version == 1) {
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if (smmu->version == 1) {
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@ -900,6 +921,10 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
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cfg->irptndx = cfg->cbndx;
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cfg->irptndx = cfg->cbndx;
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}
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}
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ACCESS_ONCE(smmu_domain->smmu) = smmu;
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arm_smmu_init_context_bank(smmu_domain);
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spin_unlock_irqrestore(&smmu_domain->lock, flags);
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irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
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irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
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ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
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ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
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"arm-smmu-context-fault", domain);
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"arm-smmu-context-fault", domain);
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@ -907,15 +932,12 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
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dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
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dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
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cfg->irptndx, irq);
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cfg->irptndx, irq);
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cfg->irptndx = INVALID_IRPTNDX;
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cfg->irptndx = INVALID_IRPTNDX;
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goto out_free_context;
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}
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}
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smmu_domain->smmu = smmu;
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arm_smmu_init_context_bank(smmu_domain);
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return 0;
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return 0;
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out_free_context:
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out_unlock:
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__arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
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spin_unlock_irqrestore(&smmu_domain->lock, flags);
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return ret;
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return ret;
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}
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}
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@ -975,7 +997,6 @@ static void arm_smmu_free_ptes(pmd_t *pmd)
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{
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{
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pgtable_t table = pmd_pgtable(*pmd);
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pgtable_t table = pmd_pgtable(*pmd);
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pgtable_page_dtor(table);
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__free_page(table);
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__free_page(table);
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}
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}
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@ -1108,6 +1129,9 @@ static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
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void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
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void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
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struct arm_smmu_smr *smrs = cfg->smrs;
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struct arm_smmu_smr *smrs = cfg->smrs;
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if (!smrs)
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return;
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/* Invalidate the SMRs before freeing back to the allocator */
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/* Invalidate the SMRs before freeing back to the allocator */
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for (i = 0; i < cfg->num_streamids; ++i) {
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for (i = 0; i < cfg->num_streamids; ++i) {
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u8 idx = smrs[i].idx;
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u8 idx = smrs[i].idx;
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@ -1120,20 +1144,6 @@ static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
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kfree(smrs);
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kfree(smrs);
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}
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}
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static void arm_smmu_bypass_stream_mapping(struct arm_smmu_device *smmu,
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struct arm_smmu_master_cfg *cfg)
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{
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int i;
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void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
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for (i = 0; i < cfg->num_streamids; ++i) {
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u16 sid = cfg->streamids[i];
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writel_relaxed(S2CR_TYPE_BYPASS,
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gr0_base + ARM_SMMU_GR0_S2CR(sid));
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}
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}
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|
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static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
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static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
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struct arm_smmu_master_cfg *cfg)
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struct arm_smmu_master_cfg *cfg)
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{
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{
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@ -1160,23 +1170,30 @@ static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
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static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
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static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
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struct arm_smmu_master_cfg *cfg)
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struct arm_smmu_master_cfg *cfg)
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{
|
{
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|
int i;
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||||||
struct arm_smmu_device *smmu = smmu_domain->smmu;
|
struct arm_smmu_device *smmu = smmu_domain->smmu;
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||||||
|
void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
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||||||
|
|
||||||
/*
|
/*
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||||||
* We *must* clear the S2CR first, because freeing the SMR means
|
* We *must* clear the S2CR first, because freeing the SMR means
|
||||||
* that it can be re-allocated immediately.
|
* that it can be re-allocated immediately.
|
||||||
*/
|
*/
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||||||
arm_smmu_bypass_stream_mapping(smmu, cfg);
|
for (i = 0; i < cfg->num_streamids; ++i) {
|
||||||
|
u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
|
||||||
|
|
||||||
|
writel_relaxed(S2CR_TYPE_BYPASS,
|
||||||
|
gr0_base + ARM_SMMU_GR0_S2CR(idx));
|
||||||
|
}
|
||||||
|
|
||||||
arm_smmu_master_free_smrs(smmu, cfg);
|
arm_smmu_master_free_smrs(smmu, cfg);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
|
static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
|
||||||
{
|
{
|
||||||
int ret = -EINVAL;
|
int ret;
|
||||||
struct arm_smmu_domain *smmu_domain = domain->priv;
|
struct arm_smmu_domain *smmu_domain = domain->priv;
|
||||||
struct arm_smmu_device *smmu;
|
struct arm_smmu_device *smmu, *dom_smmu;
|
||||||
struct arm_smmu_master_cfg *cfg;
|
struct arm_smmu_master_cfg *cfg;
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
smmu = dev_get_master_dev(dev)->archdata.iommu;
|
smmu = dev_get_master_dev(dev)->archdata.iommu;
|
||||||
if (!smmu) {
|
if (!smmu) {
|
||||||
|
@ -1188,20 +1205,22 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
|
||||||
* Sanity check the domain. We don't support domains across
|
* Sanity check the domain. We don't support domains across
|
||||||
* different SMMUs.
|
* different SMMUs.
|
||||||
*/
|
*/
|
||||||
spin_lock_irqsave(&smmu_domain->lock, flags);
|
dom_smmu = ACCESS_ONCE(smmu_domain->smmu);
|
||||||
if (!smmu_domain->smmu) {
|
if (!dom_smmu) {
|
||||||
/* Now that we have a master, we can finalise the domain */
|
/* Now that we have a master, we can finalise the domain */
|
||||||
ret = arm_smmu_init_domain_context(domain, smmu);
|
ret = arm_smmu_init_domain_context(domain, smmu);
|
||||||
if (IS_ERR_VALUE(ret))
|
if (IS_ERR_VALUE(ret))
|
||||||
goto err_unlock;
|
return ret;
|
||||||
} else if (smmu_domain->smmu != smmu) {
|
|
||||||
|
dom_smmu = smmu_domain->smmu;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (dom_smmu != smmu) {
|
||||||
dev_err(dev,
|
dev_err(dev,
|
||||||
"cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
|
"cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
|
||||||
dev_name(smmu_domain->smmu->dev),
|
dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev));
|
||||||
dev_name(smmu->dev));
|
return -EINVAL;
|
||||||
goto err_unlock;
|
|
||||||
}
|
}
|
||||||
spin_unlock_irqrestore(&smmu_domain->lock, flags);
|
|
||||||
|
|
||||||
/* Looks ok, so add the device to the domain */
|
/* Looks ok, so add the device to the domain */
|
||||||
cfg = find_smmu_master_cfg(smmu_domain->smmu, dev);
|
cfg = find_smmu_master_cfg(smmu_domain->smmu, dev);
|
||||||
|
@ -1209,10 +1228,6 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
|
||||||
return -ENODEV;
|
return -ENODEV;
|
||||||
|
|
||||||
return arm_smmu_domain_add_master(smmu_domain, cfg);
|
return arm_smmu_domain_add_master(smmu_domain, cfg);
|
||||||
|
|
||||||
err_unlock:
|
|
||||||
spin_unlock_irqrestore(&smmu_domain->lock, flags);
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
|
static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
|
||||||
|
@ -1247,10 +1262,6 @@ static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
|
||||||
return -ENOMEM;
|
return -ENOMEM;
|
||||||
|
|
||||||
arm_smmu_flush_pgtable(smmu, page_address(table), PAGE_SIZE);
|
arm_smmu_flush_pgtable(smmu, page_address(table), PAGE_SIZE);
|
||||||
if (!pgtable_page_ctor(table)) {
|
|
||||||
__free_page(table);
|
|
||||||
return -ENOMEM;
|
|
||||||
}
|
|
||||||
pmd_populate(NULL, pmd, table);
|
pmd_populate(NULL, pmd, table);
|
||||||
arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd));
|
arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd));
|
||||||
}
|
}
|
||||||
|
@ -1626,7 +1637,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
|
||||||
|
|
||||||
/* Mark all SMRn as invalid and all S2CRn as bypass */
|
/* Mark all SMRn as invalid and all S2CRn as bypass */
|
||||||
for (i = 0; i < smmu->num_mapping_groups; ++i) {
|
for (i = 0; i < smmu->num_mapping_groups; ++i) {
|
||||||
writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(i));
|
writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i));
|
||||||
writel_relaxed(S2CR_TYPE_BYPASS,
|
writel_relaxed(S2CR_TYPE_BYPASS,
|
||||||
gr0_base + ARM_SMMU_GR0_S2CR(i));
|
gr0_base + ARM_SMMU_GR0_S2CR(i));
|
||||||
}
|
}
|
||||||
|
@ -1761,6 +1772,9 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
|
||||||
dev_notice(smmu->dev,
|
dev_notice(smmu->dev,
|
||||||
"\tstream matching with %u register groups, mask 0x%x",
|
"\tstream matching with %u register groups, mask 0x%x",
|
||||||
smmu->num_mapping_groups, mask);
|
smmu->num_mapping_groups, mask);
|
||||||
|
} else {
|
||||||
|
smmu->num_mapping_groups = (id >> ID0_NUMSIDB_SHIFT) &
|
||||||
|
ID0_NUMSIDB_MASK;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* ID1 */
|
/* ID1 */
|
||||||
|
@ -1794,11 +1808,16 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
|
||||||
* Stage-1 output limited by stage-2 input size due to pgd
|
* Stage-1 output limited by stage-2 input size due to pgd
|
||||||
* allocation (PTRS_PER_PGD).
|
* allocation (PTRS_PER_PGD).
|
||||||
*/
|
*/
|
||||||
|
if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
|
||||||
#ifdef CONFIG_64BIT
|
#ifdef CONFIG_64BIT
|
||||||
smmu->s1_output_size = min_t(unsigned long, VA_BITS, size);
|
smmu->s1_output_size = min_t(unsigned long, VA_BITS, size);
|
||||||
#else
|
#else
|
||||||
smmu->s1_output_size = min(32UL, size);
|
smmu->s1_output_size = min(32UL, size);
|
||||||
#endif
|
#endif
|
||||||
|
} else {
|
||||||
|
smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT,
|
||||||
|
size);
|
||||||
|
}
|
||||||
|
|
||||||
/* The stage-2 output mask is also applied for bypass */
|
/* The stage-2 output mask is also applied for bypass */
|
||||||
size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
|
size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
|
||||||
|
@ -1889,6 +1908,10 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
|
||||||
smmu->irqs[i] = irq;
|
smmu->irqs[i] = irq;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
err = arm_smmu_device_cfg_probe(smmu);
|
||||||
|
if (err)
|
||||||
|
return err;
|
||||||
|
|
||||||
i = 0;
|
i = 0;
|
||||||
smmu->masters = RB_ROOT;
|
smmu->masters = RB_ROOT;
|
||||||
while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
|
while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
|
||||||
|
@ -1905,10 +1928,6 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
|
||||||
}
|
}
|
||||||
dev_notice(dev, "registered %d master devices\n", i);
|
dev_notice(dev, "registered %d master devices\n", i);
|
||||||
|
|
||||||
err = arm_smmu_device_cfg_probe(smmu);
|
|
||||||
if (err)
|
|
||||||
goto out_put_masters;
|
|
||||||
|
|
||||||
parse_driver_options(smmu);
|
parse_driver_options(smmu);
|
||||||
|
|
||||||
if (smmu->version > 1 &&
|
if (smmu->version > 1 &&
|
||||||
|
|
|
@ -678,8 +678,7 @@ static int __init dmar_acpi_dev_scope_init(void)
|
||||||
andd->device_name);
|
andd->device_name);
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
acpi_bus_get_device(h, &adev);
|
if (acpi_bus_get_device(h, &adev)) {
|
||||||
if (!adev) {
|
|
||||||
pr_err("Failed to get device for ACPI object %s\n",
|
pr_err("Failed to get device for ACPI object %s\n",
|
||||||
andd->device_name);
|
andd->device_name);
|
||||||
continue;
|
continue;
|
||||||
|
|
|
@ -984,7 +984,7 @@ static int fsl_pamu_add_device(struct device *dev)
|
||||||
struct iommu_group *group = ERR_PTR(-ENODEV);
|
struct iommu_group *group = ERR_PTR(-ENODEV);
|
||||||
struct pci_dev *pdev;
|
struct pci_dev *pdev;
|
||||||
const u32 *prop;
|
const u32 *prop;
|
||||||
int ret, len;
|
int ret = 0, len;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* For platform devices we allocate a separate group for
|
* For platform devices we allocate a separate group for
|
||||||
|
@ -1007,6 +1007,12 @@ static int fsl_pamu_add_device(struct device *dev)
|
||||||
if (IS_ERR(group))
|
if (IS_ERR(group))
|
||||||
return PTR_ERR(group);
|
return PTR_ERR(group);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Check if device has already been added to an iommu group.
|
||||||
|
* Group could have already been created for a PCI device in
|
||||||
|
* the iommu_group_get_for_dev path.
|
||||||
|
*/
|
||||||
|
if (!dev->iommu_group)
|
||||||
ret = iommu_group_add_device(group, dev);
|
ret = iommu_group_add_device(group, dev);
|
||||||
|
|
||||||
iommu_group_put(group);
|
iommu_group_put(group);
|
||||||
|
|
|
@ -678,14 +678,16 @@ static struct iommu_group *iommu_group_get_for_pci_dev(struct pci_dev *pdev)
|
||||||
*/
|
*/
|
||||||
struct iommu_group *iommu_group_get_for_dev(struct device *dev)
|
struct iommu_group *iommu_group_get_for_dev(struct device *dev)
|
||||||
{
|
{
|
||||||
struct iommu_group *group = ERR_PTR(-EIO);
|
struct iommu_group *group;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
group = iommu_group_get(dev);
|
group = iommu_group_get(dev);
|
||||||
if (group)
|
if (group)
|
||||||
return group;
|
return group;
|
||||||
|
|
||||||
if (dev_is_pci(dev))
|
if (!dev_is_pci(dev))
|
||||||
|
return ERR_PTR(-EINVAL);
|
||||||
|
|
||||||
group = iommu_group_get_for_pci_dev(to_pci_dev(dev));
|
group = iommu_group_get_for_pci_dev(to_pci_dev(dev));
|
||||||
|
|
||||||
if (IS_ERR(group))
|
if (IS_ERR(group))
|
||||||
|
|
Loading…
Reference in a new issue