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ucc_geth: Fix interrupt coalescing size and alignment
The rx interrupt coalescing table alignment was "guessed" to be 4, but should be 64. The size should be 8 * number of queues + 4. Verified in the MPC8323E manual. Signed-off-by: Michael Barkowski <Michael.Barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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2 changed files with 3 additions and 4 deletions
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@ -2958,8 +2958,8 @@ static int ucc_geth_startup(struct ucc_geth_private *ugeth)
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/* Size varies with number of Rx queues */
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ugeth->rx_irq_coalescing_tbl_offset =
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qe_muram_alloc(ug_info->numQueuesRx *
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sizeof(struct ucc_geth_rx_interrupt_coalescing_entry),
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UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
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sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
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+ 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
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if (IS_MURAM_ERR(ugeth->rx_irq_coalescing_tbl_offset)) {
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ugeth_err
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("%s: Can not allocate DPRAM memory for"
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@ -867,8 +867,7 @@ struct ucc_geth_hardware_statistics {
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#define UCC_GETH_SCHEDULER_ALIGNMENT 4 /* This is a guess */
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#define UCC_GETH_TX_STATISTICS_ALIGNMENT 4 /* This is a guess */
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#define UCC_GETH_RX_STATISTICS_ALIGNMENT 4 /* This is a guess */
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#define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT 4 /* This is a
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guess */
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#define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT 64
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#define UCC_GETH_RX_BD_QUEUES_ALIGNMENT 8 /* This is a guess */
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#define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT 128 /* This is a guess */
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#define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4 /* This
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