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ARM: 6980/1: mmci: use StartBitErr to detect bad connections
Stresstesting insert/remove of SD-cards can trigger a StartBitErr. This made the driver to hang in forever waiting for a non ocurring data timeout. This bit and interrupt is documented in the original PL180 TRM, just never implemented until now. Signed-off-by: Ulf Hansson <ulf.hansson@stericsson.com> Reviewed-by: Linus Walleij <linus.walleij@stericsson.com> Reviewed-by: Jonas Aberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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2eb5af44b1
commit
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2 changed files with 6 additions and 1 deletions
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@ -582,6 +582,8 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
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data->error = -EILSEQ;
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data->error = -EILSEQ;
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} else if (status & MCI_DATATIMEOUT) {
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} else if (status & MCI_DATATIMEOUT) {
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data->error = -ETIMEDOUT;
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data->error = -ETIMEDOUT;
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} else if (status & MCI_STARTBITERR) {
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data->error = -ECOMM;
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} else if (status & MCI_TXUNDERRUN) {
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} else if (status & MCI_TXUNDERRUN) {
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data->error = -EIO;
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data->error = -EIO;
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} else if (status & MCI_RXOVERRUN) {
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} else if (status & MCI_RXOVERRUN) {
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@ -86,6 +86,7 @@
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#define MCI_CMDRESPEND (1 << 6)
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#define MCI_CMDRESPEND (1 << 6)
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#define MCI_CMDSENT (1 << 7)
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#define MCI_CMDSENT (1 << 7)
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#define MCI_DATAEND (1 << 8)
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#define MCI_DATAEND (1 << 8)
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#define MCI_STARTBITERR (1 << 9)
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#define MCI_DATABLOCKEND (1 << 10)
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#define MCI_DATABLOCKEND (1 << 10)
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#define MCI_CMDACTIVE (1 << 11)
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#define MCI_CMDACTIVE (1 << 11)
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#define MCI_TXACTIVE (1 << 12)
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#define MCI_TXACTIVE (1 << 12)
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@ -112,6 +113,7 @@
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#define MCI_CMDRESPENDCLR (1 << 6)
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#define MCI_CMDRESPENDCLR (1 << 6)
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#define MCI_CMDSENTCLR (1 << 7)
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#define MCI_CMDSENTCLR (1 << 7)
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#define MCI_DATAENDCLR (1 << 8)
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#define MCI_DATAENDCLR (1 << 8)
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#define MCI_STARTBITERRCLR (1 << 9)
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#define MCI_DATABLOCKENDCLR (1 << 10)
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#define MCI_DATABLOCKENDCLR (1 << 10)
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/* Extended status bits for the ST Micro variants */
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/* Extended status bits for the ST Micro variants */
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#define MCI_ST_SDIOITC (1 << 22)
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#define MCI_ST_SDIOITC (1 << 22)
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@ -127,6 +129,7 @@
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#define MCI_CMDRESPENDMASK (1 << 6)
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#define MCI_CMDRESPENDMASK (1 << 6)
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#define MCI_CMDSENTMASK (1 << 7)
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#define MCI_CMDSENTMASK (1 << 7)
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#define MCI_DATAENDMASK (1 << 8)
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#define MCI_DATAENDMASK (1 << 8)
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#define MCI_STARTBITERRMASK (1 << 9)
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#define MCI_DATABLOCKENDMASK (1 << 10)
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#define MCI_DATABLOCKENDMASK (1 << 10)
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#define MCI_CMDACTIVEMASK (1 << 11)
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#define MCI_CMDACTIVEMASK (1 << 11)
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#define MCI_TXACTIVEMASK (1 << 12)
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#define MCI_TXACTIVEMASK (1 << 12)
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@ -150,7 +153,7 @@
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#define MCI_IRQENABLE \
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#define MCI_IRQENABLE \
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(MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \
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(MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \
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MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \
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MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \
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MCI_CMDRESPENDMASK|MCI_CMDSENTMASK)
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MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_STARTBITERRMASK)
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/* These interrupts are directed to IRQ1 when two IRQ lines are available */
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/* These interrupts are directed to IRQ1 when two IRQ lines are available */
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#define MCI_IRQ1MASK \
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#define MCI_IRQ1MASK \
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